JPH1041207A - Method for forming resist pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a resist pattern in which a fine pattern is allowed to form by solving a problem of misalignment by self- alignment technique. SOLUTION: The sum of the amount of irradiating light A and reflected light B is, in the area where the area irradiated with the irradiating light A overlaps with the area on which a wiring film 12 is formed, set to a light quantity to which a photoresist 14 is sensitive, and, in the area where the area irradiated with the irradiating light A overlaps with the area on which the wiring film 12 is not formed, set to a light quantity to which the photoresist is not sensitive, thereby the resist pattern 14a is formed in self-alignment manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a resist pattern used in manufacturing a semiconductor device and the like.

[0002]

2. Description of the Related Art At present, a reduction projection exposure apparatus is used as an exposure apparatus in a semiconductor device manufacturing process. In this reduction projection exposure apparatus, light (ultraviolet light) that has passed through a reticle
Is reduced through a reduction optical system, so that high alignment accuracy can be realized in addition to high resolution. However, recent L
With the miniaturization of SI, higher alignment accuracy is required.

Conventionally, in the design of an LSI, a matching margin is provided depending on the matching accuracy of the device. For example, as shown in FIG.
When the (via holes) are overlapped, the lower wiring is designed to be widened in the vertical and horizontal directions by an amount corresponding to the alignment error so that the connection hole 52 can be accommodated in the lower wiring even if misalignment occurs.

[0004] However, the area with a margin for alignment is originally a useless area, and has been regarded as a problem for further high integration. In addition, since the distance between the wirings is narrowed at the place where the alignment is sufficient, there is also a performance problem of RC delay due to an increase in the capacitance between the wirings.

However, it is impossible to eliminate misalignment as long as the alignment is performed using the alignment mark.
Therefore, a method has been proposed in which the upper layer and the lower layer are self-aligned in terms of process. This method will be described with reference to an example of self-alignment alignment between the upper embedded wiring and the lower connection hole (see FIG. 16).

First, an insulating layer 62 is formed on a base 61,
An RIE stop layer 63 having an RIE selectivity with respect to the insulating layer 62 is formed. Then, the connection hole portion of the stop layer 63 is selectively removed including the alignment margin (a). Next, an insulating layer 64 is further formed on the stop layer 63,
A wiring resist pattern 65 is formed on the insulating layer 64 (b). Next, RIE is performed to form a wiring groove. At this time, the etching stops at the RIE stop layer 63 except for the connection hole portion, but since the stop layer is removed at the connection hole portion, the etching proceeds only in the portion overlapping with the wiring pattern, and the wiring groove is formed. (C). Finally, wiring is completed by filling the groove and the connection hole with a wiring metal (not shown).

Although the above method is limited to the buried wiring, the upper wiring and the lower connection hole can be aligned in a self-aligned manner. However, in the scaling rule of the LSI, the lower layer pattern needs to be finer, and the scaling rule is relaxed in the upper layer pattern. Therefore, it is necessary to accurately match the upper layer pattern with the fine lower layer pattern. Therefore, it is difficult to form a completely densified pattern even in the above method.

On the other hand, in the process of manufacturing a MOS transistor, there is a case where a film on a lower structure on which a gate is formed is patterned. Even in such a case, it is difficult to process this film without misalignment with the gate, so that a margin for alignment is required, which hinders high integration of LSI.

[0009]

As described above, conventionally, it has been difficult to form a fine pattern due to the problem of misalignment, which has hindered high integration and high speed of LSI. An object of the present invention is to provide a method of forming a resist pattern capable of forming a fine pattern by solving the problem of misalignment by a self-aligned method.

[0010]

According to the present invention, there is provided a method of forming a resist pattern, comprising forming a resist on a light transmitting film covering a lower structure comprising a plurality of regions having different reflectivities, and irradiating the resist with light. The resist pattern is formed by utilizing the difference in the reflection intensity of the lower structure.

Since the resist pattern is formed by utilizing the difference in the reflection intensity of the lower structure, the problem of misalignment can be essentially eliminated, and a close-packed pattern self-aligned with the lower structure can be formed. It is possible to do.

In the method of forming a resist pattern according to the present invention, a resist is formed on a light-transmitting film covering a lower structure having a first region and a second region having different reflectances, and the resist is irradiated with light. The sum of the exposure amount of the resist by the irradiation light and the exposure amount of the resist by the reflected light from the lower structure is defined as the exposure amount that exposes the resist in the first region, and the exposure amount that does not expose the resist in the second region. Thus, a resist pattern is formed.

By making the reflectivity different between the first region and the second region, the resist is exposed in the first region and the resist is not exposed in the second region. Can be formed.
Therefore, the problem of misalignment can be essentially eliminated, and a close-packed pattern that is self-aligned with the lower structure can be formed.

In the method of forming a resist pattern according to the present invention, a resist is formed on a light transmitting film covering a lower structure having a first region and a second region having different reflectivities, and the resist is irradiated with light. By utilizing a difference in reflection intensity between the first area and the second area, an area where an irradiation area irradiated with light overlaps with the first area is selectively exposed.

Since the overlapping area between the irradiation area and the first area is selectively exposed by utilizing the difference in the reflection intensity between the first area and the second area, a pattern which is self-aligned with the first area is formed. Can be formed. Therefore, the problem of misalignment can be essentially eliminated, and a close-packed pattern that is self-aligned with the lower structure can be formed.

Each of the above methods can be applied, for example, when a contact hole is formed in a self-aligned manner with a lower wiring. That is, a resist pattern is formed in a self-aligned manner with respect to the lower wiring by the above method, and a contact hole can be formed in a self-aligned manner with the lower wiring using the resist pattern.

The resist is usually a positive resist, but may be a negative resist. Further, the method of forming a resist pattern according to the present invention includes forming a resist on a lower structure including a plurality of regions having different light reflection states, and utilizing the irregular reflection in the lower structure when the resist is irradiated with light. It forms a pattern.

If the lower structure has a planarized region and a non-planarized region due to a step or the like, light transmitted through the resist is easily irregularly reflected by the non-planarized region. As a result, only the resist in the non-planarized region can be selectively exposed. Therefore, a resist pattern can be formed in a self-aligned manner with respect to the flattened region or the non-flattened region.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of an embodiment of the present invention will be described. FIG. 2 shows the wavelength dependence of the reflectance of Al, and FIG. 3 shows an example of the dissolution rate characteristics of a positive resist. In FIG. 3, the vertical axis shows the dissolution rate in the developer, and the horizontal axis shows the irradiation light amount.

As can be seen from FIG. 2, Al has a high reflectance of about 90% or more even for ultraviolet light such as the wavelength (193 nm) of an ArF excimer laser. Also,
As can be seen from FIG. 3, the dissolution rate of the positive resist rapidly increases at a specific exposure dose.

In the case of the positive resist shown in FIG.
The resist is hardly exposed only by irradiating the resist with the irradiation light of J / cm ² . However, when there is an Al pattern on the lower layer side of the resist, light transmitted through the resist is reflected on the Al surface and is absorbed by the resist again. Therefore, in a region where the Al pattern and the irradiation light overlap, the irradiation light and the reflection light from the Al surface are added, which is substantially equivalent to irradiation of light of about 19 mJ / cm ² . As shown in FIG. 3, the resist is almost exposed at this irradiation amount, so that only the resist immediately above the Al pattern can be selectively exposed. As described above, at a certain threshold, the resist is exposed at an exposure amount higher than the threshold value, and the resist is not exposed at an exposure amount lower than the threshold value.

With the above matters in mind, specific embodiments of the present invention will be described below. FIG. 1 is a diagram showing a first embodiment of the present invention.

In FIG. 1A, reference numeral 11 denotes an undersubstrate made of a silicon substrate and an insulating film, etc., 12 denotes a wiring film using Al, and 13 denotes an interlayer insulating film (highly transparent to irradiation light such as CVD silicon oxide). , 14 is a positive photoresist, 15 is a photomask (15a is a light transmitting part, 15b is a light shielding part). As shown in the figure,
The pattern width of the irradiation light projected onto the photoresist 14 is wider than the pattern width of the wiring 12. In addition,
Although the drawing is drawn as a 1: 1 exposure for convenience, it is actually a reduced exposure using a reduced projection exposure apparatus.

The irradiation light A transmitted through the photomask 15 is
A part thereof is absorbed by the photoresist 14, and the rest reaches the upper surface of the wiring film 12 and the upper surface of the base substrate 11 through the photoresist 14. The light that reaches the upper surface of the wiring film 12 is reflected and becomes reflected light B, but the light that reaches the upper surface of the base substrate 11 is hardly reflected.

FIG. 4A is a diagram showing the distribution of the light amounts of the irradiation light A and the reflected light B, and FIG. 4B is the total of the irradiation light A and the reflected light B, that is, the irradiation light A and the reflected light B. FIG. 4 is a diagram showing a distribution of an exposure amount of a photoresist 14 by light B. The vertical axis indicates the light amount, and the horizontal axis indicates the position in the left-right direction in FIG. The dotted line in FIG.
Indicates the threshold value of the exposure amount that is exposed and the exposure amount that is not exposed. By appropriately selecting the light amount of the irradiation light, the sum of the exposure amount of the resist by the irradiation light A and the exposure amount of the resist by the reflected light B is determined by the irradiation region of the irradiation light A and the region where the wiring film 12 is formed ( In a region where the photoresist 14 is exposed, the photoresist 14 is exposed in an area where the photoresist 14 is exposed, and in a region where the wiring A is irradiated and the region where the wiring film 12 is not formed (the second region), the photoresist 14 is exposed.
Can be set to a non-exposed exposure amount.

After the step of FIG. 1A is completed, the photoresist is developed, and the area irradiated with the irradiation light A and the wiring film 12 are removed.
The photoresist is selectively removed only in the region where the photoresist pattern 14 overlaps with the region where the pattern is formed, and the photoresist pattern 14 is self-aligned with the wiring film 12 as shown in FIG.
a is formed. Then, the interlayer insulating film 13 is etched using the photoresist pattern 14a as a mask,
A contact hole 13a is formed in self-alignment with the wiring film 12 (FIG. 1C). The contact hole 13a
May be tapered as shown in FIG.

As apparent from the above description, the resist pattern 14a is self-aligned with the wiring film 12.
In order to form, the irradiation light A is applied to the photoresist 14,
It is desirable that the reflected light B be perpendicularly incident on the interlayer insulating film 13 and the wiring film 12 and be reflected perpendicularly to these films. In order to satisfy such a condition, at least in the region irradiated with the irradiation light A, the wiring film 1
2 and the upper surface of the interlayer insulating film 13 are desirably perpendicular to the irradiation light A. Therefore, it is desirable that the upper surface of the wiring film 12 and the upper surface of the interlayer insulating film 13 are flattened.

In the first embodiment, the photoresist 14 is selectively exposed only to the region where the irradiation region of the irradiation light A and the region where the wiring film 12 is formed are selectively exposed.
2, a contact hole 13a can be formed in a self-aligned manner. Therefore, there is no need to provide a matching margin between the pattern of the wiring layer 12 and the pattern of the contact hole 13a, and the wiring layer 12 can be made denser.

FIGS. 6 and 7 show a second embodiment of the present invention. In the present embodiment, an antireflection film 16 is formed on a base substrate 11, and other configurations are the same as those of the first embodiment shown in FIG. Therefore, the formation principle of the resist pattern and the like are the same as those of the first embodiment, and the same operation and effects as those of the first embodiment can be obtained. FIG. 6 shows an example in which an antireflection film 16 is formed on the entire surface of the underlying substrate 11, and FIG.
The anti-reflection film 16 is also formed on the portion where no 2 is formed.

In this embodiment, since the antireflection film 16 is provided, the reflection light from the region where the wiring film 12 is formed and the wiring film 12 are formed as compared with the first embodiment shown in FIG. The contrast with the reflected light from the non-reflective area (the area where the antireflection film is formed) can be further increased.

FIG. 8 shows a third embodiment of the present invention. In the present embodiment, a method similar to that of the first embodiment is applied to formation of a contact hole 13a for connecting the wiring film 12 and the wiring film 17. Therefore, the formation principle of the resist pattern and the like are the same as those of the first embodiment, and the same operation and effects as those of the first embodiment can be obtained.

In the present embodiment, the contact hole 13a is selectively formed only in the intersection area between the irradiation area X of the irradiation light and the wiring film 12.
Is formed. That is, the contact holes 13a are formed in a self-aligned manner with respect to the wiring film 12. Therefore, there is no need to provide a matching margin between the wiring layer 12 and the contact hole 13a, and the wiring layer 12 can be made denser.

Although the anti-reflection film is not provided in the example shown in FIG. 8, an anti-reflection film may be provided similarly to the second embodiment shown in FIGS. In the above embodiments, Al is used for the wiring film 13.
Materials such as u, W, WSi, and polysilicon that have a higher reflectance to the irradiation light than the reflectance of the underlying substrate 11 can be used.

FIG. 9 shows a fourth embodiment of the present invention. Since the basic principle of this embodiment is the same as that of the first embodiment, items that can be easily analogized from the first embodiment will be referred to the first embodiment, and description thereof will be omitted.

In FIG. 9A, reference numeral 21 denotes a base substrate;
2 is a wiring film, 23 is an interlayer insulating film (a film having a high transmittance to irradiation light is used), 24 is a positive photoresist, 25 is a photomask (25a is a light transmitting portion, 25b is a light shielding portion) ) And 26 are antireflection films. Anti-reflection film 26
For example, a carbon film or a titanium nitride film can be used.

The irradiation light A transmitted through the photomask 25 is
A part thereof is absorbed by the photoresist 24, and the rest reaches the upper surface of the base substrate 21 and the upper surface of the antireflection film 26 through the photoresist 24. The light that reaches the upper surface of the base substrate 21 is reflected and becomes reflected light B, but the light that reaches the upper surface of the antireflection film 26 is hardly reflected.

FIG. 10 is a view showing the distribution of the exposure amount absorbed by the photoresist 24 by the irradiation light A and the reflected light B. The vertical axis indicates the light amount, and the horizontal axis indicates the position in the left-right direction in FIG. Dotted lines indicate threshold values of the exposure amount at which the photoresist 24 is exposed and the exposure amount at which the photoresist 24 is not exposed. By appropriately selecting the amount of irradiation light,
The sum of the amount of exposure of the resist by the irradiation light A and the amount of exposure of the resist by the reflected light B is determined in the region where the irradiation region of the irradiation light A and the region where the antireflection film 26 is not formed (the first region) overlap. Exposure amount to expose the photoresist 24,
In the region where the irradiation region of the irradiation light A and the region where the antireflection film 26 is formed (the second region) overlap, the exposure amount that does not expose the photoresist 24 can be set.

After the step of FIG. 9A is completed, when the photoresist is developed, the photoresist is selectively applied only to the overlapping area of the irradiation area of the irradiation light A and the area where the antireflection film 26 is not formed. Then, as shown in FIG. 9B, a photoresist pattern 24a is formed in a self-aligned manner with respect to the groove between the wiring films 22. Then, using the photoresist pattern 24a as a mask, the interlayer insulating film 2 is formed.
3 is etched to form a contact hole 23a formed in a self-aligned manner with respect to the groove between the wiring films 22 (FIG. 9C). By depositing the insulating film and anisotropic etching, it is possible to selectively form the insulating film on the inner side wall of the contact hole 23a. The contact hole 23a
May be tapered as shown in FIG.

FIG. 12 shows a fifth embodiment of the present invention. The basic principle of this embodiment is the same as that of the first embodiment and the fourth embodiment. Therefore, matters that can be easily analogized from the first embodiment and the fourth embodiment will be referred to, and the description will be omitted. I do.

In FIG. 12A, reference numeral 31 denotes a base substrate,
32 is a film having a low reflectance (for example, a silicon nitride film);
Is an insulating film (a film having a high transmittance to irradiation light is used), 34 is a positive photoresist, 35 is a photomask (35a is a light transmitting portion, 35b is a light shielding portion), and 36 is a reflectivity. It is a high film (for example, a metal film of Al, Cu, W, etc.).

As described in the first and fourth embodiments, by appropriately selecting the amount of irradiation light, the amount of exposure of the resist by the irradiation light A and the amount of the resist by the reflected light B from the film 36 can be improved. In the region where the irradiation region of the irradiation light A and the region where the low-reflectance film 32 is not formed (the first region) overlap the photoresist 34
Can be set as an exposure amount that exposes the photoresist 34 in an area where the irradiation area of the irradiation light A and the area (the second area) where the film 32 having a low reflectance is formed overlap. .

The steps shown in FIGS. 12A, 12B and 12C can be easily inferred from the fourth embodiment shown in FIG. FIG. 13 is a modification of the fifth embodiment. This modification example is based on the base substrate 3
A high-reflectance film 36 is formed only on a portion of the substrate 1 where the low-reflectance film 32 is not formed, and the other configuration is the same as that of FIG.

FIG. 14 shows a sixth embodiment of the present invention. In the first to fifth embodiments, a positive photoresist is used. In this embodiment, a negative photoresist is used. Other basic principles are the first
Since this embodiment is the same as the embodiment and the like, items that can be easily inferred from the first embodiment and the like will be referred to, and description thereof will be omitted.

In FIG. 14A, reference numeral 41 denotes a base substrate,
42 is a film having a high reflectance, 43 is an insulating film (a film having a high transmittance to irradiation light is used), 44 is a negative photoresist, 45 is a photomask (45a is a light transmitting portion,
5b is a light shielding part).

As described in the first embodiment, the sum of the amount of exposure of the resist by the irradiation light A and the amount of exposure of the resist by the reflected light B is determined by appropriately selecting the amount of irradiation light. In the region where the irradiation region of the irradiation light A and the region (the first region) where the film 42 having a high reflectance is formed overlap, the exposure amount for exposing the photoresist 44 is used. In an area where the high film 42 is not formed (the second area), a photoresist 44 is formed.
Can be set to a non-exposed exposure amount.

Therefore, when the photoresist is developed, the photoresist is selectively left only in the region where the irradiation region of the irradiation light A and the region where the film 42 with high reflectivity are formed are selectively left, as shown in FIG. As shown in FIG.
2 in a self-aligned manner with the photoresist pattern 44a.
Is formed.

FIGS. 17 and 18 show a seventh embodiment of the present invention. In the present embodiment, the present invention
Applied to the MOS transistor portion of
According to the same principle as in the embodiment and the like, the positive type resist on the region (gate region and element isolation region) other than the source / drain region is selectively exposed, and the resist pattern is selectively formed only on the source / drain region. To form. Hereinafter, the manufacturing steps will be described according to steps (a) to (f).

First, an isolation oxide film 72, a gate oxide film 73 and a gate electrode 74 are formed on a silicon substrate 71. Although a silicon nitride film 75 is preferably formed on the gate electrode 74, a film using a material other than silicon nitride may be formed, or such a film may not be formed. Subsequently, a silicon oxide film is deposited on the entire surface using TEOS / ozone CVD, and the silicon oxide film 76 is left on the side wall of the gate electrode 74 by reactive ion etching. Subsequently, A is added to the source / drain region 77.
Impurities such as s, P, and B are ion-implanted, and a heat treatment for activation is performed at 850 ° C. Instead of performing the impurity ion implantation step, the surface of the silicon substrate in the source / drain region is fixed to a certain depth (for example, when the gate width is 0.1 mm) by using a method capable of selectively etching silicon such as chemical dry etching. In the case of 1 μm, the etching depth is set to, for example, about 0.03 μm.) (FIG. 17A).

Next, an amorphous silicon film doped with impurities is deposited on the entire surface by using a CVD method, a sputtering method or the like. For example, when boron ions are implanted in the above step (a), an amorphous silicon film is deposited at 350 ° C. using a diborane / disilane gas containing the same kind of impurity element. Subsequently, in order to monocrystallize the amorphous silicon film, a heat treatment is performed at 600 ° C. for about 2 hours in a nitrogen atmosphere to form an impurity-containing silicon film 78. As long as the heat treatment temperature does not hinder other steps, the heat treatment may be performed at a higher temperature for a shorter time or at a temperature of 600 ° C. or lower for a longer time. Note that the above step (a)
Instead of performing the impurity ion implantation process at
Even in the case where the step of removing the silicon substrate surface in the drain region is adopted, an amorphous silicon film doped with impurities may be deposited and monocrystallized in the same manner as described above. In this case, an amorphous silicon film is directly deposited on the removed region of the silicon substrate, and is monocrystallized by heat treatment to form a source / drain (FIG. 17).
(B)).

Next, a positive resist 79 is applied on the impurity-containing silicon film 78 and is exposed. In the region where the gate electrode 74 and the element isolation oxide film 72 are formed, most of the light that reaches these regions is reflected, and accordingly, the resist 79 is exposed to that much. On the other hand, the light that has reached the source / drain 77 has the above-described nature because the impurity-containing silicon film 78 and the source / drain 77 are formed of the same type of film, and there is virtually no interface at the boundary between these films. Does not reflect on Therefore, the resist 79 is formed on the region where the gate electrode 74 and the element isolation oxide film 72 are formed.
Is exposed, and the resist 79 is not exposed on the region where the source / drain 77 is formed (FIG. 17C).

Next, the resist 79 is developed to selectively form a resist pattern 79a only on the region where the source / drain 77 is formed (FIG. 18D). Next, using the resist pattern 79a as a mask, the impurity-containing silicon film 78 is anisotropically etched by reactive ion etching to form a source / drain electrode 78a in self-alignment with the source / drain 77. Since the source / drain electrodes 78a formed in this manner are formed in a self-aligned manner with respect to the gate electrode 74, there is no need to consider an alignment margin. Even after the formation of the gate electrode 74, the width of the gate electrode can be reduced. (FIG. 18E).

Next, an interlayer insulating film 80 is deposited on the entire surface by using TEOS / ozone CVD or BPSG, and a contact hole 80a is formed by reactive ion etching or the like. Then, a wiring 81 using aluminum or the like is formed in the contact hole 80a. As shown in the figure, if the contact hole 80a is formed to be shifted outward from the pattern of the gate electrode 74, short circuit between the gate electrode 74 and the wiring 81 due to misalignment can be prevented. Also, in this case, the wiring 8
1 is formed on the element isolation oxide film 72, so that the wiring capacitance can be reduced accordingly (FIG. 18).
(F)).

According to the above-described manufacturing method, the source / drain electrodes 78a are formed in a self-aligned manner with respect to the gate electrode 74. Therefore, it is not necessary to consider a margin for alignment. The source / drain electrode 78a can be formed by processing.

FIGS. 19 and 20 show an eighth embodiment of the present invention. In this embodiment, as in the seventh embodiment, the present invention is applied to a MOS transistor portion of an LSI. However, it is slightly different in principle from the first embodiment and the like, and the negative type resist on the source / drain regions is selectively exposed by using diffuse reflection from the lower structure, and selectively exposed only on the source / drain regions. A resist pattern is formed on the substrate. Hereinafter, steps (a) to
The manufacturing process will be described according to (f).

First, an isolation oxide film 92, a gate oxide film 93, and a gate electrode 94 are formed on a silicon substrate 91. Although a silicon nitride film 95 is preferably formed on the gate electrode 94, a film using a material other than silicon nitride may be formed, or such a film may not be formed. Subsequently, a silicon oxide film is deposited on the entire surface using TEOS / ozone CVD, and the silicon oxide film 96 is left on the side wall of the gate electrode 94 by reactive ion etching. Subsequently, A is added to the source / drain region 97.
Impurities such as s, P, and B are ion-implanted, and a heat treatment for activation is performed at 850 ° C. Instead of performing the impurity ion implantation step, the surface of the silicon substrate in the source / drain region is fixed to a certain depth (for example, when the gate width is 0.1 mm) by using a method capable of selectively etching silicon such as chemical dry etching. In the case of 1 μm, the etching depth is set to, for example, about 0.03 μm.) (FIG. 19A).

Next, an amorphous silicon film doped with impurities is deposited on the entire surface by using a CVD method, a sputtering method or the like. For example, when boron ions are implanted in the above step (a), an amorphous silicon film is deposited at 350 ° C. using a diborane / disilane gas containing the same kind of impurity element. Subsequently, in order to monocrystallize the amorphous silicon film, a heat treatment is performed at 600 ° C. for about 2 hours in a nitrogen atmosphere to form an impurity-containing silicon film 98. As long as the heat treatment temperature does not hinder other steps, the heat treatment may be performed at a higher temperature for a shorter time or at a temperature of 600 ° C. or lower for a longer time. The upper surface of the impurity-containing silicon film 98 thus formed reflects the shape of the lower structure. That is, in the region where the gate electrode 94 and the element isolation oxide film 92 are formed, the upper surface of the impurity-containing silicon film 98 is substantially flat, but in the region where the source / drain 97 is formed, the gate electrode 94 and the element isolation oxide film 92 are formed. The step becomes uneven. In addition,
In the case where the step of removing the surface of the silicon substrate in the source / drain region is employed instead of performing the impurity ion implantation step in the above step (a), an impurity-doped amorphous silicon film is deposited in the same manner as described above. Then, this may be single-crystallized. In this case, an amorphous silicon film is directly deposited on the removed region of the silicon substrate, and is monocrystallized by heat treatment to form a source / drain. Note that a metal film or an alloy film can be used instead of the impurity-containing silicon film 98 (FIG. 19).
(B)).

Next, a negative resist 99 is applied on the impurity-containing silicon film 98 and is exposed. In the region where the source / drain 97 is formed, the upper surface of the impurity-containing silicon film 98 is uneven, so that the light that reaches this region is irregularly reflected, and the resist 99 is accordingly exposed more. On the other hand, in the region where the gate electrode 94 and the element isolation oxide film 92 are formed, the upper surface of the impurity-containing silicon film 98 is almost flat, so that light reaching this region is hardly diffusely reflected. Therefore, the resist 99 is exposed on the region where the source / drain 97 is formed, and the gate electrode 9 is exposed.
The resist 99 can be prevented from being exposed on the region where the element 4 and the element isolation oxide film 92 are formed (FIG. 19).
(C)).

Next, the resist 99 is developed to selectively form a resist pattern 99a only on the region where the source / drain 97 is formed (FIG. 20D). Next, using the resist pattern 99a as a mask, the impurity-containing silicon film 98 is anisotropically etched by reactive ion etching to form a source / drain electrode 98a in self-alignment with the source / drain 97. Since the source / drain electrodes 98a formed in this manner are formed in a self-aligned manner with respect to the gate electrode 94, there is no need to consider a margin for alignment. 20 (e).

Next, an interlayer insulating film 100 is deposited on the entire surface by using TEOS / ozone CVD or BPSG, etc.
Contact hole 100a by reactive ion etching or the like
To form Then, a wiring 101 using aluminum or the like is formed in the contact hole 100a. As shown in the drawing, if the contact hole 100a is formed to be shifted outward from the pattern of the gate electrode 94, short circuit between the gate electrode 94 and the wiring 101 due to misalignment can be prevented. In addition, since a part of the wiring 101 is formed on the element isolation oxide film 92, the wiring capacitance can be reduced accordingly (FIG. 20F).

According to the above manufacturing method, since the source / drain electrodes 98a are formed in a self-aligned manner with respect to the gate electrode 94, it is not necessary to consider a margin for alignment. The source / drain electrodes 98a can be formed by processing.

The characteristics of the device fabricated by the method of the present embodiment were evaluated by measuring the delay time of a CMOS ring oscillator. As a result, the delay time is reduced to 15 psec / sta due to the decrease
was ge. A delay time of 30 psec / s in a ring oscillator using an element with a normal structure created according to the 0.2 μm rule
tage, and it was confirmed that the operation speed was greatly improved. In addition, other than the embodiment described above, the present invention can be variously modified and implemented without departing from the gist thereof.

[0062]

According to the present invention, it is possible to form a pattern which is self-aligned with the lower structure, so that a problem of misalignment can be solved and a fine pattern can be formed. Therefore, when applied to a semiconductor integrated circuit, the degree of integration can be greatly improved, the operation speed can be improved, and the manufacturing process can be further shortened.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a first embodiment of the present invention.

FIG. 2 is a diagram showing the wavelength dependence of the reflectance of Al.

FIG. 3 is a diagram showing an example of a dissolution rate characteristic of a positive resist.

4A and 4B are diagrams according to the first embodiment of the present invention, in which FIG. 4A shows a distribution of light amounts of irradiation light A and reflected light B, and FIG. 4B shows a total light amount of irradiation light A and reflected light B; FIG.

FIG. 5 is a diagram showing another example of the first embodiment of the present invention.

FIG. 6 is a diagram showing an example of a second embodiment of the present invention.

FIG. 7 is a diagram showing another example of the second embodiment of the present invention.

FIG. 8 is a diagram showing an example of a third embodiment of the present invention.

FIG. 9 is a diagram showing an example of a fourth embodiment of the present invention.

FIG. 10 is a diagram according to a fourth embodiment of the present invention, wherein irradiation light A
FIG. 7 is a diagram showing a distribution of a total light amount of reflected light B and reflected light B;

FIG. 11 is a view showing another example of the fourth embodiment of the present invention.

FIG. 12 is a view showing an example of a fifth embodiment of the present invention.

FIG. 13 is a view showing another example of the fifth embodiment of the present invention.

FIG. 14 is a view showing an example of a sixth embodiment of the present invention.

FIG. 15 is a diagram showing an example of a conventional technique.

FIG. 16 is a diagram showing another example of the related art.

FIG. 17 is a view showing an example of a seventh embodiment of the present invention.

FIG. 18 is a view showing an example of a seventh embodiment of the present invention.

FIG. 19 is a view showing an example of the eighth embodiment of the present invention.

FIG. 20 is a diagram showing an example of the eighth embodiment of the present invention.

[Explanation of symbols]

13, 23, 33, 43: Light transmitting film 14, 24, 34, 44, 79, 99: Resist 14a, 24a, 34a, 44a, 79a, 99a: Resist pattern

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasuhiko Sato 1 Tokoba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture

Claims (4)

[Claims] 1. A resist pattern is formed on a light-transmitting film covering a lower structure including a plurality of regions having different reflectivities, and a resist pattern is formed by utilizing a difference in reflection intensity of the lower structure when the resist is irradiated with light. Forming a resist pattern. 2. A first region and a second region having different reflectances from each other.
A resist is formed on a light transmitting film covering a lower structure having a region, and a sum of an exposure amount of the resist by irradiation light when the resist is irradiated with light and an exposure amount of the resist by reflected light from the lower structure is calculated. Forming a resist pattern by exposing the resist to light in the first region and exposing the resist to light in the second region. 3. A first region and a second region having different reflectances from each other.
A resist is formed on a light transmitting film covering a lower structure having a region, and light is irradiated by utilizing a difference in reflection intensity between the first region and the second region when the resist is irradiated with light. A method for forming a resist pattern, comprising selectively exposing an area where an irradiation area and the first area overlap each other. 4. A resist is formed on a lower structure including a plurality of regions having different light reflection states, and a resist pattern is formed by utilizing irregular reflection of the lower structure when the resist is irradiated with light. Method of forming a resist pattern.