JP3353473B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a wiring layer having a fine pattern, and a surface of the wiring layer is not exposed during a flattening process. The present invention relates to a method for manufacturing a semiconductor device having an interlayer insulating film which is free from voids and has excellent flatness.

[0002]

2. Description of the Related Art In recent years, with the integration of VLSIs, in logic devices, in particular, wiring structures have been miniaturized and multilayered. In the current development of devices for semiconductor integrated circuits, design rules in the sub-half-micron region are required, and accordingly, fine processing technology for wiring is required. In order to realize a desired design rule, a state-of-the-art photolithography technology is essential in the manufacturing process. The state-of-the-art stepper (reduction projection exposure machine) currently used uses KrF excimer laser light (248 nm) as a light source, and has a 0.37-0.
A lens with an NA of about 50 is mounted.

A stepper uses light of a single wavelength as an exposure light source. It is widely known that when exposure is performed at a single wavelength, a phenomenon called a standing wave effect occurs.
As a result, the amount of light absorbed by the resist changes depending on the resist film thickness. The amount of absorbed light is the energy that causes the resist to undergo a photoreaction. Further, the degree of the change in the amount of absorbed light varies depending on the type of the base substrate. That is, the degree of change in the amount of absorbed light is determined by the complex amplitude reflectance (R) taking into account multiple interference determined by the optical constants (n, k) of the base and the optical constants (n, k) of the resist (R is a real part). And an imaginary part).

[0004] In order to suppress the change in the amount of absorbed light due to the standing wave effect, a Si _x
O _Y N _Z or Si _X N _Y film antireflection film is formed, such as, on the antireflection film, and spin-coated photoresist, and exposed by an excimer stepper, the resist patterning technique used to form a resist pattern Have been.

In this resist patterning technique, a base to be processed is a metal wiring material, for example, Al, Al--Si, A
1-Si-Cu, Al-Cu, etc. can be applied, and by using this technique, it is possible to pattern the wiring design rule in the sub-half micron region.

[0006] In order to increase the number of metal wiring layers, a technique for flattening the base is indispensable. In particular, the wiring in the upper layer portion directly reflects the influence of the step of the base, and in a portion that is not completely flattened, defects such as disconnection of the metal wiring and voids occur. In order to avoid these problems, various flattening techniques have been proposed, and a resist etch-back method is one of them.

Hereinafter, a process for flattening the wiring layer using the resist etch-back method will be described with reference to FIGS. First, as shown in FIG. 15A, the lower wiring 1 is patterned based on the design. next,
A first plasma (TEO) TEO is placed on the lower wiring 1.
S (Tetraethyloxysilane or Tetraethylorthosilica
te) The film 2 is formed by CVD (Chemical Vapor Deposition) for about 30 minutes.
0 nm is formed. This is because, functions as a buffer layer, O ₃ -TEOS by silicon oxide film to be formed later (hereinafter, referred to as O ₃ -TEOS / NSG film) and, further, does not leave the side wall of the contact hole to be formed later Of the O ₃ -TEOS / NSG film having high hygroscopicity
This is to prevent the influence (corrosion, etc.) on the l wiring and to alleviate the underlayer dependence of the O ₃ -TEOS / NSG film formation.

Next, on the first plasma TEOS film 2,
O ₃ -TEOS / NSG film 3 is formed by CVD to about 500 nm.
Form. This is used to fill a narrow space between wirings without generating voids. Furthermore, this O
_{The use of the 3-} TEOS / NSG film 3 enables not only local planarization but also global planarization.

Next, a photoresist 4 is applied, followed by etch back. Then, as shown in FIG. 15B, the etched back photoresist 4 becomes O ₃ -T
The EOS / NSG film 3 remains only in the portion where the step is severe, and O
The local step of the _3- TEOS / NSG film 3 is reduced. Next, in FIG. 15B, a resist patterning 5 for dummy wiring is formed. This is used for forming an insulating layer of a dummy pattern which is essential for global flattening later.

Subsequently, using the patterned photoresist 5 as a mask, the O ₃ -TEOS / NSG film 3
Is removed by RIE (Reactive Ion Etching). The RIE amount at this time is set to be equal to the wiring film thickness, and as shown in FIG. 16C, the generated dummy pattern insulating layer 6 (O ₃ -TEOS / NSG) and the device surface height Will be aligned.

Next, as shown in FIG. 16D, a second plasma TEOS film 7 is formed by CVD, and subsequently, a SOG (spin-on glass) film 8 is coated. The second plasma TEOS film 7 functions as a stopper in the subsequent SOG etch-back, and has a role of improving the adhesion between the SOG film 8 and the underlying O ₃ -TEOS / NSG film 2. Have.

Finally, as shown in FIG.
By plasma CVD of the plasma TEOS film 9, complete planarization is performed. Thereafter, a contact hole is formed, and an upper wiring is formed thereon. The third plasma TEOS film 9 is necessary for ensuring the withstand voltage between wiring layers and improving the adhesion between the SOG film 8 and the upper wiring.

[0013]

In the above process, what is particularly important is the O ₃ -TEO shown in FIG.
The S / NSG film 3 is etched back. If the amount of the etch back is large, the upper end of the wiring 1 is exposed, and electric charges are stored inside the wiring 1. If this penetrates through the contact to the gate electrode of the transistor in the lower layer, the gate electrode has a fixed charge. Affects the value voltage. Therefore, the etch-back of the interlayer film is performed by the amount of the etch-back or the first plasma TEOS film 2 or the O ₃ -TEO so that the upper end of the lower wiring 1 is never exposed.
It must be adjusted so that the film thickness of the S / NSG film 3 becomes an optimum value.

However, in the process described above, the O ₃ -TEOS / NSG film 3 and the first plasma TE
The etch rate of the OS film 2 is almost the same, and the first plasma TEOS film 2 does not play a role of a stopper in the etch back. In order to use the underlying first plasma TEOS film 2 as a stopper, a sufficient film thickness is required in consideration of variations in RIE.

However, if these films are too thick, voids may be generated in the space between wirings, or O ₃ -T
There is a possibility that the EOS / NSG film 3 cannot fill the space between wirings. Further, the variation in the film thickness of the O ₃ -TEOS / NSG film 3 after the etch back is calculated in a form in which the variation in the CVD and the variation in the RIE of each film are accumulated, and is a considerably large value.

Specifically, the first plasma TEOS film 2 is 300 nm, and the O ₃ -TEOS / NSG film 3 is 500 nm.
When CVD is performed, a total of 800 nm SiO ₂ film is formed. When 650 nm is RIE equal to the wiring film thickness in the etch back of the O ₃ -TEOS / NSG film 3, the thickness of the remaining film simply becomes: 800-650 = 150
nm, and the variation of the remaining film thickness is ± 130 nm.
There is also a degree. Therefore, in this planarization process,
The problem remains that only a margin for the remaining 20 (150-130) nm can be secured.

The present invention has been made in view of such a situation, and enables the formation of a wiring layer having a fine pattern. In addition, the surface of the wiring layer is prevented from being exposed during the flattening process, and the flatness is reduced without voids. It is an object of the present invention to provide a method for manufacturing a semiconductor device having an excellent interlayer insulating film.

[0018]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming an antireflection film on a wiring layer; ,
A step of forming a resist film, a step of photolithographically processing the resist film into a predetermined pattern, a step of etching the wiring layer using a resist film photolithographically processed in the predetermined pattern as a mask, and Removing the film, forming an insulating film for planarization on the wiring layer while leaving the anti-reflection film, and performing a planarization process on the surface. the thickness and optical constant, the resist film of the photo setting lithography so as to suppress the standing wave effect at the time of processing and tear is, in the etching of the planarization process, before
The anti-reflection film functions as an etching stopper
You.

In the above, the flattening insulating film is
Wiring non-existing pattern portion at a predetermined interval or more in the wiring layer
Etch so that the insulating layer of the dummy pattern remains
Processed. Or, a predetermined interval or less in the wiring layer
Dummy pattern wiring on the wiring non-existing pattern part
Photolithography using the antireflection film so that a layer remains.
Ruffy processed.

The wiring layer is made of, for example, Al, Al-S
i, Al-Si-Cu, Al-Cu or the like.
The antireflection film, Si _x O _y N _z (since it contains hydrogen: also referred to as "Si _x O _y N _z H") or Si _x N _y
(Also called “Si _x N _y : H” because it contains hydrogen).

It is preferable that the wiring layer on which the antireflection film is formed be covered with the planarization insulating film via a buffer insulating film. The buffer film is composed of a silicon oxide film (plasma TEOS film) formed by a plasma enhanced chemical vapor deposition method using TEOS, and the planarization insulating film is formed by a normal pressure CVD method using ozone and TEOS. The formed silicon oxide film (O ₃ -TEOS / N
SG film), and the planarization insulating film is preferably planarized by etching.

[0022]

In the method of manufacturing a semiconductor device according to the present invention, for the fine processing of the lower layer wiring, the photoresist patterning, using an anti-reflection film, such as Si _X O _Y N _Z or Si _X N _Y film, the lower layer wiring After patterning is performed by RIE or the like, by leaving these antireflection films without removing them, they function as etching stoppers for a flattening process that is a later process.

In the present invention, since the lower wiring is subjected to photolithography processing using the antireflection film, the standing wave effect can be suppressed and the lower wiring can be finely patterned. Further, Si _X O _Y a N _Z or Si _X N _Y film antireflection film such as, by using as the O ₃ -TEOS / NSG is etched back at the stopper of the planarization insulating film, such as film, an insulating planarizing A sufficient margin at the time of etching back the film can be ensured. Si _X O _Y N _Z film or S
selectivity to i _X N _Y film of SiO ₂ are both, by adjusting the composition ratio, on the order of 20-50. That is, _x nm Si _x O _Y N as an anti-reflection film
_{When a Z} film or an _x nm Si _x N _y film is used, R
At the time of IE, the portion where the antireflection film is formed can be considered to be substantially the same as the case where the SiO ₂ film having a thickness of 20 × 50 nm is formed.

When applied to the previous example shown in FIGS.
The margin of the remaining film is (20 + 20 · x) to (20 + 50
X) increasing to nm. Therefore, the surface of the wiring layer is not exposed during the planarization process. In addition, since a sufficient margin can be secured with only the anti-reflection film alone, the thickness of the buffer layer such as the first plasma TEOS film or the flattening film such as the O ₃ -TEOS / NSG film formed beforehand can be reduced. Is also possible. Therefore, the film thickness can be set in consideration of the margin even for voids generated by increasing the thickness of these films.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the embodiments shown in the drawings. First Embodiment As shown in FIG. 1A, an antireflection film 20 and a resist film 22 are formed on a lower wiring layer 10. Lower wiring layer 1
0 denotes Al, Al-Si, Al-Si-
It is composed of Cu, Al-Cu or the like. Antireflection film is formed of, for example, a Si _X O _Y N _Z or Si _X N _Y, using _{SiH 4, N 2 O, N} 2, NH 3 or the like, for example, CVD or reactive sputtering, or, ECR
Plasma CVD or bias ECR plasma CVD
The film is formed by a plasma CVD method.

The Si _x O _y N _z, as shown in FIGS. 3 and 4, by changing the film formation conditions (in particular the flow rate ratio of SiH _4), n (refractive optical constants of the wavelength 248nm or other wavelength Real part of index), k (imaginary part of refractive index)
Can be greatly changed. Therefore, by changing the optical constant and the film thickness according to the type of the underlying film,
It can be preferably used as an optimal antireflection layer.
In FIG. 3, the horizontal axis is n and the vertical axis is k, and it has been confirmed that n and k change according to the film forming conditions (gas flow ratio Ratio, pressure Pressure, output Power). FIG.
The middle and horizontal axes represent the flow ratios of SiH ₄ and N ₂ O during film formation, and the vertical axes represent the values of n (○ in the figure) and k (● in the figure). However, in FIG. 4, the deposition time is 5 seconds, which is about 50 nm in terms of the film thickness (d). As described later, the film thickness of the optimum value of the antireflection film used in the embodiment is 23
Since the thickness is nm, 30 nm, or 25 nm, the values of n and k indicate smaller values than the graph shown in FIG. For example, when d = 23 nm, the deposition time corresponds to 2.65 seconds, which is smaller than the condition of 5 seconds shown in FIG. By changing the flow ratio between SiH ₄ and N ₂ O,
The composition of the resulting Si _x O _y N _z, varies as shown in FIG.

[0027] When used as Si _x O _y N _z film an antireflection film is as follows, the antireflection function is such that the maximum, to determine its thickness and optical constants. (1) A resist film 22 (for example, XP8843) is formed on the Al-Si wiring layer 10 without the antireflection film 20.
(Made by Shipley Microelectronics Co., Ltd.)), and a simulation result of the standing wave effect is shown in FIG. 6 on the assumption that exposure is performed by a KrF excimer laser having a wavelength of 248 nm. As shown in FIG. 6, the standing wave effect is about ± 2.
9.6%.

(2) In FIG. 6, the maximum value of the standing wave effect is when the resist film thickness is 982 nm. Focusing on the resist film thickness of 982 nm, and setting the film thickness of the antireflection layer to 30 n
FIG. 7 shows a simulation result of contour lines of the amount of light absorbed by the resist film with respect to changes in the optical constants n _arl and k _arl of the antireflection layer.

(3) Resist film thickness 1000 nm, 101
For each of 8 nm and 1035 nm, the above (2)
8, 9 and 10 show the results of the simulation of FIG. (4) As a result of _finding n _arl and k _arl of the common area where the amount of absorbed light shown in FIGS. 8 to 10 is minimized, n _arl = 4.8, k _arl = 0.45 (VALUE1) or n _arl = 2 .0, k _arl = 0.8 (VALUE2).

That is, when the thickness of the anti-reflection layer is 30 nm, the optimum optical constant of the anti-reflection layer is n _arl =
4.8, k _arl = 0.45 or n _arl = 2.0, k _arl = 0.8.

The antireflection film under such conditions is formed of Al-Si
When the standing wave effect when a film is formed on the film and a resist film is formed thereon is obtained, the results shown in FIGS. 11 and 12 are obtained. As shown in FIGS. 11 and 12, the standing wave effect is small, and in each case, it is about 1% or less. The standing wave effect can be suppressed to about 1/60 as compared with the case where there is no antireflection film.

(5) In the above procedures (2) to (4), the thickness of the antireflection layer is set to 30 nm, but the thickness of another different antireflection layer (also referred to as {ARL}) is changed. Again, by repeating the above (2) to (4), the optimum optical constant of the antireflection layer according to the thickness of the antireflection layer is determined. The obtained results are shown in FIGS. 13 (A) and (B).

[0033] (6) where whether the (5) in the film type which satisfies the conditions to be satisfied by the anti-reflection layer obtained is present, was investigated using a spectroscopic ellipsometer (SOPRA Co.), Si _x O _y n _z film, as shown in FIGS. 3 and 4, the optical constants (n, k) since the changes were found to be optimal depending on the deposition conditions. That, Si _x O _y N _z which is formed under the conditions shown in A of FIG. 3,
The conditions of FIGS. 13A and 13B are satisfied. Therefore,
A Si _x N _y film (Si = 2.08 and k = 0.85)
H ₄ / N ₂ O = 0.83) with a thickness of 25 nm
When a film is formed as an anti-reflection layer on the Si wiring layer, the standing wave effect can be suppressed to about ± 0.5% as shown by a curve A in FIG. The standing wave effect can be reduced to about 1/60 as compared with the standing wave effect without the antireflection film (curve B in FIG. 14).

Further, by a similar simulation, n
= 2.16 and _{k = 0.875 Si x O y N} z film of _{(SiH 4 / N 2 O =} 2.0) with a thickness of 23 nm, A
It has been found that an optimum anti-reflection effect can be obtained also when an anti-reflection film is formed on a wiring layer made of 1, Al-Si, Al-Si-Cu or Al-Cu.

The antireflection film 20 optimized as described above is formed on the underlying wiring layer 10 as shown in FIG. And a resist film 2 formed thereon.
By performing the photolithography process of No. 2, the fine pattern of the resist film 22 can be formed while suppressing the standing wave effect, and the line width variation is small. Therefore, if the underlying wiring layer 10 is etched by RIE or the like using the resist film 22, a fine wiring pattern 10a with a small line width variation can be obtained as shown in FIG.

Next, the buffer film 12 is formed on the wiring pattern 10a on which the anti-reflection film 20 is formed while the resist film 22 is removed and the anti-reflection film 20 is left.
The buffer layer 12 is composed of, for example, a silicon oxide film (plasma TEOS film) formed by a plasma enhanced chemical vapor deposition (CVD) method using TEOS.
It is several hundred nm, for example, about 300 nm. Buffer layer 1
Reference numeral 2 denotes a silicon oxide film of O ₃ -TEOS to be formed thereafter (hereinafter, also referred to as O ₃ -TEOS / NSG film)
And O ₃ -TEOS / NS having a high hygroscopic property to prevent the
This is to prevent the influence of the G film on the Al wiring (corrosion or the like) and to alleviate the underlayer dependence of the O ₃ -TEOS / NSG film formation.

Next, as shown in FIG. 1B, a first planarizing film 13 is formed on the buffer film 12. The first flattening film 13 is composed of, for example, an O ₃ -TEOS / NSG film. The thickness of the first flattening film 13 is several hundred nm, for example, about 500 nm. The O ₃ -TEOS / NSG film is a buffer film 1 having excellent step filling characteristics and unevenness.
2 can be formed with a constant film thickness. The first flattening film 13 is not particularly limited as long as it is a film which is excellent in step filling characteristics and can be formed with a constant film thickness. For example, a silicon oxide film obtained by a via sputtering method may be used. it can.

A first resist film is formed on the entire surface of the first flattening film 13, and the entire surface of the first resist film is etched back, so that the step formed on the surface of the first flattening film 13 is formed. The step filling resist pattern 14 is partially left in the portion. Next, a second resist film is further formed on the first flattening film 13 on which the step filling resist pattern 14 is formed, and the second resist film is subjected to photolithography processing using an inverted pattern of the wiring pattern 10a. . If the second resist film is photolithographically processed with an inverted pattern of the wiring pattern 10a, the wiring pattern 1
The resist pattern 15 remains in the wiring non-existing pattern portion at a predetermined interval or more in 0a, and the resist pattern disappears in the wiring non-existing pattern portion at a predetermined interval or less.

Next, as shown in FIG. 1C, anisotropic etching such as RIE is performed using the resist patterns 14 and 15 as a mask to process the first flattening film 13. By making the anisotropic etching amount approximately equal to the film thickness of the first planarizing film 13, the height of the insulating layer 16 of the dummy pattern formed by the resist pattern 15 can be reduced by the wiring 10a.
Of the buffer film 12 formed on the above pattern. Further, the first flattening film 13 is anisotropically etched so that
The buried portions 13a and 13b composed of the flattening film 13 are left.

In this embodiment, in this etching, the antireflection film 20 functions as an etching stopper,
A larger margin can be secured under the RIE condition in which the upper end of the lower wiring 10a is not exposed. Next, as shown in FIG. 1C, the plasma TEOS-CV
An intermediate flattening film 17 composed of a D film or the like is formed. The intermediate flattening film 17 is, for example, a silicon oxide film having a thickness of about several hundred nm. On this intermediate flattening film 17, a second flattening film 18 is formed. The second flattening film 18 is not particularly limited as long as it is a film having excellent local step filling characteristics.
Preferably, it is composed of an SOG film formed by the SOG method. The thickness of the second flattening film 18 is several hundred nm.

By forming the second flattening film 30, local steps due to the wiring 10a can be flattened. In addition, a relatively wide step due to the wiring 10a is eliminated by the insulating layer 16 of the dummy pattern formed of the first planarization film. In the present invention, the intermediate flattening film 17 is not necessarily required, but the first flattening film 13 is formed of O ₃ -T
When the second planarization film 18 is an EOS / NSG film and the second planarization film 18 is an SOG film, an intermediate planarization film 17 is preferably formed so as not to directly contact them.

Next, the entire surface of the second flattening film 18 is anisotropically etched to expose the surface of the intermediate flattening film 17, and the intermediate flattening film 17 is etched by a predetermined amount, whereby the surface of the second flattening film 17 is etched. Plan for flattening. Next, a film thickness adjusting film 19 is formed on the surface of the intermediate flattening film 17. The film thickness adjusting film 19
Flattened interlayer insulating film 3 laminated on wiring 10a
It is for adjusting the total film thickness of 0, and is made of, for example, a plasma TEOS film. The film thickness of the film thickness adjusting film 19 is several hundred nm.

According to the metal wiring patterning method and the method of flattening the interlayer insulating film between wiring layers according to the present embodiment, in order to enable fine processing of the metal wiring, Si _X O _Y N by CVD a _Z or Si _X N _Y film, in a photolithography process for patterning the wiring, by using as an antireflection film,
Enables high-precision patterning in the sub-half-micron region. Moreover, without removing the anti-reflection film used here,
By leaving it as it is, it can be used as a stopper at the time of etch-back in flattening between wiring layers, and a larger margin can be secured under the RIE condition in which the upper end of the lower wiring is not exposed.

Second Embodiment Next, another embodiment of the present invention will be described. In this embodiment, members common to those of the first embodiment are denoted by common reference numerals, and description thereof is omitted. In addition, the first
A description of a process and conditions common to the embodiment is omitted.

In this embodiment, as shown in FIG.
On the lower wiring layer 10, an optimized anti-reflection film 20 is formed in the same manner as in the first embodiment, and photolithography of the resist film is performed. At this time, unlike the first embodiment, a dummy resist is formed so that the wiring layer 10b of the dummy pattern remains in a portion of the wiring that does not originally become a wiring pattern and is a wiring non-existent pattern portion at a predetermined interval or more in the wiring. The pattern 22b is formed together with the wiring resist pattern 22a.

Thereafter, the wiring layer 10 is etched using the resist films of the patterns 22a and 22b as masks, and as shown in FIG. 2B, the wiring layer 10b of the dummy pattern is replaced with the original wiring layer pattern 10a. Form with. Similar to the dummy pattern insulating layer 16 shown in FIG. 1, the wiring layer 10b of the dummy pattern flattens a relatively wide step.

Thereafter, a flattening process is performed in the same manner as in the first embodiment except that the second resist film 15 shown in FIG. 1B is not used. The manufacturing method of this embodiment also has the same operation as that of the first embodiment. Note that the present invention is not limited to the above-described embodiments, and can be variously modified within the scope of the present invention.

[0048]

As described above, according to the present invention, it is possible to form a wiring layer having a fine pattern, and it is possible to effectively prevent the surface of the wiring layer from being exposed during the planarization process. In addition, it is not necessary to increase the thickness of the interlayer insulating film more than necessary, and it is possible to form an interlayer insulating film having excellent flatness without voids or the like. Therefore, the method of the present invention is particularly suitable for miniaturized multilayer wiring.

[Brief description of the drawings]

FIGS. 1A to 1C are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to one embodiment of the present invention.

FIGS. 2A to 2C are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 3 is a graph showing a relationship between manufacturing conditions of an antireflection film and optical constants.

FIG. 4 is a graph showing a relationship between manufacturing conditions of an antireflection film and optical constants.

FIG. 5 is a graph showing a relationship between a manufacturing condition and a composition of an antireflection film.

FIG. 6 is a graph showing a standing wave effect of a resist film on an Al—Si wiring in a case where an antireflection film is not provided.

FIG. 7 is a graph showing a locus of a change in the amount of light absorbed by the resist film when the optical constant of the antireflection film is changed at a resist film thickness of 982 nm.

FIG. 8 is a graph showing a locus of a change in the amount of light absorbed by the resist film when the optical constant of the antireflection film is changed at a resist film thickness of 1000 nm.

FIG. 9 is a graph showing a locus of a change in the amount of light absorbed by the resist film when the optical constant of the antireflection film is changed at a resist film thickness of 1018 nm.

FIG. 10 is a graph showing a locus of a change in the amount of light absorbed by the resist film when the optical constant of the antireflection film is changed at a resist film thickness of 1035 nm.

FIG. 11 is a graph showing the standing wave effect of the optimized antireflection film.

FIG. 12 is a graph showing a standing wave effect of an optimized anti-reflection film.

FIGS. 13A and 13B are graphs showing the relationship between the thickness of the antireflection film and k and n.

FIG. 14 is a view showing an example in which SiO _x N _y :
7 is a graph showing a difference between a standing wave effect in a case where an H film is formed and a case in which it is not.

FIGS. 15A and 15B are schematic cross-sectional views illustrating a planarization method according to a conventional example.

16 (C) to 16 (E) are schematic cross-sectional views showing a process subsequent to FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Wiring layer 10a ... Wiring pattern 10b ... Wiring layer of dummy pattern 12 ... Buffer film 13 ... First planarization film 16 ... Insulating layer of dummy pattern 14, 15 ... Resist pattern 17 ... Intermediate planarization film 18 ... Second flat Oxide film 19 ... film thickness adjusting film 20 ... anti-reflection film 30 ... interlayer insulating film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/3065 H01L 21/318 H01L 21/3205

Claims (6)

(57) [Claims] A step of forming an anti-reflection film on the wiring layer; a step of forming a resist film on the anti-reflection film; and a step of photolithography processing the resist film into a predetermined pattern. A step of etching the wiring layer using a resist film photolithographically processed in the predetermined pattern as a mask; removing the resist film and flattening the wiring layer while leaving the antireflection film. Forming a passivation insulating film and performing a surface flattening process, wherein the thickness and the optical constant of the antireflection film suppress a standing wave effect at the time of photolithography processing of the resist film. In the etching of the flattening process, the anti-reflection film functions as an etching stopper, and the flattening insulating film is formed at a position in the wiring layer. At regular intervals
Above the wiring non-existing pattern part,
A method of manufacturing a semiconductor device in which etching is performed so that an edge layer remains . 2. A process for forming an antireflection film on a wiring layer.
And extent, on the antireflection film, photolithography and the step of forming a resist film, the resist film in a predetermined pattern
Processing, and a photolithography processing of the predetermined pattern.
The wiring layer is etched using the dist film as a mask.
And removing the resist film, leaving the anti-reflection film
Then, an insulating film for planarization is formed on the wiring layer,
Performing a flattening process, wherein the film thickness and the optical constant of the antireflection film are
Suppresses standing wave effects during photolithographic processing of films
In the etching of the flattening process, the antireflection film
Function as an etching stopper, and a wiring non-existence pattern of a predetermined distance or more in the wiring layer.
So that the dummy pattern wiring layer remains in the
Photolithography using anti-reflective coating is performed
A method for manufacturing a semiconductor device. 3. The method according to claim 1, wherein the wiring layer is made of Al, Al—Si, Al
-Si-Cu, wherein is any one of Al-Cu
Item 3. The method for manufacturing a semiconductor device according to item 1 or 2 . Wherein said anti-reflection film, Si _x O _y N _z and Si _x N claims 1-3 Noi is one of a _y
A method for manufacturing a semiconductor device according to any one of the above. 5. The method of manufacturing a semiconductor device according to claim 1 , wherein the wiring layer on which the antireflection film is formed is covered with the planarization insulating film via a buffer insulating film. . 6. The buffer film is composed of a silicon oxide film formed by plasma enhanced chemical vapor deposition using TEOS, and the planarizing insulating film is formed of ozone and TE.
6. The method of manufacturing a semiconductor device according to claim 5 , wherein the planarization insulating film is formed by a silicon oxide film formed by a normal pressure CVD method using an OS, and the planarization insulating film is planarized by etching.