JPH1038812A - Mask defect detecting method - Google Patents
Mask defect detecting methodInfo
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- JPH1038812A JPH1038812A JP18898496A JP18898496A JPH1038812A JP H1038812 A JPH1038812 A JP H1038812A JP 18898496 A JP18898496 A JP 18898496A JP 18898496 A JP18898496 A JP 18898496A JP H1038812 A JPH1038812 A JP H1038812A
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- detection
- mask
- area
- detected
- defect
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置製造プ
ロセスのリソグラフィの露光工程に用いられるマスクの
欠陥を検出する方法に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a method for detecting a defect in a mask used in a lithography exposure step of a semiconductor device manufacturing process.
【０００２】[0002]
【従来の技術】半導体装置の製造分野では、半導体集積
回路の最小加工寸法が年々微細化されており、今や０．
２５μｍにまで達している。そして、このことに伴って
フォトリソグラフィ工程に用いるクロム（Ｃｒ）マスク
の欠陥（例えばＣｒの残りやＣｒの欠け）の最小許容寸
法も、年々微細化してきている。０．２５μｍの設計ル
ール半導体装置の場合には、１／５縮小投影露光を前提
にすると、マスクの欠陥の最小許容寸法が０．２μｍ
（ウエハ上で０．０４μｍ）であるとも言われている。
なお、縮小投影露光に用いるマスクは通常レチクルと呼
ばれるが、本明細書中ではこれもマスクと称することに
する。2. Description of the Related Art In the field of manufacturing semiconductor devices, the minimum processing size of a semiconductor integrated circuit has been reduced year by year.
It has reached 25 μm. Accordingly, the minimum allowable size of a defect (for example, residual Cr or chipped Cr) of a chromium (Cr) mask used in the photolithography process has been miniaturized year by year. In the case of a semiconductor device having a design rule of 0.25 μm, the minimum allowable size of a mask defect is 0.2 μm, assuming 1/5 reduction projection exposure.
(0.04 μm on the wafer).
The mask used for the reduced projection exposure is usually called a reticle, but in the present specification, this is also called a mask.
【０００３】ところで、従来より、マスクの微細欠陥の
検出には、欠陥検出装置が用いられる。通常、欠陥検出
装置は、ダイトゥダイ方式またはダイトゥデータベース
方式を採用しており、いずれの方式も２つのものを比較
して、一致するか否かで欠陥を検出している。例えばダ
イトゥダイ方式は、欠陥検出が行われるマスク（以下、
これを被検出マスクと記す）を用いて基板上に形成され
た複数のダイのパターン同士を形状比較して、欠陥を検
出する。またダイトゥデータベース方式は、被検出マス
クを用いて基板上に形成されたパターンとＣＡＤデータ
またはマスクパターン作成装置の入力データとを比較し
て、欠陥を検出する。また従来では、いずれの方式を用
いる場合にも、検出感度を一律にして欠陥検出を行って
いる。Conventionally, a defect detecting device has been used for detecting a fine defect of a mask. Usually, the defect detection apparatus employs a die-to-die method or a die-to-database method, and in each method, two methods are compared and a defect is detected based on whether they match. For example, in the die-to-die method, a mask (hereinafter, referred to as a defect detection) is used.
A defect is detected by comparing the shapes of a plurality of die patterns formed on a substrate with each other using a mask to be detected). In the die-to-database method, a defect is detected by comparing a pattern formed on a substrate using a mask to be detected with CAD data or input data of a mask pattern creating apparatus. Conventionally, in either case, the defect detection is performed with uniform detection sensitivity.
【０００４】[0004]
【発明が解決しようとする課題】従来のマスク欠陥の検
出方法では、被検出マスクのより微細な欠陥を検出する
には、検出に用いる欠陥検出装置の検出感度を上げなけ
ればならない。ところが、前述したように従来では、検
出感度を一律にして検出を行うため、検出感度を高くす
ると非常に多くの検出時間を要することになる。これを
回避する方法としては、欠陥検出装置を多数台用いるこ
とが考えられる。しかしながら、欠陥検出装置は非常に
高価であるため、欠陥検出装置を多数台用いるとマスク
コストの増大につながる。このことは、特に少量多品種
生産のロジック系の半導体集積回路を製造する場合に顕
著になるため、好ましくない。In the conventional method of detecting a mask defect, in order to detect a finer defect in a mask to be detected, the detection sensitivity of a defect detection apparatus used for the detection must be increased. However, as described above, in the related art, since detection is performed with uniform detection sensitivity, an extremely high detection sensitivity requires an extremely long detection time. As a method for avoiding this, it is conceivable to use a large number of defect detection devices. However, since the defect detection device is very expensive, using a large number of defect detection devices leads to an increase in mask cost. This is not preferable because it becomes remarkable especially when a logic-based semiconductor integrated circuit for small-quantity multi-product production is manufactured.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決するため
に本発明に係るマスク欠陥の検出方法は、欠陥の検出が
行われる被検出マスクに形成されたパターンを、第１検
出領域と第２検出領域とに分割し、分割された領域毎に
検出感度を変えて被検出マスクの欠陥の検出を行うこと
を特徴とする。According to the present invention, there is provided a method of detecting a mask defect, comprising the steps of: forming a pattern formed on a mask to be detected in which a defect is to be detected into a first detection area and a second detection area; The mask is divided into detection areas, and the detection sensitivity is changed for each of the divided areas to detect a defect of the mask to be detected.
【０００６】通常、リソグラフィの露光工程で用いるマ
スクに形成されたパターンには、同じ層のマスク（同一
レイヤ）内に、高い寸法精度で作成すべき領域と、それ
ほど寸法精度が要求されない、つまりラフでもよい領域
とが存在している。よって、被検出マスクに形成された
パターンにおける高い寸法精度で作成すべき領域、ラフ
でもよい領域をそれぞれ、第１領域、第２領域として分
割すれば、分割された領域毎に検出感度を変えて被検出
マスクの欠陥検出を行うので、高い寸法精度で作成すべ
き領域のみが高い感度で検出され、ラフでもよい領域が
それよりも低い感度で検出される。Normally, a pattern formed on a mask used in a lithography exposure step has a region to be formed with high dimensional accuracy and a mask that does not require much dimensional accuracy, ie, rough There are areas that can be used. Therefore, if the area to be created with high dimensional accuracy and the area that may be rough in the pattern formed on the detection target mask are divided into the first area and the second area, respectively, the detection sensitivity is changed for each of the divided areas. Since the defect of the mask to be detected is detected, only the region to be created with high dimensional accuracy is detected with high sensitivity, and the region that may be rough is detected with lower sensitivity.
【０００７】[0007]
【発明の実施の形態】以下、本発明に係るマスク欠陥の
検出方法の実施形態を図面に基づいて説明する。ここで
は、欠陥検出を行うマスク（以下、被検出マスクと記
す）を半導体装置のゲートパターン形成用のマスクにし
た場合について述べる。またダイトゥデータベース方式
の欠陥検出装置、すなわち被検出マスクを用いて基板上
に形成されたパターンを画像処理し、このデータと、被
検出マスクの設計データとを比較して欠陥検出を行う装
置を用いて欠陥検出を行う場合を例に取って述べる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for detecting a mask defect according to the present invention will be described below with reference to the drawings. Here, a case will be described in which a mask for performing defect detection (hereinafter, referred to as a detected mask) is a mask for forming a gate pattern of a semiconductor device. Also, a die-to-database type defect detection apparatus, that is, an apparatus that performs image processing on a pattern formed on a substrate using a detected mask and compares this data with design data of the detected mask to perform defect detection. A case where defect detection is performed by using the above will be described as an example.
【０００８】図１は実施形態に係るマスク欠陥の検出方
法を工程順に示すフローチャートであり、図２は被検出
マスクを用いて基板上に形成されたゲートパターン付近
の拡大平面図である。被検出マスクの欠陥を検出するに
あたっては、まず図１のステップ１（以下、ステップを
ＳＴと記す）に示すように、欠陥検出装置の検出感度を
設定する。この実施形態では、後述する第１検出領域を
検出するための検出感度と、第２検出領域を検出するた
めの検出感度との異なる２つの感度水準を設定する。例
えば第２検出領域を検出するための検出感度を、現在行
われている欠陥検出での通常の感度に設定し、第１検出
領域を検出するための検出感度を、通常の感度よりも高
い感度に設定する。FIG. 1 is a flowchart showing a method of detecting a mask defect according to the embodiment in the order of steps, and FIG. 2 is an enlarged plan view near a gate pattern formed on a substrate using a mask to be detected. In detecting a defect of the mask to be detected, first, as shown in Step 1 of FIG. 1 (hereinafter, the step is referred to as ST), the detection sensitivity of the defect detection device is set. In this embodiment, two different sensitivity levels are set, which are a detection sensitivity for detecting a first detection area described later and a detection sensitivity for detecting a second detection area. For example, the detection sensitivity for detecting the second detection area is set to the normal sensitivity for the currently performed defect detection, and the detection sensitivity for detecting the first detection area is set to a sensitivity higher than the normal sensitivity. Set to.
【０００９】なお、欠陥検出装置としては、高速で検出
感度を切り換えることができ、ゲートパターンが形成さ
れた基板を載置するステージを、感度切り替えに追随し
て移動させることができる装置を用いる。現在、レチク
ルのわくデータのような大まかに区切った領域毎に、検
出感度を設定変更できる装置がある。したがって、この
ような既存の装置のソフトウェアを変更することなどに
よって、上記した欠陥検出装置を実現することが可能で
ある。As the defect detection device, a device capable of switching the detection sensitivity at a high speed and moving a stage on which a substrate on which a gate pattern is formed is mounted following the sensitivity switching is used. At present, there is an apparatus that can change the setting of the detection sensitivity for each roughly divided area such as reticle frame data. Therefore, it is possible to realize the above-described defect detection device by changing the software of such an existing device.
【００１０】例えば欠陥検出装置が画像処理する際のピ
クセル（画素）の受光量と、被検出マスクの設計デー
タ、例えば電子ビーム（Electoron Beam) 描画装置の入
力データとを比較する際に、差のしきい値をソフト的に
変更することで、高速で検出感度を切り替える装置を得
ることが可能である。また、欠陥検出装置のレンズ倍率
を機械的に変更して行う（ピクセルサイズを変更する）
方法も考えられるが、レンズ倍率の変更に秒単位の時間
を要するので今のところ現実的でない。ただし、レンズ
倍率の変更を高速で行うことが可能になれば、このよう
な方法を採用することも可能である。For example, when comparing the amount of light received by a pixel at the time of image processing by the defect detection apparatus with the design data of the mask to be detected, for example, input data of an electron beam (Electoron Beam) drawing apparatus, the difference By changing the threshold value by software, it is possible to obtain a device that switches the detection sensitivity at high speed. Also, this is performed by mechanically changing the lens magnification of the defect detection device (changing the pixel size).
Although a method is conceivable, changing the lens magnification requires time in seconds, which is not practical at present. However, if it becomes possible to change the lens magnification at high speed, such a method can be adopted.
【００１１】欠陥検出装置の感度を設定した後は、次い
でＳＴ２〜ＳＴ４に示す工程を行って、被検出マスクに
形成されたゲートパターン（以下、被検出マスクのゲー
トパターンと記す）を、第１検出領域と第２検出領域と
に分割する。図２に示すように、被検出マスクを用いて
基板１０上に形成されたゲートパターン１３には、比較
的高い寸法精度が要求される領域（図中、ハッチングで
示す部分）１３ａと、それほど寸法精度が要求されない
ラフな領域１３ｂとが存在する。After setting the sensitivity of the defect detection apparatus, the steps shown in ST2 to ST4 are performed, and the gate pattern formed on the mask to be detected (hereinafter, referred to as the gate pattern of the mask to be detected) is converted into the first pattern. It is divided into a detection area and a second detection area. As shown in FIG. 2, the gate pattern 13 formed on the substrate 10 by using the detection target mask has a region (a portion indicated by hatching in the figure) 13a where relatively high dimensional accuracy is required, and There is a rough area 13b where accuracy is not required.
【００１２】すなわち、基板１０には、ＬＯＣＯＳ酸化
膜からなる素子分離領域１２で囲まれた位置に活性領域
１２が形成されており、この活性領域１２上に、２つの
直線状のゲートパターン１３が並んで設けられている。
また各ゲートパターン１３は、その両端が活性領域１２
からさらに素子分離領域１２上へと延びて形成されてい
る。活性領域１２は、欠陥が存在してほしくない領域で
あり、素子分離領域１２は小さな欠陥であれば少々存在
していてもよいラフな領域である。したがってゲートパ
ターン１３も、活性領域１２上に形成された領域が、高
い寸法精度が要求される領域１３ａになり、素子分離領
域１１上がラフな領域１３ｂになる。That is, an active region 12 is formed on the substrate 10 at a position surrounded by an element isolation region 12 made of a LOCOS oxide film, and two linear gate patterns 13 are formed on the active region 12. They are provided side by side.
Each gate pattern 13 has both ends of the active region 12.
And further extends over the element isolation region 12. The active region 12 is a region where a defect is not desired to exist, and the element isolation region 12 is a rough region where a small defect may be present. Therefore, also in the gate pattern 13, the region formed on the active region 12 becomes a region 13a where high dimensional accuracy is required, and the region above the element isolation region 11 becomes a rough region 13b.
【００１３】そこでこの実施形態では、被検出マスクの
ゲートパターンにおいて、高い寸法精度が要求される領
域１０ａに対応する領域を、高感度での検出が必要な第
１検出領域とし、ラフな領域１３ｂに対応する領域を、
通常の感度での検出でよい第２検出領域として、ゲート
パターンの分割を行う。ゲートパターンの分割は、欠陥
検出装置にて、被検出マスクのゲートパターンから第１
検出領域を抽出して設定し、抽出された以外の領域を第
２領域として設定することにより行う。第１検出領域の
抽出は、被検出マスクのデータと、その他の各層（レイ
ヤ）のマスク、特に製造プロセス上の被検出マスクの直
前、直後のマスクのデータとを用いた図形論理演算によ
って容易に行える。Therefore, in this embodiment, in the gate pattern of the mask to be detected, a region corresponding to the region 10a where high dimensional accuracy is required is set as a first detection region requiring high-sensitivity detection, and a rough region 13b is detected. The area corresponding to
The gate pattern is divided as a second detection area where detection with normal sensitivity is sufficient. The gate pattern is divided by the defect detection device from the gate pattern of the mask to be detected to the first.
This is performed by extracting and setting the detection area and setting an area other than the extracted area as the second area. The extraction of the first detection area is easily performed by a graphic logic operation using the data of the mask to be detected and the masks of the other layers (layers), particularly, the mask data immediately before and after the mask to be detected in the manufacturing process. I can do it.
【００１４】すなわち、まずＳＴ２に示すように、欠陥
検出装置に被検出マスクのゲートパターンのデータを入
力する。続いてＳＴ３に示すように、ゲートパターンの
周辺のパターン形成に用いるマスクに形成されるパター
ンのデータを、欠陥検出装置に入力する。ここでは、図
２に示した素子分離領域１１の形成に用いるマスクの素
子分離領域パターンのデータを入力する。これら欠陥検
出装置に入力するデータには、設計データ、例えばマス
クパターン形成用のＣＡＤ装置やマスクパターン作成装
置の入力データを用いる。That is, as shown in ST2, the data of the gate pattern of the mask to be detected is input to the defect detection device. Subsequently, as shown in ST3, data of a pattern formed on a mask used for forming a pattern around the gate pattern is input to the defect detection device. Here, data of an element isolation region pattern of a mask used to form the element isolation region 11 shown in FIG. 2 is input. As data to be input to these defect detection devices, design data, for example, input data of a CAD device for forming a mask pattern or a mask pattern creation device is used.
【００１５】そしてＳＴ４に示すように、図形論理演算
を行って、ゲートパターンのデータと素子分離領域パタ
ーンのデータとのアンドをとることにより、第１検出領
域を抽出し、設定する。また、これ以外の領域を第２検
出領域として設定する。次に、欠陥検出装置による被検
出マスクの欠陥検出を開始する。この際、欠陥検出装置
は、被検出マスクを用いて形成されたゲートパターン１
３において、現在の位置が、第１検出領域の位置にある
か否かを判断し（ＳＴ５）、第２検出領域でないと判断
すると、通常の検出感度で欠陥検出を行う（ＳＴ６）。
またＳＴ５にて現在検出を行っている位置が、第１検出
領域の位置であると判断すると、検出感度を高感度に切
り替えて欠陥検出を行う（ＳＴ７）。Then, as shown in ST4, the first detection area is extracted and set by performing AND operation on the data of the gate pattern and the data of the element isolation area pattern by performing a graphic logic operation. In addition, other areas are set as second detection areas. Next, detection of a defect of the detection target mask by the defect detection device is started. At this time, the defect detection device operates the gate pattern 1 formed using the detected mask.
In 3, it is determined whether or not the current position is in the position of the first detection area (ST5). If it is determined that the current position is not in the second detection area, defect detection is performed with normal detection sensitivity (ST6).
If it is determined in ST5 that the current detection position is the position of the first detection area, the detection sensitivity is switched to high sensitivity to perform defect detection (ST7).
【００１６】ＳＴ６またはＳＴ７にて欠陥検出を行った
後は、欠陥検出装置のステージを移動する（ＳＴ８）。
続いて、欠陥検出は終了か否かを判断する（ＳＴ９）。
欠陥検出は終了でないと判断された場合には、ＳＴ５に
戻って、現在の位置が、第１検出領域の位置にあるか否
かを判断し、欠陥検出を続ける。またＳＴ９にて、欠陥
検出は終了であると判断されると、一連の欠陥検出が終
了になる。After performing the defect detection in ST6 or ST7, the stage of the defect detection device is moved (ST8).
Subsequently, it is determined whether or not the defect detection is completed (ST9).
If it is determined that the defect detection has not been completed, the process returns to ST5 to determine whether or not the current position is at the position of the first detection area, and continues defect detection. When it is determined in ST9 that the defect detection has been completed, a series of defect detections is completed.
【００１７】このように、上記した欠陥検出方法では、
高い寸法精度が要求されるために微細な欠陥検出が必要
な第１検出領域のみを高感度で検出でき、それほど寸法
精度が要求されない第２検出領域を第１検出領域よりも
低い感度で検出できる。よって、微細な欠陥を検出しよ
うとすると、時間を要する高感度検出を一律に行わざる
を得なかった従来法に比較して、検出時間を短縮するこ
とができ、しかも必要な領域を高感度に欠陥検出するこ
とができる。したがって、この方法によればマスクコス
トを低減することができので、特に、少量多品種生産の
半導体集積回路を製造する場合に非常に有効な方法にな
る。As described above, in the above defect detection method,
Only the first detection area that requires fine defect detection because high dimensional accuracy is required can be detected with high sensitivity, and the second detection area that does not require much dimensional accuracy can be detected with lower sensitivity than the first detection area. . Therefore, when trying to detect minute defects, the detection time can be reduced compared to the conventional method, which requires time-consuming high-sensitivity detection, and the required area can be highly sensitive. Defects can be detected. Therefore, according to this method, the mask cost can be reduced, and this is a very effective method especially when a semiconductor integrated circuit manufactured in small quantities and in many kinds is manufactured.
【００１８】また上記した欠陥検出方法では、第１検出
領域を設定するための図形論理演算に、既に設計の段階
で存在している被検出マスクの設計データおよび素子分
離領域形成用のマスクの設計データを用いるので、新た
な作業を行うことなく容易にゲートパターンを第１検出
領域、第２検出領域に分割することができる。In the above-described defect detection method, the design data of the mask to be detected and the design of the mask for forming the element isolation region are already included in the graphic logical operation for setting the first detection region. Since the data is used, the gate pattern can be easily divided into the first detection area and the second detection area without performing a new operation.
【００１９】なお、上記実施形態では、ダイトゥデータ
ベース方式の欠陥検出装置を用いた欠陥検出方法につい
て述べたが、予め座標で指定された領域を区別して行う
ダイトゥダイ方式の欠陥検出装置を用いて欠陥検出を行
うこともできる。この場合には、欠陥検出装置のスキャ
ン方向で検出感度を切り替えるタイミングのデータを欠
陥検出装置に入力しておくことが必要になる。In the above embodiment, a defect detection method using a die-to-database type defect detection apparatus has been described. However, a defect detection method using a die-to-die type defect detection apparatus that distinguishes regions specified by coordinates in advance is used. Detection can also be performed. In this case, it is necessary to input data on the timing of switching the detection sensitivity in the scan direction of the defect detection device to the defect detection device.
【００２０】また上記実施形態では、検出感度の水準を
２つに設定した場合について述べたが、本発明はこの例
に限定されない。例えば第１検出領域を複数抽出し、第
１検出領域毎に検出感度が異なるように検出感度の水準
を設定することも可能である。この場合には、よりパタ
ーンの寸法精度の要求に即した欠陥検出を行えるととも
に、検出時間の短縮化を図ることができる。さらに上記
実施形態では、本発明をゲートパターン形成用のマスク
の欠陥検出に適用したが、本発明はリソグラフィ工程に
用いるいずれのマスクの欠陥検出に適用できるのはもち
ろんである。In the above embodiment, the case where the detection sensitivity levels are set to two has been described, but the present invention is not limited to this example. For example, it is possible to extract a plurality of first detection regions and set the level of the detection sensitivity so that the detection sensitivity differs for each first detection region. In this case, it is possible to perform defect detection more in line with the requirement of the pattern dimensional accuracy, and to shorten the detection time. Further, in the above embodiment, the present invention is applied to defect detection of a mask for forming a gate pattern. However, the present invention is of course applicable to defect detection of any mask used in a lithography process.
【００２１】[0021]
【発明の効果】以上説明したように本発明に係るマスク
欠陥の検出方法では、被検出マスクに形成されたパター
ンを分割した領域毎に、検出感度を変えて欠陥検出を行
うので、被検出マスクのパターンを高い寸法精度で作成
すべき領域とラフでもよい領域とに分割すれば、高い寸
法精度で作成すべき領域のみを高感度で検出し、ラフで
もよい領域を低い感度で検出するといった欠陥検出を行
うことができる。よって、必要な領域を高精度に欠陥検
出でき、しかも従来法に比較して検出時間を短縮できる
ので、コストを削減しつつ高精度のマスクを得ることが
できる。したがって、本発明は少量多品種生産の半導体
集積回路を製造する場合に非常に有効な方法になる。As described above, in the method of detecting a mask defect according to the present invention, the defect detection is performed by changing the detection sensitivity for each divided region of the pattern formed on the detected mask. If the pattern is divided into an area that should be created with high dimensional accuracy and an area that may be rough, defects such as detecting only the area that should be created with high dimensional accuracy with high sensitivity and detecting the area that may be rough with low sensitivity Detection can be performed. Therefore, a defect can be detected in a necessary area with high accuracy, and the detection time can be shortened as compared with the conventional method, so that a highly accurate mask can be obtained while reducing costs. Therefore, the present invention is a very effective method for manufacturing a small-quantity multi-product semiconductor integrated circuit.
【図１】本発明に係るマスク欠陥の検出方法の実施形態
を工程順に示すフローチャートである。FIG. 1 is a flowchart showing an embodiment of a mask defect detection method according to the present invention in the order of steps.
【図２】被検出マスクを用いて形成されたゲートパター
ン付近の平面図である。FIG. 2 is a plan view showing the vicinity of a gate pattern formed using a detection mask.
１３ ゲートパターン 13 Gate pattern
Claims (2)
スクの欠陥を検出する方法であって、 欠陥の検出が行われる被検出マスクに形成されたパター
ンを、第１検出領域と第２検出領域とに分割する第１工
程と、 前記分割された領域毎に検出感度を変えて被検出マスク
の欠陥の検出を行う第２工程とを有することを特徴とす
るマスク欠陥の検出方法。1. A method for detecting a defect of a mask used in an exposure step of lithography, wherein a pattern formed on a mask to be detected in which a defect is detected is divided into a first detection region and a second detection region. A method of detecting a mask defect, comprising: a first step of dividing; and a second step of detecting a defect of a mask to be detected by changing a detection sensitivity for each of the divided areas.
されたパターンのデータと、その他の層のマスクに形成
されたパターンのデータとを用いて論理演算を行うこと
によって、前記被検出マスクに形成されたパターンを第
１検出領域と第２検出領域とに分割することを特徴とす
る請求項１記載のマスク欠陥の検出方法。2. In the first step, a logical operation is performed using data of a pattern formed on a mask to be detected and data of a pattern formed on a mask of another layer, thereby obtaining the mask to be detected. 2. The method according to claim 1, wherein the pattern formed in the step (c) is divided into a first detection area and a second detection area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18898496A JP3646415B2 (en) | 1996-07-18 | 1996-07-18 | Mask defect detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18898496A JP3646415B2 (en) | 1996-07-18 | 1996-07-18 | Mask defect detection method |
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| Publication Number | Publication Date |
|---|---|
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| JP3646415B2 JP3646415B2 (en) | 2005-05-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18898496A Expired - Fee Related JP3646415B2 (en) | 1996-07-18 | 1996-07-18 | Mask defect detection method |
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