JP2008047598A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method that allows to efficiently detect defects, respectively having the same size and occurring at the same position in chip patterns caused by an exposure device. <P>SOLUTION: In an exposure step, three exposure devices are used for one substrate while respectively using each mask having the same pattern so as to execute exposure processing (S102a-c). In an inspection step (S106) after development, chip patterns a-c respectively exposed by different exposure devices are compared with each other so as to detect a non-aligned part between the chip patterns a, b and that between the chip patterns b, c respectively, and also, the respective non-aligned parts are compared with each other so as to determine in which pattern a-c defects occur. When the defects respectively having the same shape and occurring at the same position occur in a prescribed number of the chip patterns exposed by the same exposure device, the defects are determined as the defects caused by that exposure device so as to stop the use of that exposure device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which defects caused by an exposure apparatus used in an exposure process of the semiconductor device can be easily detected.

  In a semiconductor device such as a large scale integrated circuit (LSI), various fine structures are formed in a wiring layer formed on or inside a semiconductor substrate using a lithography technique. In lithography technology, light is transmitted through a mask or reticle on which a circuit pattern is formed, or exposure is performed by using a circuit pattern data to form a latent image (exposed portion) of a circuit pattern directly on a photosensitive resist film with an electron beam. A process, a developing process for removing exposed or non-exposed parts of the resist film with a developer, a processing process for performing etching or impurity implantation based on the pattern formed on the resist film by the developing process, and a resist film It consists of a removal step to remove. In the manufacturing process of the semiconductor device, these processes are repeated.

  In the exposure process, an exposure apparatus using an ultraviolet ray, laser beam, or electron beam as a light source is used. In the exposure process, in most cases, defects are randomly generated in the wafer or chip pattern.

  Also, if the exposure control system fails at a certain point and the desired precise operation cannot be performed, all the chips exposed by the exposure system have the same size and the same size defect. (A so-called pattern defect) may occur. In this case, an inspection method has been proposed in which image data between exposure apparatuses is compared by macro comparison inspection or appearance inspection between exposure apparatuses to detect abnormalities in the processing apparatus or processing unit (for example, Patent Documents 1 to 3). 3).

However, these inspection methods can deal only with macro defects in millimeters or more, such as uneven resist coating within the wafer surface. Further, wafers are required for the number of exposure apparatuses and the number of units, and further, an imaging process and a huge data storage system and data processing system are separately required.
JP 2004-140206 A JP 2000-207562 A JP 2001-194322 A

  By the way, in the defect inspection process after the exposure process, in order to detect a minute defect, the adjacent chip patterns in the wafer or areas where the same same fine pattern in the chip pattern exists are compared and different. A method of detecting a part as a defect is applied.

  A defect may occur in the same size and shape at the same place in the chip chip pattern over a large number of chip patterns. In this case, if the light source is a stepper or scanner that uses ultraviolet light or laser light, the reticle and mask are inspected for dirt, etc., but defects such as foreign matter and scratches attached to the reticle and mask after inspection Defects due to system failures are assumed. When the light source is an electron beam, it is assumed that a defect of the same position and the same size occurs in one dot or one shot, which is a unit for irradiating the electron beam, due to a malfunction of the system.

  FIG. 1 is a diagram for explaining a chip pattern formed on the surface of a substrate and problems of defect inspection. As shown in the upper diagram of FIG. 1, a large number of chip patterns are formed in a matrix on the surface of the semiconductor substrate. In the figure, one chip pattern is indicated by a solid rectangle. In the defect inspection, three adjacent chip patterns are enlarged and compared with a microscope.

  As indicated by TA1 in the lower diagram of FIG. 1, the defect inspection machine captures images of three chip patterns and compares the images. For example, first, the chip pattern A and the chip pattern B are compared, and the position and size of the non-matching portion of the image, that is, the defect 101 indicated by “●” is stored. Next, the chip pattern B and the chip pattern C are compared, and the coordinates and size of the inconsistent portion of the image are stored. In the case of chip pattern B and chip pattern C, the images all match. Then, it is determined by a majority decision that the minority chip pattern is defective. That is, between the chip patterns A to C, there is a non-matching part between the chip patterns A and B, and there is no non-matching part between the chip patterns B and C. A is a minority. Therefore, the chip pattern A has a defect in the mismatched portion.

  However, in the case of TA2 in the lower diagram of FIG. 1, when the defects 102 having the same position and size exist in the chip patterns A and B and there is no defect in the chip pattern C, the chip pattern C Since A and B match and the chip pattern C has a non-matching portion with respect to B, the chip patterns A and B are normal by the majority vote, and the chip pattern C has a defect. That is, there arises a problem that the inspection result does not accurately reflect the defect occurrence state of the chip pattern, and a problem that the defective chip pattern is normal and flows to a downstream process.

  Furthermore, in the case of TA3 in the lower diagram of FIG. 1, when there is a defect 103 having the same position and the same size in each of the chip patterns A to C, the chip patterns A to C are completely matched, so there is no defect. As a result, the above problem becomes more serious.

  As shown by TA3 in the lower figure of FIG. 1, when defects of the same size occur at the same position in all or most of the chip patterns due to a failure of the exposure apparatus itself, the difference cannot be determined depending on the chip pattern, so accurate defect inspection However, there is a problem that the detection rate becomes extremely low even if it cannot be detected.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor capable of efficiently detecting a defect having the same position and size in a chip pattern caused by an exposure apparatus. It is to provide a method for manufacturing a device.

  According to one aspect of the present invention, an exposure step of exposing a chip pattern to a resist film formed on a surface of a substrate using an exposure apparatus, and developing the exposed resist film to form a plurality of chip patterns as a resist film A semiconductor device manufacturing method comprising: a developing step for forming a plurality of chip patterns; and an inspection step for comparing the plurality of chip patterns with each other to determine a mismatched portion as a defect, wherein the exposure step is performed on a surface of a single substrate. The resist film formed on the substrate is exposed to the same chip pattern by each of a plurality of exposure apparatuses, and the inspection step compares the chip patterns exposed by different exposure apparatuses on the one substrate with each other to detect defects. A method for manufacturing a semiconductor device is provided.

  According to the present invention, chip patterns are formed on the surface of a single substrate by a plurality of exposure apparatuses, and these chip patterns are compared with each other to detect defects. It is possible to easily detect a defect that repeatedly occurs in the same shape at the same position. In the claims and specification of the present application, the chip pattern means a pattern that is exposed or drawn on the resist film in one exposure process, and a pattern that is formed on the resist film through the exposure process and the development process. To do.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the semiconductor device which can detect efficiently the defect of the position and magnitude | size in a chip pattern which generate | occur | produces resulting from an exposure apparatus can be provided efficiently.

  In the manufacturing process of a semiconductor device, a photosensitive resist film used as a mask for forming various structures on a semiconductor substrate, for example, a desired pattern such as a gate electrode, a wiring pattern, a vertical wiring portion such as a contact hole or a via, etc. And an exposure process for forming a latent image of a chip pattern on the resist film by the exposure process, selectively removing the resist film corresponding to the latent image, and forming a recess or an opening in the resist film And a processing step of performing an etching process or the like using the resist film as a mask is repeated. In the exposure process, a plurality of exposure apparatuses that form the same pattern are arranged in order to improve the processing capacity per time. In the present invention, when the same chip pattern is formed by a plurality of exposure apparatuses, when a defect having the same shape occurs over the plurality of chip patterns at the same position of the chip pattern due to a defect occurring in a specific exposure apparatus, The detection efficiency can be improved.

  The defects that can be detected in the method for manufacturing a semiconductor device according to the present invention are defects caused by the exposure apparatus. As a cause of such a defect, for example, when a mask or a reticle is used, there is a scratch on the mask or the reticle or an attached foreign substance. Masks and reticles are usually inspected by a dedicated defect inspection apparatus in advance, and only those determined as good as a result are used in the exposure apparatus. However, if scratches or foreign matter adhere after the inspection, especially if it is very small (for example, several microns or less, especially hundreds of nanometers to several tens of nanometers), it can be easily detected by the method of manufacturing a semiconductor device according to the present invention. is there.

  When the exposure apparatus is an electron beam drawing apparatus, the chip pattern calculates the size of the area exposed by one shot of the electron beam and the beam intensity based on the data, but an error occurs in the calculation process. In some cases, a chip pattern different from the desired chip pattern is formed. As a defect in this case, for example, the exposure areas exposed by one shot of the electron beam are usually formed in contact with each other, but the adjacent exposure areas are misaligned or unexposed portions are formed between the exposure areas. Is. These cases can also be easily detected by the semiconductor device manufacturing method according to the present invention.

  The exposure process, the development process, and the defect inspection process of the semiconductor device manufacturing method according to the present invention are performed as inspections. For example, it is performed daily or intermittently when the production line is in operation, or as an inspection immediately after maintenance of the production line or the exposure apparatus. As a result, the defect detection rate can be improved, the yield can be improved, and the handling of the substrate can be avoided. Furthermore, it is possible to avoid a decrease in yield due to a trouble that occurs immediately after maintenance. In addition, you may carry out in a normal manufacturing process. Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
The manufacturing method of the semiconductor device according to the first embodiment of the present invention is characterized by an exposure process, and further includes an inspection process for inspecting a defect of a pattern formed on the resist film after the development process. The inspection process is also unique.

  In the first embodiment, description will be made assuming that three exposure apparatuses A to C are used. The type of exposure apparatus targeted by the present invention is not particularly limited. For example, an electron beam exposure apparatus, an X-ray exposure apparatus, a deep ultraviolet (DUV) or ultrashort ultraviolet (EUV) laser such as KrF, ArF, or a fluorine dimer. Any of such light exposure apparatuses may be used. The types of the three exposure apparatuses are not limited as long as they use the same chip pattern mask or the same chip pattern data. The same type of exposure apparatus may be used, and at least one exposure apparatus may be combined with other exposure apparatuses. Different types of exposure apparatuses may be used. Different types of exposure apparatuses are apparatuses having different exposure light wavelengths or apparatuses having different drawing methods. By using different types of exposure apparatuses in this way, for example, the detection rate of defects derived from the wavelength of exposure light and the drawing method can be improved. The same applies to the second and third embodiments.

  In the first embodiment, a resist film forming process, an exposure process, a developing process, an inspection process, an etching process process, and a resist film removing process when forming an opening for forming a vertical wiring portion on a semiconductor substrate. A series of steps will be described as an example.

  2 and 3 are flowcharts of the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a manufacturing process diagram of the semiconductor device. FIG. 5 is an explanatory diagram of an exposure pattern according to the first embodiment. In FIG. 5, the vertical direction on the paper is the X direction and the horizontal direction on the paper is the Y direction.

  Referring to FIGS. 2 and 4A, a resist film is formed by applying a resist agent on the structure formed on the surface of the substrate 11 (S100). Here, on the substrate 11, a wiring layer 12, a cap layer 13, a first interlayer insulating film 14, a silicon oxide film 15, a second interlayer insulating film 16, a silicon oxide film 17, and an antireflection film 18 are sequentially stacked. The body is formed. The resist film 20 is made of, for example, a photosensitive resin that is sensitive to an electron beam, EUV having a wavelength of around 135 nm, DUV having wavelengths of 157 nm (fluorine dimer laser), 193 nm (ArF laser), and 248 nm (KrF laser).

  Next, in the exposure process, one substrate 11 is exposed using the same chip pattern mask using the three exposure apparatuses A to C (S102). In the exposure step, first, the substrate 11 on which the resist film 20 is formed is transported to the exposure apparatus A, and the chip pattern is exposed to the resist film 20 by the exposure apparatus A. As shown in FIG. Four chip patterns (chip pattern array a1) are formed in the direction (S102a). Thereby, as shown in FIG. 4A, a chip pattern latent image 20 a is formed on the resist film 20. Further, after that, a space for a pattern to be formed by the exposure apparatuses B and C is left, and another row (chip pattern row a2) is formed. Further, other one row or a plurality of rows (not shown) may be formed in the same manner.

  Next, the substrate 11 is transported to the exposure apparatus B and exposed by the exposure apparatus B using a mask having the same chip pattern as that of the exposure apparatus A. As shown in FIG. A chip pattern (chip pattern row b1) is formed (S102b). Here, the chip pattern row b1 is exposed to a region which is shifted in the Y direction with respect to the chip pattern row a1 and where no chip pattern is formed. At this time, it is preferable that the chip patterns of the chip pattern row c1 are formed so as to be aligned in the Y direction. Further, exposure is performed in the same manner as the chip pattern row b 1 by the exposure apparatus B, and the chip pattern row b 2 is formed on the resist film 20.

Next, the substrate 11 is transported to the exposure apparatus C, and exposed by the exposure apparatus C using a mask having the same chip pattern as that of the exposure apparatus A. As shown in FIG. A chip pattern (chip pattern row c1) is formed (S102c). Here, the chip pattern row c1 is exposed to a region which is shifted in the Y direction with respect to the chip pattern row b1 and where no chip pattern is formed. At this time, it is preferable that each chip pattern of the chip pattern row c1 is formed so as to be aligned in the Y direction with respect to each chip pattern of the chip pattern row b1. Further, exposure is performed in the same manner as the chip pattern row c 1 by the exposure apparatus C, and the chip pattern row c 2 is formed on the resist film 20.
As described above, a latent image of the chip pattern exposed by the exposure apparatuses A to C is formed on the resist film 20.

  Next, the resist film 20 on which the latent images of the chip pattern rows a1 to c2 are formed is developed (S104). Specifically, when the resist film 20 is a positive type using a developing solution, the latent image portion is dissolved to form the opening 20b. As a result, an opening 20b is formed in the resist film 20 as shown in FIG.

  Next, a defect inspection of the pattern formed on the resist film 20 is performed (S106). The pattern defect inspection will be described in detail later, but is performed according to the flowchart shown in FIG.

  Next, dry etching is performed using the resist film 20 as a mask (S108). Specifically, using the resist film 20 as a mask, the antireflection film 18, the silicon oxide film 17, the second interlayer insulating film 16, the silicon oxide film 15, the antireflection film 14, and the cap layer 13 in the opening 20b are respectively formed. A process gas is selected according to the layer material and removed by a reactive ion etching (RIE) method to expose the surface of the wiring layer 12.

  Next, the resist film 20 that has become unnecessary is removed (S110). Thus, the opening 21 for forming the vertical wiring portion is formed.

  Next, the defect inspection process will be described in detail. First, the defect inspection machine will be described.

  FIG. 6 is a configuration diagram of an example of a defect inspection machine used in the manufacturing method according to the present invention. Referring to FIG. 6, the defect inspection machine 60 is provided with a mounting table 61 for fixing the substrate 11 by suction or the like. The mounting table 61 is provided on the XY stage 62 and the Z-θ stage 63, and the substrate 11 can be positioned in the X axis, Y axis, and Z axis directions orthogonal to each other and the rotation direction of the substrate 11. Yes. The defect inspection machine 60 is a so-called bright field type or dark field type optical defect inspection machine. The defect inspection machine 60 includes a light source 64 that emits white light, UV light, laser light, or the like, a half mirror 65 that passes the irradiation beam from the light source 64 and changes the optical path of the reflected beam from the substrate 11, and the irradiation beam. A lens 66 that condenses light on the surface of the substrate 11 and converts the reflected beam from the substrate 11 into parallel light, a lens 68 that condenses the reflected beam on the CCD sensor 69, and a CCD sensor 69 that detects an image by the reflected beam. Have. Further, the defect inspection machine 60 processes the image from the CCD sensor 69 and detects the defect and controls the entire apparatus such as the XY stage 62 and the Z-θ stage 63, an image display unit 81, An input unit 82, a recording device 83, and the like are included. The control calculation unit 70 includes an image processing unit 71, an optical system / stage control unit 72, an image comparison unit 73, a mismatched portion storage unit 74, and a defect determination unit 75. Note that. The image comparison unit 73, the mismatched part storage unit 74, and the defect determination unit 75 are functional blocks that function by the CPU and the memory and the program stored in the memory.

  The defect inspecting machine 60 divides two chip patterns, for example, the regions of the chip pattern a in the chip pattern row a1 and the chip b in the chip pattern row b1 shown in FIG. Position control is performed by the θ stage 63, and images of the areas are magnified by the lenses 66 and 68 and detected by the CCD sensor 69. After image processing by the image processing unit 71, two images are compared by the image comparison unit 73. The contrasts of the chip patterns a and b are compared to detect a mismatched portion, and the position and shape are stored in the mismatched portion storage unit. On the other hand, for the chip pattern b and the chip c in the chip pattern row c 1, the contrast mismatch portion between the two chip patterns b and c is detected and the position and shape are stored in the mismatch portion storage unit 74. Then, the defect determination unit 75 compares the inconsistent portions and determines whether or not the defect is present. A specific defect determination method will be described with reference to FIG.

  With reference to FIG. 3 together with FIG. 5C, the defect inspection process of the chip patterns a to c formed on the resist film will be described. In the defect inspection, the chip pattern a of the chip pattern array a1, the chip pattern b of the chip pattern array b1, and the chip pattern c of the chip pattern array c1 are inspected as one comparison target group TG. These chip pattern a, chip pattern b, and chip pattern c are chip patterns adjacent in the Y direction. In this way, by selecting a chip pattern in which one comparison target chip pattern as an inspection unit is close to each other, the movement time of the XY stage and the movement time of the Z-θ stage for focusing can be shortened. This is preferable in terms of improving the throughput.

  First, images of chip pattern a and chip pattern b are compared by a defect inspection machine (S120). The comparison of the images is performed for each region where the positions in the chip pattern correspond to each other. For example, the images of the chip pattern a and the chip pattern b are compared for each rectangular region having a side of 5 μm. As a result of the comparison (comparison result 1), if there is a mismatched portion at a position corresponding to each other between the chip pattern a and the chip pattern b, the position and size of the mismatched portion are stored.

  Next, the images of the chip pattern b and the chip pattern c are compared in the same manner as in S120 (S122). If there is a mismatched result (comparison result 2), the position and size of the mismatched part are recorded.

  Next, the comparison results 1 and 2 are compared for each region in the chip pattern (S124). As a result, when there is a non-matching part only between the chip pattern a and the chip pattern b in a certain area in the chip pattern, that is, there is a non-matching part between the chip pattern a and the chip pattern b. If there is no inconsistent portion with the chip pattern a, the chip pattern b and the chip pattern c are not defective, and the chip pattern a is defective (S126).

  On the other hand, when there is a non-matching part only between the chip pattern b and the chip pattern c, that is, there is a non-matching part between the chip pattern b and the chip pattern c. If there is no mismatch, the chip pattern c is defective (S128).

  On the other hand, if there is a mismatch between the chip pattern a and the chip pattern b and between the chip pattern b and the chip pattern c, the chip patterns a and c are free from defects and the chip pattern There is a defect in b (S130).

  Next, when there are other uninspected chip patterns a to c (groups to be compared with uninspected chip patterns) (“YES” in S132), S120 to S132 are performed for the chip patterns a to c.

  When image comparison is performed for all the chip patterns a to c (“No” in S132), it is determined whether or not the defect position and the shape are the same for each exposure apparatus that has formed the latent image of the chip pattern row (S134). ). That is, for example, in the chip pattern rows a1 and a2, it is determined whether or not a predetermined number or more of chip patterns have defects having the same defect position and shape. If there are defects in the predetermined number or more of chip patterns, use of the exposure apparatus that has exposed the chip patterns, for example, the exposure apparatus A is stopped (S138). Here, the predetermined number is not particularly limited as long as it is 2 or more, and can be set as appropriate.

  On the other hand, when there are defects having the same defect position and shape in less than a predetermined number of chip patterns, normal defect processing, for example, processing such as finally rejecting a defective chip pattern is performed ( S136). Thus, the defect inspection process is completed.

  According to the first embodiment, chip patterns a to c are formed on the resist film 20 on one substrate 11 by three exposure apparatuses A to C, and these chip patterns a to c are mutually connected. Since the defect is detected by comparison, it is possible to easily detect a defect that repeatedly occurs in the same shape at the same position in the chip pattern due to the exposure apparatus. Therefore, since it is possible to detect defects immediately after occurrence without waiting for quality inspection of the final product, for example, it is possible to dispose of a substrate having a defect number exceeding a predetermined number without performing a downstream manufacturing process. is there. As a result, the manufacturing apparatus can be occupied for processing a substrate with good quality, so that the production efficiency can be improved and the production yield can be further improved.

  Further, since the chip patterns a to c are formed on the single substrate 11 by the three exposure apparatuses A to C, it is sufficient to store only the non-matching portion as a comparison result as data, so that the data amount is small. As a result, the data transfer time can be shortened, so that the defect inspection time can be shortened and the amount of memory can be reduced compared to a defect device that stores an image of a chip pattern for one substrate and compares it with the chip pattern of another substrate. Can be reduced.

  It should be noted that whether or not the predetermined number or more of chip patterns in S134 have defects having the same defect position and shape does not require inspection of the total number of chip turns on the substrate, from the beginning of one substrate S120. To S132, the exposure apparatus may be stopped at S138 when the count reaches a predetermined number. In this case, the counting may be started from the middle of the substrate inspection.

  Moreover, although the example which performs the exposure process, the image development process, and the defect inspection process which concerns on 1st Embodiment in the normal manufacturing process was given above, an effect improves further by performing as an inspection. For example, it is performed daily or intermittently when the production line is in operation, or as an inspection immediately after maintenance of the production line or the exposure apparatus. As a result, the defect detection rate can be improved, the yield can be improved, and the handling of the substrate can be avoided. Furthermore, it is possible to avoid a decrease in yield due to a trouble that occurs immediately after maintenance. Further, the substrate used in the manufacturing method according to the present embodiment may be a substrate on which a semiconductor circuit is finally formed. However, as a substrate for checking an exposure process, a silicon substrate such as a bare silicon wafer or an oxide film on the surface It is preferable to use a silicon substrate on which is formed, or a silicon substrate having a silicon oxide film deposited on the surface thereof for about 100 nanometers. As a result, the contrast of the image is improved, and finer defects can be detected more accurately.

  In the above description, an example using three exposure apparatuses is shown. However, the same applies to the case where the exposure apparatus is provided as one column of a multi-chamber type or cluster type semiconductor manufacturing apparatus. Further, the same applies to the multi-column method and the multi-beam method in which a single apparatus exposes and draws a plurality of chip patterns simultaneously on a single wafer. In this case, the above chip pattern may be exposed on one substrate by three columns. In the multi-column method and the multi-beam method, the case of three or a plurality of columns is executed at the same time. The same applies to the second and third embodiments described below.

(Second Embodiment)
The method for manufacturing a semiconductor device according to the second embodiment of the present invention is a modification of the method for manufacturing a semiconductor device according to the first embodiment. Since the manufacturing method according to the second embodiment is the same except that the exposure process and the defect inspection process for exposure using the two exposure apparatuses A and B are different, the description of the same parts is omitted.

  FIG. 7 is an explanatory diagram of an exposure pattern according to the second embodiment of the present invention.

  Referring to FIG. 7, in the exposure process, chip patterns a1, b1, a2, a3, b2, and a4 are separated from each other in the X direction and in the Y direction by exposure apparatuses A and B, respectively. Form. Here, the chip pattern arrays a1 to a4 are formed by the exposure apparatus A, and the chip pattern arrays b1 and b2 are formed by the exposure apparatus B. The method for forming the chip pattern row is the same as in the first embodiment.

  Then, in the defect inspection process of the second embodiment, as shown in FIG. 7B, the chip pattern a-1 of the chip pattern array a1, the chip pattern b-1 of the chip pattern array, and the chips of the chip pattern array Defect inspection is performed using the pattern a-2 as one comparison target group TG. The flowchart of the defect inspection process is substantially the same as that of FIG. 3, and in the second embodiment, the chip pattern a shown in FIG. 3 is a-1, the chip pattern b is b-1, and the chip pattern c is a. -2, respectively. That is, in S120 of FIG. 3, the chip pattern a-1 and the chip pattern b-1 are compared, and in S122, the chip pattern b-1 and the chip pattern a-2 are compared. By doing in this way, the defect resulting from the exposure apparatus A or B can be detected.

  As described above, according to the second embodiment, even when there are two exposure apparatuses, the same effect as that of the first embodiment is obtained, that is, the chip pattern is caused by the exposure apparatus. It is possible to find defects that occur repeatedly at the same position and in the same shape.

(Third embodiment)
The method for manufacturing a semiconductor device according to the third embodiment of the present invention is a modification of the method for manufacturing a semiconductor device according to the first embodiment. Since the manufacturing method according to the third embodiment is the same except that the exposure process and the defect inspection process for exposure using four or more, for example, six exposure apparatuses A to F, are different, the same parts are described. Description is omitted.

  FIG. 8 is an explanatory diagram of an exposure pattern according to the third embodiment of the present invention.

  Referring to FIG. 8, in the exposure process, chip pattern rows a to f are formed along the X direction and separated from each other in the Y direction by exposure apparatuses A to F, respectively. Here, the chip pattern arrays a1 to a4 are formed by the exposure apparatus A, and the chip pattern arrays b1 and b2 are formed by the exposure apparatus B. The method for forming the chip pattern row is the same as in the first embodiment.

  In the defect inspection process of the third embodiment, the chip pattern of the chip pattern columns a to c is defined as one comparison target group TG1, and the chip pattern of the chip pattern sequence df is defined as one comparison target group TG2. Perform an inspection. The flowchart of the defect inspection process is substantially the same as FIG.

  In the third embodiment, even when there are four or more exposure apparatuses, the same effect as in the first embodiment is obtained, that is, the same position at the same position of the chip pattern due to the exposure apparatus. You can find defects that occur repeatedly in shape.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the present invention described in the claims. It can be changed.

  In the above embodiment, each exposure apparatus forms a chip pattern along the X direction. However, as long as it has information on the relationship between the exposure apparatus and the chip pattern, a chip pattern formed by one exposure apparatus. May be formed at an arbitrary position. However, even in that case, it is preferable that adjacent chip patterns are formed by different exposure apparatuses.

  Further, when the number of exposure apparatuses to be detected for defects is not a multiple of 3, the exposure pattern of the first embodiment and the exposure pattern of the second embodiment may be appropriately combined. Further, the number of chip patterns in one comparison target group in S120 and S122 in FIG. 3 may be more than three, but three is preferable in terms of more efficient.

In addition, the following additional notes are disclosed regarding the above description.
(Appendix 1)
An exposure step of exposing the chip pattern to a resist film formed on the surface of the substrate using an exposure apparatus;
A developing step of developing the exposed resist film to form a plurality of chip patterns on the resist film;
An inspection step of comparing the plurality of chip patterns with each other and determining an inconsistent portion as a defect, comprising:
In the exposure step, a resist film formed on the surface of a single substrate is exposed to the same chip pattern by each of a plurality of exposure apparatuses,
The method for manufacturing a semiconductor device, wherein the inspection step detects defects by comparing chip patterns exposed by different exposure apparatuses on the one substrate with each other.
(Appendix 2)
In the exposure step, the resist film formed on the surface of one substrate is exposed using at least two exposure apparatuses,
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the inspection step, defects are detected by comparing three chip patterns formed on the resist film by at least two exposure apparatuses.
(Appendix 3)
The exposure step exposes the chip patterns so as to be adjacent to each other using three exposure apparatuses,
3. The method of manufacturing a semiconductor device according to claim 2, wherein in the inspection step, defects are detected by comparing chip patterns respectively formed by the three different exposure apparatuses.
(Appendix 4)
The exposure step is characterized in that the respective exposure apparatuses expose the chip pattern along the first direction and adjacent to the second direction orthogonal to the first direction. Or 3. A method of manufacturing a semiconductor device according to 3.
(Appendix 5)
The exposure step uses two exposure apparatuses to expose so that two chip patterns formed by one exposure apparatus sandwich one chip pattern formed by the other exposure apparatus,
3. The method of manufacturing a semiconductor device according to claim 2, wherein in the inspection step, each of the two chip patterns and the one chip pattern are compared with each other to detect a defect.
(Appendix 6)
6. The method of manufacturing a semiconductor device according to any one of appendices 1 to 5, wherein at least one of the plurality of exposure apparatuses uses exposure light having a wavelength different from that of other exposure apparatuses or a drawing method.
(Appendix 7)
7. The method of manufacturing a semiconductor device according to claim 1, wherein a semiconductor circuit is finally formed on the substrate.
(Appendix 8)
7. The method of manufacturing a semiconductor device according to any one of appendices 1 to 6, wherein the substrate is a silicon substrate having an oxide film formed on a surface thereof or a silicon substrate having a silicon oxide film deposited thereon.
(Appendix 9)
9. The method of manufacturing a semiconductor device according to any one of appendices 1 to 8, wherein the chip pattern and an exposure apparatus that exposes a latent image of the chip pattern are compatible.
(Appendix 10)
The inspection step detects the shape and occurrence position of the defect, and when a predetermined number of defects having the same shape and the same occurrence position are detected among a plurality of chip patterns exposed by the same exposure apparatus, 10. The method of manufacturing a semiconductor device according to any one of appendices 1 to 9, wherein the use of the exposure apparatus is stopped as an abnormality of the apparatus.
(Appendix 11)
Of the additional notes 1 to 10, wherein the exposure process, the development process, and the inspection process are performed to detect abnormalities in devices and manufacturing processes that are performed on a daily, intermittent, or timely basis as needed. A manufacturing method of a semiconductor device given in any 1 paragraph.

It is a figure for demonstrating the problem of the chip | tip formed in the surface of a board | substrate, and a defect inspection. 5 is a flowchart (No. 1) of the method for manufacturing the semiconductor device according to the first embodiment of the invention. 6 is a flowchart (part 2) of the method for manufacturing the semiconductor device according to the first embodiment; It is a manufacturing process figure of a semiconductor device. It is explanatory drawing of the exposure pattern of 1st Embodiment. It is a block diagram of an example of the defect inspection machine used for the manufacturing method which concerns on this invention. It is explanatory drawing of the exposure pattern of the 2nd Embodiment of this invention. It is explanatory drawing of the exposure pattern of the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Board | substrate 12 Wiring layer 13 Cap layer 14 1st interlayer insulation film 15, 17 Silicon oxide film 16 2nd interlayer insulation film 18 Antireflection film 20 Resist film 60 Defect inspection machine 61 Mounting stand 62 XY stage 63 Z-theta stage 63 Reference Signs List 64 Light source 65 Half mirror 66, 68 Lens 69 CCD sensor 70 Control operation unit 71 Image processing unit 72 Optical system / stage control unit 73 Image comparison unit 74 Unmatched part storage unit 75 Defect determination unit 81 Image display unit 82 Input unit 83 Recording device a1, a2, b1, b2, c1, c2, a to f Chip pattern row TG Comparison target group

Claims (5)

An exposure step of exposing the chip pattern to a resist film formed on the surface of the substrate using an exposure apparatus;
A developing step of developing the exposed resist film to form a plurality of chip patterns on the resist film;
An inspection step of comparing the plurality of chip patterns with each other and determining an inconsistent portion as a defect, comprising:
In the exposure step, a resist film formed on the surface of a single substrate is exposed to the same chip pattern by each of a plurality of exposure apparatuses,
The method for manufacturing a semiconductor device, wherein the inspection step detects defects by comparing chip patterns exposed by different exposure apparatuses on the one substrate with each other. In the exposure step, the resist film formed on the surface of one substrate is exposed using at least two exposure apparatuses,
2. The method of manufacturing a semiconductor device according to claim 1, wherein the inspection step detects defects by comparing three chip patterns formed on the resist film by at least two exposure apparatuses.   3. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of the plurality of exposure apparatuses uses exposure light having a wavelength different from that of other exposure apparatuses or a drawing method.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is a silicon substrate having an oxide film formed on a surface thereof or a silicon substrate having a silicon oxide film deposited thereon. .   The inspection step detects the shape and occurrence position of the defect, and when a predetermined number of defects having the same shape and the same occurrence position are detected among a plurality of chip patterns exposed by the same exposure apparatus, 5. The method of manufacturing a semiconductor device according to claim 1, wherein use of the exposure apparatus is stopped.

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