JPH10341008A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device and its manufacturing method, wherein the patterns of its gate electrodes can be formed accurately, responding to their design specifications and which have high-performance MOSFETs. SOLUTION: The manufacturing method of a semiconductor integrated circuit device has a step for forming a gate insulation film 4, a conductive layer which are to become gate electrodes 5, etc., an insulating film 6 on a semiconductor substrate 1, a step for forming the patterns for the gate electrodes 5 in a photoresist film 7 by a photolithographic technique after forming the photoresist film 7 on the semiconductor substrate 1 and for forming the patterns for dummy gate electrodes 5a adjacent to the patterns for the specific gate electrodes 5, and a step for forming the gate electrodes 5 and the dummy gate electrodes 5a by patterning the conductive layer through selectively etching it, using the photoresist film 7 with the patterns for the gate and dummy gate electrodes 5, 5a as an etching mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device having a high-performance MOSFET capable of forming a gate electrode pattern in accordance with design specifications with high precision. And a method of manufacturing the same.

[0002]

2. Description of the Related Art The present inventor has proposed a DRAM (Dynamic Random Access Memory).
A method of manufacturing a semiconductor integrated circuit device having an access memory was studied. The following is a technique studied by the present inventors, and the outline is as follows.

That is, in a method of manufacturing a semiconductor integrated circuit device having a DRAM, an M
After forming an OSFET and a MOSFET constituting a peripheral circuit thereof on a semiconductor substrate using the same manufacturing process, a multilayer wiring layer is formed on the semiconductor substrate.

As a document describing a method of manufacturing a semiconductor integrated circuit device having a DRAM, there is a document described in, for example, Japanese Patent Application Laid-Open No. 3-214669.

[0005]

However, the aforementioned D
In a semiconductor integrated circuit device having a RAM, a separation distance between gate electrodes of a plurality of MOSFETs forming a memory array and adjacent peripheral circuits (word driver, sense amplifier, Y-direction decoder, etc.) adjacent thereto ( Although the separation distance between adjacent gate electrodes is small (dense), the separation distance between the gate electrodes of a plurality of MOSFETs constituting an indirect peripheral circuit (such as a logic circuit) as its peripheral circuit is large (coarse). ), The threshold voltage (V
th) and there is a problem that a timing mismatch occurs.

Also, indirect peripheral circuits (logic circuits, etc.)
Since the separation distance between the gate electrodes of the plurality of MOSFETs constituting the gate electrode is large (coarse), when the gate electrode pattern is formed by using the photolithography technique and the selective etching technique, the gate of the design specification is required. Since a pattern having a width larger than the width of the electrode is formed in the photoresist film, the width of the gate electrode becomes larger than the pattern of the design specification, and the MOSFET has a threshold voltage different from the threshold voltage of the design specification. Is formed, which causes a problem that the MOSFET has a threshold voltage different from the threshold voltage of the design specification.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-performance MOS transistor capable of forming a gate electrode pattern in accordance with design specifications with high accuracy.
An object of the present invention is to provide a semiconductor integrated circuit device having an FET and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device of the present invention, a dummy gate electrode of the same layer as the gate electrode is arranged adjacent to a specific gate electrode.

Further, according to a method of manufacturing a semiconductor integrated circuit device of the present invention, a step of forming a field insulating film in a selective region on a surface of a semiconductor substrate, a step of forming a gate insulating film on the semiconductor substrate, Next, after forming a conductive layer to be a gate electrode on the gate insulating film, forming an insulating film on the conductive layer, and forming a photoresist film on the semiconductor substrate, using photolithography technology Forming a gate electrode pattern on the photoresist film and forming a dummy gate electrode pattern adjacent to the specific gate electrode pattern; and a photoresist having the gate electrode pattern and the dummy gate electrode pattern. By using the film as an etching mask and patterning the conductive layer using selective etching technology, the gate electrode and dummy And a step of forming a over gate electrode.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

FIGS. 1 to 8 are sectional views showing the steps of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

The semiconductor integrated circuit device according to the present embodiment has a DRAM having a capacitor in a memory cell. In FIGS. 1 to 8, a cross-sectional view shown on the left side shows a region of a memory array. It is a sectional view showing a part,
The cross-sectional view shown on the right side is a cross-sectional view showing a part of a region of an indirect peripheral circuit such as a logic circuit arranged around the region of the memory array.

In the semiconductor integrated circuit device having the DRAM of the present embodiment, a plurality of memory arrays and a plurality of adjacent peripheral circuits (word drivers, sense amplifiers, Y-direction decoders, etc.) adjacent thereto are formed. M
The separation distance between the gate electrodes of the OSFETs (the separation distance between adjacent gate electrodes) is small (dense), but the gates of a plurality of MOSFETs that constitute an indirect peripheral circuit (such as a logic circuit) that is a peripheral circuit thereof The separation between the electrodes is large (coarse).

A semiconductor integrated circuit device having a DRAM according to the present embodiment and a method for manufacturing the same will be described.

First, as shown in FIG. 1, a p-type well 2 and an n-type well (not shown) are formed on a p-type semiconductor substrate 1 made of, for example, single crystal silicon, and then a groove is formed in an element isolation region. Is formed, an insulating film made of, for example, a silicon oxide film is buried in the premise to form the element isolation portion 3. In this case, in order to make the surface of the element isolation portion 3 and the surface of the semiconductor substrate 1 flush with each other, after forming a silicon oxide film, the surface is formed using a CMP (Chemical Mechanical Polishing) method or the like. Polishing is performed as needed.

Next, a gate insulating film 4 made of, for example, a silicon oxide film or the like is formed on the semiconductor substrate 1. After that, for example, a conductive polycrystalline silicon layer (conductive layer) serving as the gate electrode 5 is formed on the gate insulating film 4 by CVD (Chemical
After being formed using a vapor deposition method, an insulating film 6 made of, for example, a silicon oxide film is formed thereon (FIG. 2).

Next, after a photoresist film 7 is applied on the semiconductor substrate 1, the photoresist film 7 is used as an etching mask for forming a pattern of the gate electrode 5 using a photolithography technique. A pattern is formed (FIG. 3).

In this case, when forming the pattern (gate electrode pattern) of the photoresist film 7 as an etching mask for forming the gate electrode 5 of the indirect peripheral circuit, a dummy gate electrode 5a (FIG. 4 (shown in FIG. 4) is formed as a pattern (pattern for a dummy gate electrode) of the photoresist film 7a as an etching mask.

In addition, photolithography techniques include:
After exposing the photoresist film 7 using a light exposure device, development and annealing are performed, and the pattern (gate) of the photoresist film 7 as an etching mask for forming the gate electrode 5 on the photoresist film 7 is formed. An electrode pattern is formed, and a pattern (dummy gate electrode pattern) of a photoresist film 7a is formed as an etching mask for forming a dummy gate electrode 5a near the gate electrode 5 of the indirect peripheral circuit. .

Further, as a photolithography technique, when exposing the photoresist film 7 using a light exposure apparatus, a Levenson type phase shift reticle (mask) is used.
Such a phase shift reticle (mask) can be used. In this case, by disposing a photoresist film 7a having a dummy gate electrode pattern near the photoresist film 7 having a gate electrode pattern,
Since a phase shift reticle (mask) can be used, the contrast can be increased and the resolution can be improved.

Next, using the photoresist film 7 and the photoresist film 7a as an etching mask, using a selective etching technique such as dry etching,
Unnecessary regions of the insulating film 6, the conductive polycrystalline silicon layer, and the gate insulating film 4 are removed to form a pattern of a gate region having a pattern of the gate electrode 5, and a pattern of a dummy gate electrode 5a at the same time. A pattern of a dummy gate region is formed (FIG. 4).

In this case, the two gate electrodes 5 at the center of the memory array area are partly used as first gate gate electrodes and are also used as DRAM word lines (word lines; WL). The gate electrode 5 adjacent to the gate electrode 5 is used as a wiring layer.

FIG. 9 is a plan view corresponding to the semiconductor integrated circuit device of the present embodiment shown in FIG. In this case, FIG.
Corresponds to a cross-sectional view showing a cross section taken along line AA of FIG.

According to the above-described manufacturing method, the dummy gate electrodes 5a are provided on both sides of the gate electrode 5 of the indirect peripheral circuit (the gate electrode 5 having a large separation distance between the adjacent gate electrodes 5).
Is arranged, when forming the pattern of the photoresist film 7 as an etching mask when forming the pattern of the gate electrode 5, the dummy gate electrode 5 is formed.
The pattern of the photoresist film 7a as an etching mask when forming the pattern a is simultaneously formed. Therefore, using photolithography technology,
When forming the pattern of the photoresist film 7, the photoresist film 7 a is located near the pattern of the photoresist film 7.
Is formed at the same time, exposure of the photoresist film 7 in a region other than the pattern of the design specification can be prevented, so that the same pattern as the pattern of the design specification can be formed on the photoresist film 7 with high accuracy.

As a result, the pattern of the gate electrode 5 can be formed by using the photoresist film 7 having the same pattern as the pattern of the design specification as an etching mask by using the selective etching technique. Of the gate electrode 5 can be formed with high precision.

Next, after forming sidewall spacers 8 on the side walls of the gate electrode 5 and the dummy gate electrode 5a, an n-type semiconductor region 9 serving as a source / drain of the MOSFET is formed (FIG. 5).

In this case, after an insulating film such as a silicon oxide film is formed on the semiconductor substrate 1 including the side walls of the gate electrode 5 and the dummy gate electrode 5a by using the CVD method, photolithography and selective etching are performed. By removing the insulating film in an unnecessary region by using the technique, a sidewall spacer 8 made of an insulating film is formed on the side wall of the gate electrode 5 and the dummy gate electrode 5a.

After that, an n-type impurity such as phosphorus is ion-implanted from above the semiconductor substrate 1 into the p-type well 2 by using an ion implantation method. An n-type semiconductor region 9 serving as a drain is formed. Thereafter, although not shown, a p-type impurity such as boron is ion-implanted into the n-type well from above the semiconductor substrate 1 using an ion implantation method, and then an annealing process is performed. MOSFE
A p-type semiconductor region serving as a source / drain of T is formed.

Next, after an insulating film 10 is formed on the semiconductor substrate 1, a through hole (connection hole) is formed in the insulating film 10.
Is formed, and a plug 11 is formed in the through hole (FIG. 6). In this case, a planarized insulating film 10 is formed by, for example, forming a silicon oxide film by a CVD method as the insulating film 10 and then polishing the surface to planarize the surface. The flattening treatment may employ a mode in which the surface of the insulating film 10 is flattened by, for example, a CMP method or an etch-back method.

Next, after forming a through hole in a selective region of the insulating film 10 by using a photolithography technique and a selective etching technique, a conductive material such as a conductive polycrystalline silicon film is buried in the through hole. Thus, the plug 11 is formed.

In this case, a through hole is formed between the gate electrode 5 and the dummy gate electrode 5a with a self-alignment structure using a self-alignment technique. Therefore, the manufacturing process can be simplified. As a result, by forming a through-hole having a self-alignment structure, the plug 11 embedded therein can be miniaturized, and electrical characteristics such as reduction of contact resistance and diffusion layer parasitic capacitance can be improved.

Next, after an insulating film 12 such as a thin silicon oxide film is formed on the semiconductor substrate 1, a through hole is formed in the insulating film 12 on a specific plug 11, and then, for example, an aluminum layer or the like is formed. Is formed (FIG. 7). In this case, the wiring layer 13 in the area of the memory array
Are bit lines (bit lines; BL) of the DRAM.

Next, as shown in FIG. 8, an insulating film 14 is formed on the semiconductor substrate 1. The insulating film 14 is formed by, for example, forming a silicon oxide film by a CVD method, polishing the surface, and flattening the surface to form a flattened insulating film 14. In this case, the insulating film 14 is, for example, a PSG (Phoshod) which is a silicon oxide film containing phosphorus.
BPSG (Boro Phospho S), which is a pho Silicate Glass film or a silicon oxide film containing boron and phosphorus
An ilicate glass (Silicon Glass) film or an SOG (Spin On Glass) film that can be formed by a spin coating method can be used.

Thereafter, through holes are formed in selective regions of the insulating film 14 and the insulating film 12 thereunder by using a photolithography technique and a selective etching technique, and then, for example, conductive polycrystalline silicon or tungsten is formed in the through holes. Plug 15 by embedding a conductive material such as
To form

Next, COB (Capacitor) is placed on the semiconductor substrate 1.
A storage node (storage electrode) 16 which is an electrode of a capacitor of a tor over bitline type memory cell is formed.
The storage node 16 is formed by depositing a conductive polycrystalline silicon layer containing an impurity such as phosphorus on the semiconductor substrate 1 by a CVD method and then patterning the layer using a lithography technique and a selective etching technique. Form. In this case, the storage node 16
It has a function as a lower electrode of a capacitor which is a capacitor for storing information of a memory cell.

Next, a dielectric film 17 is deposited on the semiconductor substrate 1 including the storage node 16. Dielectric film 17
Are, for example, Si ₃ N ₄ (silicon nitride), Ta ₂
O ₅ (tantalum pentoxide) or PZT which is a ferroelectric film
(Lead zirconate titanate) or the like is deposited. Thereafter, a plate electrode 18 which is an electrode of a capacitor is formed on the semiconductor substrate 1. The plate electrode 18 is formed by depositing a conductive polycrystalline silicon layer containing impurities such as phosphorus on the semiconductor substrate 1 by a CVD method and then patterning the layer using a photolithography technique and a selective etching technique. Form. In this case, the plate electrode 18 has a function as an upper electrode in a capacitor which is a capacitance element for storing information of a memory cell.

Next, an insulating film 19 as an interlayer insulating film is formed on the semiconductor substrate 1. Thereafter, the insulating film 19 is formed by using a photolithography technique and a selective etching technique.
Through holes (not shown) are formed as necessary in the selective region of (1). The insulating film 19 is formed by, for example, forming a silicon oxide film by a CVD method, and then polishing the surface and performing a flattening process on the surface to thereby form the flattened insulating film 1.
9 is formed. The flattening process can adopt a mode in which the surface of the insulating film 19 is flattened by, for example, a CMP method or an etch-back method. The insulating film 19 is, for example, a PSG film which is a silicon oxide film containing phosphorus or a silicon oxide film B which is a silicon oxide film containing boron and phosphorus.
A PSG film, an SOG film formed by a spin coating method, or the like can be used.

Thereafter, a wiring layer 20 made of, for example, an aluminum layer is formed on the semiconductor substrate 1. In this case, the wiring layer 20 is a power supply wiring layer.

The wiring layer 13 and the wiring layer 2 described above are used.
When forming 0, the dummy gate electrode 5a disposed on the element isolation portion 3 above the p-type semiconductor region such as the p-type well 2 is connected to a reference voltage line (for example, a reference voltage of 0 V is provided. (Interconnect wiring layer). A mode in which the dummy gate electrode 5a arranged on the element isolation portion 7a on the n-type semiconductor region is connected to a power supply voltage line (for example, a wiring layer having a voltage of 2.5 V to 3.3 V). It can be.

By applying this aspect, the parasitic depletion layer in the semiconductor region below the dummy gate electrode 5a can be reduced, so that a parasitic leak current between MOSFETs adjacent to the semiconductor region can be prevented.

Next, by forming a passivation film (not shown) on the semiconductor substrate 1, the DRAM is formed.
The manufacturing process of the semiconductor integrated circuit device having the above is ended.

According to the semiconductor integrated circuit device of the present embodiment and the method of manufacturing the same, dummy electrodes are provided on both sides of the gate electrode 5 of the indirect peripheral circuit (the gate electrode 5 having a large separation distance between adjacent gate electrodes 5). By arranging the gate electrode 5a, when forming the pattern of the photoresist film 7 as an etching mask when forming the pattern of the gate electrode 5, etching when forming the pattern of the dummy gate electrode 5a is performed. The pattern of the photoresist film 7a as a mask for use is simultaneously formed. Therefore, when the pattern of the photoresist film 7 is formed using the photolithography technique, the photoresist film 7a is simultaneously formed in the vicinity of the pattern of the photoresist film 7, so that the pattern other than the pattern of the design specification can be obtained. Since the exposure of the photoresist film 7 in the region can be prevented, the same pattern as the design specification pattern can be formed on the photoresist film 7 with high accuracy.

As a result, the pattern of the gate electrode 5 can be formed by using the photoresist film 7 having the same pattern as the pattern of the design specification as an etching mask by using the selective etching technique. Of the gate electrode 5 can be formed with high precision. Therefore, variation in the shape of the gate electrode 5 can be prevented, variation in electrical characteristics such as a threshold voltage can be prevented, and the electrical characteristics can be controlled with high accuracy. In addition, since a timing mismatch or the like can be prevented, a high-performance and highly reliable semiconductor integrated circuit device can be obtained.

According to the semiconductor integrated circuit device of this embodiment and the method of manufacturing the same, gate electrode 5 of the indirect peripheral circuit is provided.
(Gate electrode 5 having a large separation distance between adjacent gate electrodes 5) and dummy gate electrodes 5a disposed on both sides of the gate electrode 5 are formed by the same manufacturing process. Further, a through hole is formed between the gate electrode 5 and the dummy gate electrode 5a with a self-alignment structure using a self-alignment technique. Therefore, the manufacturing process can be simplified. As a result, by forming a through-hole having a self-alignment structure, the plug 11 embedded therein can be miniaturized, and electrical characteristics such as reduction of contact resistance and diffusion layer parasitic capacitance can be improved. It is possible to increase the degree of integration and performance of the circuit device and increase the number of layers in the wiring structure.

According to the semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment, dummy gate electrode 5a arranged on element isolation portion 3 above a p-type semiconductor region such as p-type well 2 Can be used as a reference voltage line (for example, a wiring layer having a reference voltage of 0 V), and the dummy gate electrode 5a disposed on the element isolation portion 5a on the n-type semiconductor region is Power supply voltage line (for example, 2.5V ~
(A wiring layer having 3.3 V). As a result, the parasitic depletion layer in the semiconductor region below the dummy gate electrode 5a can be reduced, and a parasitic leak current between adjacent MOSFETs can be prevented by the semiconductor region. Semiconductor integrated circuit device.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, according to the present invention, in addition to the DRAM, the SR
The present invention can be applied to a semiconductor integrated circuit device having a memory system such as an AM (Static Random Access Memory) and a method for manufacturing the same. It is possible to adopt a mode of disposing only in

Further, the present invention relates to a MOSFET, a CMOS,
DR with FET, BiCMOSFET, etc. as constituent elements
The present invention can be applied to a semiconductor integrated circuit device having a memory system such as an AM or an SRAM and a method of manufacturing the same.

Further, the present invention relates to a MOSFET, a CMO
The present invention can be applied to various semiconductor integrated circuit devices such as a logic system including SFETs, BiCMOSFETs, bipolar transistors, and the like as components, and a method of manufacturing the same.

[0052]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, dummy gate electrodes are arranged on both sides of a gate electrode (a gate electrode having a large separation distance between adjacent gate electrodes) such as an indirect peripheral circuit. When forming the pattern of the photoresist film as an etching mask when forming the pattern of the gate electrode, simultaneously forming the pattern of the photoresist film as the etching mask when forming the pattern of the dummy gate electrode. ing. Therefore, when forming the pattern of the photoresist film using the photolithography technology, the photoresist film is simultaneously formed in the vicinity of the pattern of the photoresist film. Since the exposure of the resist film can be prevented, the same pattern as the design specification pattern can be formed on the photoresist film with high accuracy.

As a result, the pattern of the gate electrode can be formed by using a selective etching technique using a photoresist film having the same pattern as the pattern of the design specification as an etching mask. An electrode pattern can be formed with high precision. Therefore, variation in the shape of the gate electrode can be prevented, variation in electrical characteristics such as threshold voltage can be prevented, and electrical characteristics can be controlled with high accuracy. In addition, by being able to prevent timing mismatches,
A high-performance and highly reliable semiconductor integrated circuit device can be obtained.

(2). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, a gate electrode (a gate electrode having a large separation distance between adjacent gate electrodes) such as an indirect peripheral circuit and dummy gates arranged on both sides of the gate electrode The electrodes are formed by the same manufacturing process. Also,
A through hole is formed between the gate electrode 5 and the dummy gate electrode 5a with a self-alignment structure using a self-alignment technique. Therefore, the manufacturing process can be simplified. As a result, by forming a through-hole having a self-aligned structure, it is possible to finely structure a plug embedded therein and to improve electrical characteristics such as reduction of contact resistance and diffusion layer parasitic capacitance. It is possible to increase the degree of integration and performance of the device and increase the number of layers in the wiring structure.

(3). According to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, the dummy gate electrode disposed on the element isolation portion above the p-type semiconductor region such as the p-type well is connected to the reference voltage line (for example, 0V). And a dummy gate electrode disposed on the element isolation portion above the n-type semiconductor region is connected to a power supply voltage line (for example, 2.5 V to 3 V). 0.3 V). As a result, the parasitic depletion layer in the semiconductor region below the dummy gate electrode can be reduced, so that the M
By preventing a parasitic leak current between OSFETs and the like, a semiconductor integrated circuit device having high performance and high reliability can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing process of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device according to one embodiment of the present invention;

FIG. 9 is a plan view corresponding to the semiconductor integrated circuit device according to the embodiment of the present invention shown in FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Well 3 Element isolation part 4 Gate insulating film 5 Gate electrode 5a Dummy gate electrode 6 Insulating film 7 Photoresist film 7a Photoresist film 8 Side wall spacer 9 Semiconductor region 10 Insulating film 11 Plug 12 Insulating film 13 Wiring layer 14 Insulating film 15 Plug 16 Storage node 17 Dielectric film 18 Plate electrode 19 Insulating film 20 Wiring layer

Claims (9)

[Claims] 1. A semiconductor integrated circuit device, wherein a dummy gate electrode of the same layer as the gate electrode is arranged adjacent to a specific gate electrode. 2. The semiconductor integrated circuit device according to claim 1, wherein said dummy gate electrode is arranged on both sides of said specific gate electrode. 3. The semiconductor integrated circuit device according to claim 2, wherein a contact hole is arranged between said specific gate electrode and said dummy gate electrode adjacent thereto. Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein a distance between the specific gate electrode and a gate electrode adjacent to the specific gate electrode is different from the specific gate electrode. A semiconductor integrated circuit device which is larger than the separation distance between the gate electrodes in the region. 5. The semiconductor integrated circuit device according to claim 1, wherein said dummy gate electrode disposed on a field insulating film on a p-type semiconductor region comprises: A semiconductor integrated circuit device, wherein the dummy gate electrode is a reference voltage line, and the dummy gate electrode disposed on the field insulating film above the n-type semiconductor region is a power supply voltage line. 6. The semiconductor integrated circuit device according to claim 1, wherein said dummy gate electrode comprises:
A semiconductor integrated circuit device which is arranged adjacent to a gate electrode of an indirect peripheral circuit in a memory type semiconductor integrated circuit device. 7. A step of forming a field insulating film in a selective region on a surface of a semiconductor substrate, forming a gate insulating film on the semiconductor substrate, and forming a gate electrode on the gate insulating film. After forming a conductive layer, a step of forming an insulating film on the conductive layer, After forming a photoresist film on the semiconductor substrate, using a photolithography technique, the photoresist film Forming a gate electrode pattern and forming a dummy gate electrode pattern adjacent to a specific gate electrode pattern; and etching the photoresist film having the gate electrode pattern and the dummy gate electrode pattern. Using a selective etching technique as a mask, pattern the conductive layer to form a gate electrode and a dummy gate electrode And a method for manufacturing a semiconductor integrated circuit device. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein, when forming the field insulating film, the surface of the field insulating film is formed to be flush with the surface of the semiconductor substrate. A method for manufacturing a semiconductor integrated circuit device, comprising: 9. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said dummy gate electrode is formed adjacent to a gate electrode of an indirect peripheral circuit in a memory-based semiconductor integrated circuit device. A method for manufacturing a semiconductor integrated circuit device, comprising: