JPH10340951A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, wherein the size of a contact hole is smaller than the resolution of photolithography and irregularities in the dimension of the contact hole is restrained, and its manufacturing method. SOLUTION: An N-type impurity diffusion layer region 17 of the surface layer of a semiconductor substrate 3 and a wiring layer 5 are electrically connected by embedding a connection wiring layer 6 in a contact hole 2 penetrating an insulating film 4 and a slit formed on the wiring layer 5. When the contact hole 2 is patterned by photolithography, exposure to light is performed by using a mask having a mask pattern 2a with which a slit overlapping perpendicular to the slit of the wiring layer 5 is formed on a photoresist. When the contact hole 2 is formed by etching, only the insulating film 4 is eliminated by applying the selecting ratio of the insulating film 4 and the wiring layer 5. The size of the aperture of the contact hole 2 is prescribed on a region, in which the slit of the wiring layer 5 and the mask pattern 2a overlap with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a method for forming a semiconductor substrate and an interlayer insulating film on the surface of the semiconductor substrate by forming a connection conductor layer in a minute contact hole. The present invention relates to a semiconductor device that is electrically connected to a wiring layer formed through the semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art As miniaturization of semiconductor devices progresses, processing of wiring layers and contact holes becomes more difficult year by year. Particularly recently, the dimension of the opening of the contact hole is required to be smaller than the resolution of photolithography.
Contact structures called side wall contacts have been used. In this sidewall contact structure, a film such as an oxide film is formed on a side wall (side wall) of the contact hole.

A conventional method of manufacturing a semiconductor device using the structure of the side wall contact will be described with reference to FIG. 7, focusing on a method of forming a contact hole in which a silicon oxide film is formed in the side wall. FIG.
FIG. 11 is a diagram for explaining a conventional method for manufacturing a semiconductor device. A conventional semiconductor device is manufactured through the steps shown in FIGS. 7A to 7F shown in FIG.

First, in FIG. 7A, an N-type impurity diffusion layer region 117 is partially formed in a surface layer of a semiconductor substrate 103, and the N-type impurity diffusion layer region 11 of the semiconductor substrate 103 is formed.
An element isolation region 116 is formed in a portion except for the N-type impurity diffusion layer region 117 on the surface on the seventh side. The insulating film 10 is formed on the surface of the N-type impurity diffusion layer region 117 and the element isolation region 116.
4 is formed. Then, in order to form a contact hole in the insulating film 104, the surface of the insulating film 104 is patterned with a photoresist 112 by photolithography.

Next, in FIG. 7B, the exposed portion of the insulating film 104 is removed by anisotropic dry etching, and a contact hole 102 reaching the surface of the N-type impurity diffusion layer region 117 is formed in the insulating film. 104.

Next, referring to FIG. 7C, after the photoresist 112 is removed, the surface of the insulating film 104, the side wall of the contact hole 102, the N-type impurity diffusion layer region 11 are removed.
7 on the surface of oxide film 113 serving as a side wall.
It is formed by a D (Chemical Vapor Deposition) method.
As this oxide film 113, HTO (High Temperature
Oxide) or the like having good coverage (coverability) is used.

Next, in FIG. 7D, an oxide film 11 is formed.
The portion 3 except for the side wall of the contact hole 102 is removed by anisotropic dry etching.

Next, as shown in FIG. 7E, a polysilicon layer serving as a connection wiring layer 114 is grown inside the contact hole 102 where the oxide film 113 is formed on the side wall and on the surface of the insulating film 104. The surface of the connection wiring layer 114 is patterned with a photoresist 115 by photolithography.

Next, in FIG. 7F, a portion of the connection wiring layer 114 which is not covered with the photoresist 115 is removed by dry etching. Thereafter, the photoresist 115 is peeled off, and a semiconductor device having a contact hole using an oxide film as a sidewall is manufactured.

In such a conventional semiconductor device, since the side wall of the contact hole 102 is covered with the oxide film 113, the size of the opening of the contact hole can be reduced, and patterning of the contact hole is performed by photolithography. In this case, even if the alignment with the N-type impurity diffusion layer region located on the bottom surface of the contact hole or the wiring layer is shifted, the risk of short circuit is reduced.

In the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 4-355951, a first wiring layer and a second wiring layer formed on the surface of the first wiring layer via an insulating film are formed by contact holes. After forming the first and second wiring layers for electrical connection, a contact hole penetrating through the second wiring layer and the insulating film and reaching the first wiring layer is formed.
Then, by forming a metal plug in the contact hole, the first wiring layer and the second wiring layer are electrically connected. In such a semiconductor device, when patterning the contact hole by photolithography, the margin for positioning the contact hole is increased.

[0012]

However, in the method of forming a contact hole using a side wall, the size of the opening of the contact hole depends not only on the resolution size of photolithography but also on the thickness of the side wall. In addition, it is difficult to obtain a contact hole having a uniform size due to a variation in an oxide film for a sidewall formed by a CVD method and a variation in an etching rate when etching back the entire surface of a wafer. Further, even if the opening size of the contact hole deviates from the intended size after etching back the surface of the semiconductor device, it is difficult to correct the processing size.

In the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 4-355951, the opening size of the contact hole is large.
Since there is no margin for alignment of the contact hole with the wiring layer, there is a problem that the width of the wiring layer must be increased.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, an object of the present invention is to electrically connect an impurity diffusion layer region of a semiconductor substrate and a wiring layer or two wiring layers formed in different layers. An object of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, in which the size of a contact hole formed in the semiconductor device is made smaller than the resolution of photolithography to reduce the risk of a short circuit. It is another object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a contact hole having a uniform size.

[0015]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor substrate in which an impurity diffusion layer region is partially formed in a surface layer, and a semiconductor substrate having a surface on the impurity diffusion layer region side. A wiring layer formed via an interlayer insulating film;
A connection wiring layer formed in a portion of the interlayer insulating film corresponding to the impurity diffusion layer region inside a contact hole penetrating the interlayer insulating film to electrically connect the impurity diffusion layer region and the wiring layer; A slit passing through a portion of the wiring layer corresponding to the contact hole in the interlayer insulating film in the wiring layer, and a part of the connection wiring layer is formed inside the slit. It is characterized by being embedded.

Further, according to the present invention, there is provided a semiconductor substrate in which an impurity diffusion layer region is partially formed in a surface layer, a first wiring layer arranged on the impurity diffusion layer region side of the semiconductor substrate, A second wiring layer formed on the surface of the wiring layer opposite to the semiconductor substrate side with an interlayer insulating film interposed therebetween, and the interlayer insulating film in a portion of the interlayer insulating film corresponding to the first wiring layer. A semiconductor device comprising: a connection wiring layer formed inside a contact hole penetrating a film and electrically connecting the first wiring layer and the second wiring layer;
A slit is formed in the first wiring layer through a portion of the first wiring layer corresponding to the contact hole of the interlayer insulating film, and a part of the connection wiring layer is embedded in the slit. It is characterized by having.

Further, according to the present invention, there is provided a step of partially forming an impurity diffusion layer region in a surface layer of a semiconductor substrate, and forming a wiring layer on the surface of the semiconductor substrate on the side of the impurity diffusion layer via an interlayer insulating film. Performing a first photolithography and a first etching to expose at least a portion of a portion of the wiring layer corresponding to the impurity diffusion layer region, thereby exposing the interlayer insulating film; Removing at least a part of the exposed portion by second photolithography and second etching to form a contact hole reaching the surface of the impurity diffusion layer region; and inside the contact hole and the contact hole Forming a connection wiring layer inside the hole of the wiring layer that communicates with the semiconductor device. The bets lithography, of the wiring layer, wherein the exposure is performed using a mask having a pattern as the slits are formed by the first etching a portion corresponding to the impurity diffusion layer region.

Further, in the second photolithography, a slit perpendicular to the slit formed in the wiring layer is formed in the photoresist, and the slit in the wiring layer overlaps the slit in the photoresist. Exposure is performed using a mask having such a pattern, and in the second etching, the wiring layer is not removed by setting the etching selectivity between the interlayer insulating film and the wiring layer, so that the interlayer insulating film is not removed. Preferably, only the film is removed.

Further, according to the present invention, there is provided a step of forming a first wiring layer on one surface side of a semiconductor substrate, and forming a second wiring layer on the surface of the first wiring layer via an interlayer insulating film. And exposing at least a part of a portion of the second wiring layer corresponding to the first wiring layer by first photolithography and first etching to expose the interlayer insulating film; At least a part of the exposed portion of the interlayer insulating film is subjected to a second photolithography and a second photolithography.
Forming a contact hole reaching the surface of the first wiring layer by removing the wiring by etching, and forming a connection wiring layer inside the contact hole and inside a hole of the second wiring layer communicating with the contact hole. Forming,
In the method of manufacturing a semiconductor device, the first photolithography includes forming the first wiring pattern on the second wiring layer.
The exposure is performed by using a mask having a pattern such that a slit is formed by the first etching in a portion corresponding to the wiring layer.

Further, in the second photolithography, a slit perpendicular to the slit formed in the first wiring layer is formed in the photoresist, and the slit in the first wiring layer is formed in the photoresist. Exposure is performed using a mask having a pattern such that the slits of the resist overlap with each other. In the second etching, the selectivity of etching between the interlayer insulating film and the second wiring layer is determined to obtain the second etching. Preferably, the second wiring layer is not removed, and only the interlayer insulating film is removed.

According to the invention as described above, when removing at least a part of the wiring layer corresponding to the impurity diffusion layer region in order to form a contact hole in the interlayer insulating film, the first photolithography requires the wiring Exposure was performed using a mask having a pattern such that a slit was formed by the first etching in a portion of the layer corresponding to the impurity diffusion layer region. Thereby, the interlayer insulating film is exposed to the slit formed in the wiring layer by the first etching, and a part of the interlayer insulating film exposed to the slit part of the wiring layer is subjected to the second photolithography and the second etching. By the removal, a contact hole is formed in the interlayer insulating film. In such a contact hole, since the size of the contact hole is determined by the width of the slit in the interlayer insulating film, the uniformity of the opening size of the contact hole in manufacturing a semiconductor device is improved.
Further, since the shape of the hole in the wiring layer is a slit, the margin for positioning the contact hole with respect to the slit in the wiring layer when forming the contact hole in the interlayer insulating film is widened. Further, the width of the slit in the wiring layer and the opening size of the contact hole are determined by the width of the slit formed in the photoresist by the first photolithography. Therefore, after the first photolithography step, if the width of the slit of the photoresist is out of a prescribed dimension by measuring the width of the slit, the photoresist is peeled off and the photoresist is formed again by the first photolithography. By doing so, the width of the slit in the wiring layer can be adjusted to a desired size. As a result, a contact hole having a target opening dimension is formed.

In the second photolithography,
A slit perpendicular to the slit formed in the wiring layer is formed in the photoresist, and the slit of the photoresist is overlapped with the slit in the wiring layer. After the formation of the photoresist, the interlayer insulating film is removed by a second etching to form a contact hole in the interlayer insulating film. At this time, in the second etching, the wiring layer is not removed because the etching selectivity between the interlayer insulating film and the wiring layer is set, and the interlayer insulating film is removed. Therefore, the size of the opening of the contact hole in the interlayer insulating film is defined by the region where the slit of the wiring layer and the slit of the photoresist in the second photolithography overlap, and the contact hole smaller than the resolution of the photolithography is defined. Can be formed.

Further, the method of forming a structure for electrically connecting an impurity diffusion layer region and a wiring layer in the above-described method of manufacturing a semiconductor device is described in the case of electrically connecting two wiring layers formed in different layers. Can be applied to For example, when a first wiring layer disposed on one surface side of a semiconductor substrate is electrically connected to a second wiring layer formed on the surface of the first wiring layer via an interlayer insulating film. Forming a contact hole in the interlayer insulating film sandwiched between the first and second wiring layers, and forming a connection wiring layer inside the contact hole. In order to electrically connect the first wiring layer and the second wiring layer even when manufacturing such a semiconductor device, the uniformity of the opening size of the contact hole can be reduced by using the above-described manufacturing method. improves. Further, a contact hole smaller than the resolution of photolithography can be formed.

[0024]

Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view and a top view showing a first embodiment of a semiconductor device of the present invention. FIG. 1A is a cross-sectional view illustrating the semiconductor device of the present embodiment, and FIG. 1B is a top view of the semiconductor device illustrated in FIG.

In the semiconductor device of this embodiment, as shown in FIG. 1A, an N-type impurity diffusion layer region 17 is partially formed in the surface layer of the semiconductor substrate 3 which is a P-type silicon substrate. I have. An element isolation region 16 is formed in a portion of the surface of the semiconductor substrate 3 on the side of the N-type impurity diffusion layer region 17 excluding the N-type impurity diffusion layer region 17.

The insulating film 4 is laminated on the entire surface of the N-type impurity diffusion layer region 17 and the element isolation region 16. On the surface of the insulating film 4, a wiring layer 5 having a shape corresponding to a pattern of a mask used when manufacturing a semiconductor device is formed. In a portion of the insulating film 4 corresponding to the N-type impurity diffusion layer region 17, the contact hole 2 penetrates from one surface of the insulating film 4 to the other surface.

The connection wiring layer 6 is formed in the contact hole 2.
Is embedded, the N-type impurity diffusion layer region 1
6 and the wiring layer 5 are electrically connected.

Further, as shown in FIG. 1B, a slit is formed in the wiring layer 5 so as to pass through a portion of the wiring layer 5 corresponding to the contact hole 2 of the insulating film 4. By embedding the connection wiring layer 6 in the slit of the wiring layer 5 or in the contact hole 2, the connection wiring layer 6
The wiring layer 5 and the N-type impurity diffusion layer region 16 are electrically connected via the. The wiring layer 5 and the connection wiring layer 6 are electrically connected at the side wall of the slit in the wiring layer 5. In order to form the contact hole 2 as described later, a semiconductor substrate on which a photoresist has been applied in advance is exposed by photolithography using a mask. A part of the mask pattern used in this exposure is the mask pattern 2a shown in FIG.

Next, a method for manufacturing the above-described semiconductor device of the present embodiment will be described. 2 and 3 are views for explaining the method for manufacturing the semiconductor device of the present embodiment.
FIGS. 2A to 3E are cross-sectional views taken along a line AA ′ shown in FIG. 1B, and FIGS. 2A and 2B are views (a ′) shown in FIGS. (E ') is a sectional view taken along line BB' shown in (b) of FIG. The semiconductor device of the present embodiment is manufactured through the steps of FIG. 3E and FIG. 3E from FIG. 2A and FIG.

First, in FIGS. 2A and 2A, an element isolation region 16 is formed on the surface of a P-type semiconductor substrate 3. Then, the element isolation region 16 is partially removed,
An N-type impurity diffusion layer region 17 is formed on the surface of the semiconductor substrate 3 exposed by removing the element isolation region 16. On the entire surface of the element isolation region 16 and the N-type impurity diffusion layer region 17,
After forming an oxide film as the insulating film 4 using the CVD method,
A 200-nm-thick polysilicon film is formed as a wiring layer 5 on the entire surface of the insulating film 4 by using a CVD method. Wiring layer 5
For example, a wiring material other than polysilicon, for example, tungsten silicide by a sputtering method may be used, or a multilayer structure may be formed by a combination of a CVD method and a sputtering method. Thereafter, a photoresist 7 is applied to the entire surface of the wiring layer 5 and exposed using a mask having a pattern of a desired shape to form a photoresist 7 having a pattern of a desired shape on the surface of the wiring layer 5. I do. In the first photolithography step of patterning the photoresist 7, slits are formed in portions of the wiring layer 5 corresponding to the N-type impurity diffusion layer regions 17 as shown in FIGS. Exposure is performed using a mask having a pattern in which is formed. Then, the wiring layer 5
A portion of the wiring layer 5 not covered with the photoresist 7 is removed by anisotropic first etching to form a slit in the wiring layer 5.

Next, in FIGS. 2B and 2B, after forming a slit in the wiring layer 5 by anisotropic etching, the photoresist 7 is peeled off. Then, a photoresist 8 is applied to the surface of the wiring layer 5 or the exposed surface of the insulating film 4 and is exposed using a mask having a pattern of a desired shape. Is formed. A part of the mask pattern used here is the mask pattern 2a shown in FIG. In the second photolithography, a slit perpendicular to the slit of the wiring layer 5 is formed in the photoresist 8 and a mask having a pattern in which the slit of the wiring layer 5 and the slit of the photoresist 8 overlap with each other is used. Exposure is performed using

Next, referring to FIGS. 2C and 2C, the insulating film 4 is removed by anisotropic second etching, and a contact hole penetrating the insulating film 4 is formed.
At this time, since the anisotropic etching is performed under the condition that the etching selectivity between the insulating film 4 and the wiring layer 5 is high, only the insulating film 4 is removed without removing the wiring layer 5;
Actually, the contact hole is formed only in a region where the slit of the wiring layer 5 and the slit of the photoresist 8 overlap.

Next, in FIGS. 3D and 3D, the photoresist 8 is peeled off, and the wiring layer is formed inside the contact hole, the surface of the wiring layer 5 and the surface of the exposed insulating film 4. As 9, a material having good coverage such as polysilicon is formed by a CVD method.

Thereafter, as shown in FIGS. 3E and 3E, a so-called etch back for removing the surface layer of the wiring layer 9 is performed to manufacture a semiconductor device.

As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the slit formed in the wiring layer 5 and the second
The contact hole 2 is formed by removing the insulating film 4 exposed to the slit formed in the photoresist by the photolithography and the second etching. Accordingly, since the size of the opening of the contact hole 2 is defined by the region where the slit of the wiring layer 5 and the slit of the photoresist in the second photolithography overlap, the size of the opening of the contact hole is determined by photolithography. It can be smaller than the resolution. Further, since the slit of the photoresist 8 is vertically overlapped with the slit of the wiring layer 5, the margin of the alignment of the slit of the photoresist 8 with respect to the wiring layer 5 is widened.

Further, the size of the opening of the contact hole 2 is determined by the opening width of each of the slit of the wiring layer 5 formed by the first photolithography and the slit of the photoresist in the second photolithography. . Therefore, the dimensions of the opening width of the slit formed in the photoresist by the respective steps of the first and second photolithography are measured, and when the dimensions are out of the prescribed dimensions, the photoresist is peeled off, By repeating the photolithography process again, a contact hole having a desired size can be formed.

(Second Embodiment) FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. 4A and 4B are cross-sectional views illustrating the semiconductor device of the present embodiment, and FIG. 4B is a cross-sectional view taken along AA ′ of FIG.
It is a line sectional view.

In the semiconductor device of this embodiment, as shown in FIG. 4A, an N-type impurity diffusion layer region 37 is partially formed in the surface layer of the semiconductor substrate 23 which is a P-type silicon substrate. I have. An element isolation region 36 is formed in a portion other than the N-type impurity diffusion layer region 37 on the surface of the semiconductor substrate 23 on the N-type impurity diffusion layer region 37 side.

Then, the insulating film 14 is stacked on the entire surface of the N-type impurity diffusion layer region 37 and the element isolation region 36, and the insulating film 10 is further stacked on the surface of the insulating film 14.
On the surface of the insulating film 10, a wiring layer 1 having a shape corresponding to a pattern of a mask used when manufacturing a semiconductor device is provided.
5 are formed. Also, the insulating film 10 and the insulating film 14
In a portion corresponding to the N-type impurity diffusion layer region 37, a contact hole 22 penetrating the insulating film 10 and the insulating film 14 is formed.

As can be seen from FIGS. 4A and 4B, a slit is formed in the wiring layer 15 so as to pass through a portion of the wiring layer 15 corresponding to the contact hole 22. The hole 22 communicates. In the slit of the wiring layer 15 and the contact hole 22
The connection wiring layer 26 is embedded therein. Connection wiring layer 2
The wiring layer 15 is electrically connected to the wiring layer 15 at the side wall of the slit of the wiring layer 15, and the wiring layer 15 and the N-type impurity diffusion layer region 27 are electrically connected via the connection wiring layer 26. ing.

The surface of the wiring layer 15, the surface of the insulating film 10,
The capacitor insulating film 18 is formed on the exposed portion of the connection wiring layer 26, and the counter electrode 19 is formed on the surface of the capacitor insulating film 18. In the semiconductor device having the above configuration, the wiring layer 1
5 is provided as a capacitor electrode (storage electrode).

Next, a method of manufacturing the above-described semiconductor device of the present embodiment will be described. 5 and 6 are views for explaining the method for manufacturing the semiconductor device of the present embodiment.
FIGS. 5 (a) to (g) shown in FIGS. 5 and 6 are sectional views shown in FIG. 4 (a), and FIGS. 5 (a) to (g ') shown in FIGS. Is a cross-sectional view shown in FIG. The semiconductor device of the present embodiment is manufactured through the steps shown in FIG. 6A and FIG. 6G from FIG. 5A and FIG.

First, referring to FIGS. 5A and 5A, an element isolation region 36 is formed on the surface of a P-type semiconductor substrate 23. Then, the element isolation region 36 is partially removed, and an N-type impurity diffusion layer region 37 is formed on the surface of the semiconductor substrate 23 where the element isolation region 36 has been removed and exposed. An oxide film or a borophosphosilicate glass (BPSG) film is formed as an insulating film 14 over the entire surface of the element isolation region 36 and the N-type impurity diffusion layer region 37 by using the CVD method. As the film thickness 2
A 00 nm oxide film is formed. Thereafter, the entire surface of the insulating film 10 is formed as a wiring layer 15 with a film thickness of 20 using a CVD method.
A 0 nm polysilicon film is formed. The wiring layer 15 may be made of a wiring material other than polysilicon, for example, tungsten silicide by sputtering, or C
A multilayer structure may be obtained by combining the VD method and the sputtering method. Thereafter, a photoresist 27 is applied to the entire surface of the wiring layer 15 and exposed using a mask having a pattern of a desired shape to form a photoresist 27 having a pattern of a desired shape on the surface of the wiring layer 15. I do. In the first photolithography step of patterning the photoresist 27, a pattern in which a slit is formed in a portion of the wiring layer 15 corresponding to the N-type impurity diffusion layer region 37 as shown in FIG. Exposure is performed using the mask. Thereafter, a portion of the wiring layer 15 that is not covered with the photoresist 27 is removed by anisotropic first etching, and a slit is formed in the wiring layer 15 as shown in FIG.

Next, as shown in FIGS. 5B and 5B, after forming a slit in the wiring layer 15 by anisotropic first etching, the photoresist 27 is peeled off. Then, an insulating material such as BPSG is formed as the insulating film 11 on the surface of the wiring layer 15 or the exposed surface of the insulating film 10 to planarize the surface.

Next, in FIGS. 5C and 5C, the surface layer of the insulating film 11 is removed by etching until the surface of the wiring layer 15 is exposed. Then, a photoresist 28 is applied to the surfaces of the wiring layer 5 and the insulating film 11 and is exposed using a mask having a pattern of a desired shape, and the photoresist 28 having a pattern of a desired shape is formed on the surface of the wiring layer 15. To form In the second photolithography, a slit perpendicular to the slit of the wiring layer 15 is formed in the photoresist 28 and the slit of the wiring layer 15 and the slit of the photoresist 28 are formed similarly to the first embodiment. Exposure is performed using a mask having an overlapping pattern.

Next, as shown in FIGS. 5D and 5D, the insulating film 11, the insulating film 10 and the insulating film 14 are removed by anisotropic second etching, and the contact hole 2 is removed.
Form 2 At this time, the second etching is performed on the insulating film 1.
Since the etching is performed under the condition that the etching selectivity between 0, 11, and 14 and the wiring layer 15 is high, only the insulating film 14 is removed without removing the wiring layer 15, and the contact hole 22 is actually formed. What is the slit of the wiring layer 15,
This is only the region where the slits of the photoresist 28 overlap.

Next, as shown in FIGS. 6E and 6E, the photoresist 28 is removed and the contact hole 2 is removed.
2 and the surface of the wiring layer 15 and the exposed insulating film 1
A material having good coverage, such as polysilicon, is formed as a connection wiring layer 26 on the surface of the substrate 4 by a CVD method.

Next, in FIGS. 6F and 6F, the surface layer of the connection wiring layer 26 is removed by etching until the surface of the wiring layer 15 is exposed.

Next, as shown in FIGS. 6G and 6G, the wiring layer 5 is connected to the DR as in the semiconductor device of this embodiment.
When used as a storage electrode of an AM (dynamic random access memory), the insulating film 11 other than the inside of the hole of the wiring layer 15 is removed by wet etching. Insulating film 1
0 serves as a stopper for wet etching, so that the insulating film 10
Use a material that is less likely to be etched. in this case,
For example, a silicon oxide film is used as the insulating film 10, a BPSG film is used as the insulating film 11, and a solution containing hydrofluoric acid is used as an etchant.

Thereafter, after forming the capacitance insulating film 18 on the surface of the wiring layer 15 and the connection wiring layer 26 and the surface of the insulating film 11, the counter electrode 19 is formed on the surface of the capacitance insulating film 18 to obtain the structure shown in FIG. Is manufactured.

As described above, in the method of manufacturing a semiconductor device according to the present embodiment, as in the first embodiment, the slit formed in the wiring layer 15 and the slit formed in the photoresist by the second photolithography are used. The contact holes 22 are formed by removing the exposed insulating films 10 and 14 by the second etching. Therefore, the size of the opening of the contact hole 22 depends on the wiring layer 1.
Since the slit of No. 5 and the slit of the photoresist in the second photolithography overlap each other, the size of the opening of the contact hole can be made smaller than the resolution of the photolithography. Further, since the slit of the photoresist 28 is vertically overlapped with the slit of the wiring layer 15, the margin for positioning the slit of the photoresist 28 with respect to the wiring layer 15 is widened.

Further, the size of the opening of the contact hole 22 is determined by the opening width of each of the slit of the wiring layer 15 formed by the first photolithography and the slit of the photoresist in the second photolithography. . Therefore, the dimensions of the opening width of the slit formed in the photoresist by the respective steps of the first and second photolithography are measured, and when the dimensions are out of the prescribed dimensions, the photoresist is peeled off, By repeating the photolithography process again, a contact hole having a desired size can be formed.

In the first and second embodiments described above, the semiconductor device having the structure in which the N-type impurity diffusion layer region of the surface layer of the semiconductor substrate is electrically connected to the wiring layer, and the method of manufacturing the semiconductor device However, the semiconductor device according to the present invention and the method of manufacturing the semiconductor device are not limited to those described in the first and second embodiments. For example, a first wiring layer is arranged on one surface side of a semiconductor substrate,
In the case where a second wiring layer is formed on the surface of the first wiring layer via an interlayer insulating film, the first and second wiring layers are electrically connected to each other. A manufacturing method may be applied. In this case, after a slit is formed in the second wiring layer by the first photolithography and the first etching, a photoresist having a slit vertically overlapping the slit of the second wiring layer is applied to the second wiring layer. It is formed by photolithography. Then, a region of the interlayer insulating film sandwiched between the first and second wiring layers where the slit of the second wiring layer and the slit of the photoresist overlap is removed by a second etching to form a contact hole. I do. Then, in the contact hole or the second
The first and second wiring layers are electrically connected by embedding the connection wiring layer in the slit of the wiring layer.

[0055]

As described above, according to the present invention, in the first photolithography, a mask having a pattern such that a slit is formed by a first etching in a portion of a wiring layer corresponding to an impurity diffusion layer region. When the contact hole is formed by removing at least a part of the interlayer insulating film exposed to the slit formed in the wiring layer by the second etching,
The size of the contact hole is defined by the width of the slit in the wiring layer. Therefore, there is an effect that the opening size of the contact hole is made uniform. In addition, there is an effect that a minute contact hole can be formed by reducing the width of the wiring layer. In addition, when a contact hole is formed in the interlayer insulating film, there is an effect that a margin for positioning the contact hole in the length direction of the slit of the wiring layer is widened. Further, since the opening size of the contact hole is defined by the width of the slit of the wiring layer, the width of the slit corresponding to the slit of the wiring layer in the photoresist in the first photolithography step is measured, and the width is defined. If the size is out of the range, the photoresist can be peeled off and another photoresist can be formed again. Therefore, there is an effect that the contact hole can be adjusted to a target size by re-forming the photoresist.

In the second photolithography, a photoresist having a slit vertically overlapping with the slit in the wiring layer is formed, and in the second etching, the photoresist slit in the second photolithography and the wiring layer are formed. Since the contact hole is formed by removing the interlayer insulating film in the area where the slit overlaps,
There is an effect that a contact hole having an opening smaller than the resolution of photolithography can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional view and a top view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.

FIG. 4 is a cross-sectional view illustrating a second embodiment of the semiconductor device of the present invention.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device shown in FIG.

FIG. 7 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

[Explanation of symbols]

 2, 22 contact hole 2a mask pattern 3, 23 semiconductor substrate 4, 10, 11, 14 insulating film 5, 15 wiring layer 6, 26 connection wiring layer 7, 8, 27, 28 photoresist 16, 36 element isolation region 17, 37 N-type impurity diffusion layer region 18 Capacitive insulating film 19 Counter electrode

Claims (6)

[Claims] A semiconductor substrate in which an impurity diffusion layer region is partially formed in a surface layer; a wiring layer formed on a surface of the semiconductor substrate on the side of the impurity diffusion layer region via an interlayer insulating film; A connection wiring layer formed in a contact hole of the insulating film corresponding to the impurity diffusion layer region and penetrating the interlayer insulating film and electrically connecting the impurity diffusion layer region and the wiring layer; A slit passing through a portion of the wiring layer corresponding to the contact hole of the interlayer insulating film in the wiring layer, and a part of the connection wiring layer is embedded in the slit. A semiconductor device characterized in that: 2. A semiconductor substrate in which an impurity diffusion layer region is partially formed in a surface layer, a first wiring layer disposed on the impurity diffusion layer region side of the semiconductor substrate, and A second wiring layer formed on the surface opposite to the semiconductor substrate side via an interlayer insulating film,
A connection wiring layer formed in a contact hole penetrating the interlayer insulating film at a portion corresponding to the first wiring layer to electrically connect the first wiring layer and the second wiring layer; A slit passing through a portion of the first wiring layer corresponding to the contact hole of the interlayer insulating film in the first wiring layer, and the connection wiring is formed inside the slit. A semiconductor device in which a part of a layer is embedded. 3. a step of partially forming an impurity diffusion layer region in a surface layer of a semiconductor substrate; and a step of forming a wiring layer on a surface of the semiconductor substrate on the impurity diffusion layer region side via an interlayer insulating film; Removing at least a part of a portion of the wiring layer corresponding to the impurity diffusion layer region by first photolithography and first etching to expose the interlayer insulating film; and exposing the exposed portion of the interlayer insulating film. Removing at least part of the portion by second photolithography and second etching to form a contact hole reaching the surface of the impurity diffusion layer region; and forming the contact hole inside the contact hole and communicating with the contact hole. Forming a connection wiring layer inside the hole of the wiring layer, wherein the first photolithography is performed. In, of the wiring layer,
A method of manufacturing a semiconductor device, comprising: performing exposure using a mask having a pattern in which a slit is formed by the first etching in a portion corresponding to the impurity diffusion layer region. 4. In the second photolithography,
Slits perpendicular to the slits formed in the wiring layer are formed in the photoresist, and exposure is performed using a mask having a pattern in which the slits in the wiring layer and the slits in the photoresist overlap. 4. The semiconductor according to claim 3, wherein in the second etching, the wiring layer is not removed and only the interlayer insulating film is removed by setting an etching selectivity between the interlayer insulating film and the wiring layer. 5. Device manufacturing method. 5. A step of forming a first wiring layer on one surface side of a semiconductor substrate, and a step of forming a second wiring layer on a surface of the first wiring layer via an interlayer insulating film; Removing at least a portion of a portion of the second wiring layer corresponding to the first wiring layer by first photolithography and first etching to expose the interlayer insulating film; Removing at least a part of the exposed portion by second photolithography and second etching to form a contact hole reaching the surface of the first wiring layer;
Forming a connection wiring layer inside a hole of the second wiring layer that communicates with the contact hole. In the first photolithography, And a step of performing exposure using a mask having a pattern such that a slit is formed by the first etching in a portion corresponding to the first wiring layer. 6. In the second photolithography,
A slit perpendicular to the slit formed in the first wiring layer is formed in the photoresist and
Exposure is performed using a mask having a pattern in which the slit of the wiring layer and the slit of the photoresist overlap with each other. In the second etching, the interlayer insulating film and the second
6. The method of manufacturing a semiconductor device according to claim 5, wherein the second wiring layer is not removed but only the interlayer insulating film is removed by setting the etching selectivity with respect to the wiring layer.