JPH10339765A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a constitution of an IC suppressing the increase of external terminal of the IC in testing a block to be tested and enabling testing at frequency in normal operation and analyzing failure locations. SOLUTION: Test input signals are inputted in a test circuit 1 in time division from an external input terminal and is extended in parallel using a test input interface circuit 10a and stored in RAM 20a. The stored test input signal is read out in normal frequency of the IC, supplied to a testing block 3 and executes tests. Then, the test output signal as the test results is stored in RAM 20b in normal operation frequency of the IC. This test output signal is outputted to an external output terminal in time division using a test output interface circuit 10b and compared with an expected value with an external tester, and the IC is judged good or bad.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (hereinafter referred to as an IC), and more particularly, to a functional test of an internal block provided with a logic circuit and a plurality of independently accessible RAMs or at least one multiport RAM. Relating to an IC that can be used.

[0002]

2. Description of the Related Art Random logic ICs including RAMs include ASICs such as gate arrays, cell-based ICs, and DSPs.
(ICs for specific applications), etc., and the scale of these IC chips is rapidly increasing and their structures are becoming more complicated. At present, the controllability and observability of the IC internal blocks as viewed from outside the ICs are poor and poor. Analysis tests are difficult. Therefore, it is necessary to design a circuit so that the controllability and observability of the IC internal block can be improved to facilitate the test. For this reason, in general, a circuit is designed in the IC for facilitating the test, and at the time of the test, the test is performed using the test function.

In the design stage, the purpose of the above-mentioned failure analysis test is to verify a circuit portion having a small margin for a required operation speed, to find a portion where a failure is likely to occur in the design of an IC, to carry out a simulation and an actual test. There is a discovery of a malfunctioning portion due to a timing deviation from a circuit, and a discovery of a defect generated in a process of manufacturing an IC at the time of mass production and selection.

Conventionally, as a test of an internal block of an IC, there is a method as shown in FIG.

[0005] In this method, a test circuit for a test mode such as a selector is inserted in advance for each functional block inside the IC, and a test input signal input from an external terminal is selected based on a command from a control circuit 124 during a test. 121
, And outputs the output from the test block 123 to an external terminal via the selector 122 based on a command from the control circuit 124 for testing by an external tester. The input pattern of the IC and the expected output value corresponding to the input pattern created in advance by simulation etc. are input to the memory of the tester, and whether or not the IC outputs the expected value in response to the input to the tester Is determined using a comparator inside the tester. If the output of the IC matches all expected values, the test has passed.

However, according to this method, a test input signal is input to the block under test 123 from an external terminal.
To output a test output signal to an external terminal, external terminals are required by the number of input / output terminals of the block under test 123, which increases costs.

For example, there are two systems of 20-bit input terminals,
Tested block 1 having one 20-bit output terminal
In order to test 23, a total of 60 terminals are required only for the terminals connected to the data lines. Securing more than 60 external terminals for testing will significantly increase the cost of the IC package.

In order to solve this, a method of inputting / outputting a test signal in a time-division manner using a small number of external terminals has been considered. For example, as shown in FIG. 13, there is a method of time-divisionally inputting a test input signal from a small number of input terminals.
That is, a test input signal input in a time-sharing manner from an external input terminal is sequentially distributed to a register 134 via a selector 131 by a command from a control circuit 135, and the test input signal is supplied to a test block 133 via a selector 132. Is to give.

As shown in FIG. 14, there is a method of time-divisionally outputting a test output signal from a small number of output terminals. In this method, the test output pattern output from the block under test 142 is time-divided by the selector 141 in response to a command from the control circuit 143 and output to an external terminal.

As an application of the test method for reducing the number of input / output terminals, Japanese Patent Application Laid-Open Nos. 61-11677 (Publication 1), Japanese Patent Application Laid-Open No. 2-57989 (Publication 2), and No. 66892 (publicly known document 3)
Has disclosed a test method using a RAM built in a chip. Known Document 1 is to reduce the number of external output terminals by storing a test output signal from a block under test using a RAM which is not used for an original functional circuit and outputting the test output signal in a time-division manner. . Known Documents 2 and 3 disclose that a test input signal is input in a time-division manner, stored in a first RAM, supplied to a block under test, and output as a test output signal and a second RAM.
The number of external input terminals and the number of external output terminals are both reduced by comparing and judging the expected value inputted in advance in the device.

[0011]

However, in the conventional method of inputting / outputting a test signal in a time-division manner, the conventional method of inputting / outputting a test signal is restricted by the capability of the transistor of the IC itself and the capability of the tester depending on the degree of the time-division. It is often not possible to test at frequencies.

For example, a test input signal is applied to a block under test operating with a system clock of 10 MHz.
It is assumed that the test is performed by dividing the test output signal into two. If the operating frequency of the tester needs to be 60 MHz in order to perform the test of the block under test at the normal operating frequency by dividing the total into six, a tester corresponding to a test speed of 60 MHz or more is required, and the IC itself The test interface circuit and the like also need transistors capable of supporting a test speed of 60 MHz.

[0013] Increasing the capacity of a cell or using a high performance tester just for testing is wasteful and not a practical method.

Further, as disclosed in the above-mentioned known documents 2 and 3, the method of performing the expected value comparison inside the device makes it difficult to specify a defective portion when a defect occurs in a test.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to suppress an increase in the number of external terminals of an IC at the time of testing a block under test while suppressing the increase in the number of external terminals of the IC at a system clock frequency during normal operation. An object of the present invention is to provide an IC configuration that enables testing and analysis of a defective portion.

[0016]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit, comprising: an arithmetic processing circuit that performs a predetermined arithmetic processing; An internal circuit test means for testing is formed integrally with the arithmetic processing circuit, and the internal circuit test means inputs a time-divided test input signal from the outside and develops the test input signal in parallel. These are input to the circuit under test, and a test output signal output from the circuit under test is time-divided and output to an external terminal. A first circuit for storing the test input signals and outputting them to the circuit under test at a system clock frequency used during normal operation of the circuit under test.
And a second RAM which can be accessed independently of the first RAM to which the test output signal output from the circuit under test is input at the system clock frequency.
And characterized in that:

According to the above invention, a test input signal is time-divisionally input from an external test terminal of the IC, developed into a parallel test input signal using a test input interface circuit or the like, and these are input to the first RAM. Store. After storing a series of test input signals, the test input signal is
, And outputs the test output signal from the test block output at the normal operating frequency to the second RA at the same time.
Write to M in order. After storing a series of test output signals, the test output signals are time-divided from the second RAM using a test output interface circuit or the like and output to the test external terminal.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
In order to solve the above problem, an internal circuit test means for testing the arithmetic processing circuit using an arithmetic processing circuit for performing predetermined arithmetic processing as a circuit under test is formed integrally with the arithmetic processing circuit, and The circuit test means inputs a time-division-divided test input signal from the outside, expands the test input signal in parallel, inputs them to the circuit under test, and outputs a test output signal output from the circuit under test. Wherein the internal circuit testing means stores the test input signals developed in parallel and uses them during normal operation of the circuit under test. A first port that outputs to the circuit under test at a clock frequency, and the test output signal that is output from the circuit to be tested is connected to the system clock. It is characterized in that it comprises one or more multi-port RAM and a second port that are input by the number.

According to the above invention, the test input signal is time-divided from the test external terminal and developed into a parallel test input signal using the test input interface circuit and the like, and these are transmitted from the first port to the multi-port RAM. In order. After storing a series of test input signals,
A test input signal is sequentially output from the first port of the multi-port RAM to the test block at the normal operating frequency of the IC, and at the same time, a test output signal from the test block output at the normal operating frequency of the IC is output to the multi-port RAM. R
The data is sequentially written from the second port of the AM to the address where the test input signal already used is stored. When the storage of a series of test output signals is completed, the test output signals are time-divided from the multiport RAM using a test output interface circuit or the like and output to the test external terminal.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS.

As shown in FIG. 1, the main parts of the IC of this embodiment are a test circuit 1 as an internal circuit test means and a test block 3 as an arithmetic processing circuit and a circuit under test.
It is composed of Further, the test circuit 1 includes a test input interface circuit 10a, a test output interface circuit 10b, a RAM 20a as a first RAM,
RAM 20b as a second RAM, signal holding registers 30a, 30b, signal path selecting selectors 40a, 4b
0b, 40c, 40d and a control circuit 50. The RAMs 20a and 20b are those used for the arithmetic processing of the normal operation of the IC and are diverted for testing, and can be accessed independently of each other.

In the method of testing the block under test 3, the control circuit 50 uses three test modes, that is, a test pattern input mode, a test execution mode, and a test output mode, in order during testing. Here, the control circuit 50 has two input terminals (not shown), and mode switching is performed by inputting a 2-bit code corresponding to each mode to these input terminals. For example, in the normal operation mode, A code of “00”, a code of “01” in the test pattern input mode, a code of “11” in the test execution mode, and a code of “10” in the test output mode are input. When the above code is input, the control circuit 50
A mode control signal is output to each circuit inside C to set the mode. FIG. 6 shows a flow of mode switching in the present embodiment.

First, the IC enters a test pattern input mode in response to a mode control signal from the control circuit 50. FIG. 2 shows an example of the configuration and processing of a part used in the test pattern input mode.

In this mode, a test input signal is input to the test input interface circuit 10a in a time-division manner from the external input terminals whose number is smaller than the number of input terminals of the block under test 3, and this is input into the test input interface circuit 10a. Are developed into parallel test input signals before division by using the selector 11a and the register 12a.

The developed test input signal is supplied to the RAM 20a through the signal path selection selector 40a, and the signal path selection selector 40a increments the address of the RAM 20a and successively outputs the test input signal to the RAM 2a.
0a. RAM2 for all test input signals
After storing it in 0a, the mode is entered into the test execution mode by the mode control signal from the control circuit 50. FIG. 3 shows an example of the configuration and processing of a part used in the test execution mode. FIG.
Shows a timing example in the test execution mode. In the test execution mode, the test input signals stored in the RAM 20a are sequentially read out at the normal operation frequency, supplied to the block under test 3, and the output signals are sequentially stored in the RAM 20b.

As shown in FIG. 4, the test input signal of the step n at an arbitrary timing stored in the RAM 20a operates normally at the timing taken by the LOW active RAM 20a read enable signal (OE bar) from the address A _In of the RAM 20a. read in frequency, it is generated as an output I _n of RAM 20a. RAM
20a is an output of the test input signal I _n register signals held at the timing of the fall of the system clock 30
a, and is supplied to the block under test 3 through the signal path selection selector 40b as an output of the signal holding register 30a. Test output signal O _n from the test block 3 is supplied through the signal path selection selector 40c after uptake in timing signal holding register 30b of the fall of the next system clock to RAM 20b. Test output signal O _n is stored at the timing taken by RAM 20b write enable signal LOW active (WE bar) to the address A _On the RAM 20b. Step n + 1, step n + 2,. . .
In the same manner as described above, supply of test patterns and storage of output patterns are performed one after another, and all test output signals are stored in the RAM 20b.
, The test output mode is entered by the mode control signal from the control circuit 50.

FIG. 5 shows an example of the configuration and processing of a portion used in the test output mode.

In the test output mode, the test output signals stored in the RAM 20b are sequentially supplied to the test output interface circuit 10b, and the register 12b and the selector 1 in the test output interface circuit 10b are provided.
1b, the parallel data is time-divided and sequentially output to a small number of external output terminals via the signal path selection selector 40d.

The output test output signal is compared with an expected value by an external tester to determine the quality of the IC.

In the test, the external input terminal and the external output terminal are used individually. However, the same terminal can be switched for input in the input mode and switched for output in the output mode. It is also possible to reduce the number of external terminals by sharing terminals.

In the present invention, since the output obtained by operating the block under test 3 at the frequency of the system clock can be inspected, the test at the normal operating frequency can be realized with a small number of external input / output terminals.

Embodiment 2 Another embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, the first embodiment is described.
Components having the same functions as those shown in the drawings are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 7, the main part of the IC according to the present embodiment includes a test circuit 2 as an internal circuit test means,
It comprises an arithmetic processing circuit and a block under test 3 as a circuit under test. The test circuit 2 further includes a test input interface circuit 10a, a test output interface circuit 10b, a multiport RAM 4, signal holding registers 30a and 30b, and a signal path selecting selector 40.
a, 40b, 40c, and 40d, and a control circuit 50. Further, the multi-port RAM 4 is used for a test, which is used for the arithmetic processing of the normal operation of the IC.

In the method of testing the block under test 3, as in the first embodiment, three modes of the test pattern input mode, the test execution mode, and the test output mode are used at the time of testing.
Switch between two test modes in order. FIG. 6 shows a flow of mode switching.

First, the IC enters a test pattern input mode in response to a mode control signal from the control circuit 50. FIG. 8 shows an example of the configuration and processing of a part used in the test pattern input mode.

In this mode, the test input signal is input to the test input interface circuit 10a in a time-division manner from external input terminals less than the number of input terminals of the block under test 3, and the selector 11a inside the test input interface circuit 10a is By using the register 12a, it is developed into a parallel test input signal before division. The developed test input signal is supplied to the A port 4a as the first port of the multiport RAM 4 through the signal path selecting selector 40a. The signal path selection selector 40a
The address of the A port 4a of the multiport RAM 4 is incremented, and the test input signal is successively input to the multiport R4.
The data is stored in the AM 4 using the A port 4a. When all the test input signals are stored in the multi-port RAM 4, the test execution mode is entered by the mode control signal from the control circuit 50.

FIG. 9 shows an example of the configuration and processing of a portion used in the test execution mode. FIG. 10 shows a timing example in the test execution mode.

In the test execution mode, the multiport RA
The test input signal stored in M4 is read out one after another from the A port 4a at the normal operation frequency and supplied to the block under test 3, and its output signal is
Are sequentially stored from the B port 4b as the second port to the address where the used pattern is stored.

The test input signal of the step n at an arbitrary timing stored in the multiport RAM 4 is the A port 4 which is LOW active from the address A _In of the A port 4a.
read at normal operating frequency at a timing taken by a read enable signal (OE bar) is generated as an output I _n of the A port 4a. Test input pattern I _n that as the output of the A port 4a is taken into the signal holding register 30a at the timing of the fall of the system clock, the test through the signal path selection selector 40b as the output of the signal holding register 30a Block 3
Supplied to

The multiport RAM4 test output signal O _n through the signal path selection selector 40c after being taken into the signal holding register 30b at the timing of the falling edge of the next system clock from the test block 3 B
It is supplied to port 4b. Test output signal O _n it is completed the supply of the test input signal already against test target block 3 from the A port 4a, LO to the address A _On that finished with
It is stored at the timing taken by the W active B port 4b write enable signal (WE bar). Step n + 1, step n + 2,. . . The test input signal is supplied and the test output signal is stored one after another in the same manner as described above. When all the test output signals are stored in the multi-port RAM 4 from the B port 4b, the test output mode is set by the mode control signal from the control circuit 50. enter. FIG.
Represents an example of the configuration and processing of a part used in the test output mode.

In the test output mode, the multiport RA
The test output signal stored in M4 is sequentially supplied to the test output interface circuit 10b through the B port 4b, and the parallel data is time-division-divided using the register 12b and the selector 11b inside the output interface circuit 10b to select a signal path. Are sequentially output to a small number of external output terminals via the selector 40d. The output test output signal is compared with the expected value by an external tester,
The quality of the IC is determined.

As described above, in the present embodiment, the test input signal storage RAM and the test output signal storage RAM are integrated into one, so that the area of the IC chip is reduced in the first embodiment.
Can be reduced as compared with the case of

In the test, the external input terminal and the external output terminal are used individually. However, the same terminal can be switched for input in the input mode and output for the output mode. It is also possible to reduce the number of external terminals by sharing terminals.

According to the present invention, since the output obtained by operating the block under test 3 at the frequency of the system clock can be inspected, the test at the normal operating frequency can be realized with a small number of external input / output terminals.

[0045]

As described above, in the semiconductor integrated circuit according to the first aspect of the present invention, the internal circuit test means for testing the arithmetic processing circuit using the arithmetic processing circuit for performing the predetermined arithmetic processing as the circuit under test is described. The internal circuit test means is formed integrally with the arithmetic processing circuit, receives the time-divided test input signal from the outside, expands the test input signal in parallel, and then applies these to the circuit under test. In a semiconductor integrated circuit, a test output signal output from the circuit under test is inputted in a time-division manner and output to an external terminal. The internal circuit test means stores the test input signal developed in parallel. A first RAM that outputs these to the circuit under test at a system clock frequency used during normal operation of the circuit under test; Test output signal is configured to include the above-described first RAM and independently accessible second RAM that is entered in the system clock frequency.

Therefore, it is possible to test the functional block at the normal operation frequency without greatly increasing the number of test external terminals, and to analyze a defective portion.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising:
As described above, the internal circuit test means for testing the arithmetic processing circuit using the arithmetic processing circuit for performing the predetermined arithmetic processing as the circuit under test is formed integrally with the arithmetic processing circuit. Input a time-division-divided test input signal from the outside, expand the test input signal in parallel, and then input these to the circuit under test,
In a semiconductor integrated circuit in which a test output signal output from the circuit under test is time-divided and output to an external terminal, the internal circuit test means stores the test input signals developed in parallel and stores them. A first port outputting to the circuit under test at a system clock frequency used during normal operation of the circuit under test, and a second port receiving the test output signal output from the circuit under test at the system clock frequency And one or more multi-port RAMs having the following ports.

Therefore, similarly to the first aspect,
It is possible to perform a function block test at a normal operation frequency without greatly increasing the number of test external terminals, and to analyze a defective portion.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an internal circuit test means of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration and a process of a test pattern input mode according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of a configuration and a process of a test execution mode according to an embodiment of the present invention.

FIG. 4 is a timing chart in the test execution mode.

FIG. 5 is a block diagram illustrating an example of a configuration and a process of a test output mode according to an embodiment of the present invention.

FIG. 6 is an explanatory diagram of a mode switching flow in one embodiment of the present invention and another embodiment.

FIG. 7 is a block diagram showing a configuration of an internal circuit test means of a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 8 is a block diagram showing an example of the configuration and processing of a test pattern input mode according to another embodiment of the present invention.

FIG. 9 is a block diagram illustrating an example of a configuration and a process of a test execution mode according to another embodiment of the present invention.

FIG. 10 is a timing chart in the test execution mode.

FIG. 11 is a block diagram showing an example of the configuration and processing of a test output mode according to another embodiment of the present invention.

FIG. 12 is a block diagram illustrating a conventional method for testing an internal block of an IC.

FIG. 13 is a block diagram illustrating a test method of inputting a test input signal in a time-division manner in a test of an internal block of a conventional IC.

FIG. 14 is a block diagram illustrating a test method of outputting a test output signal in a time-division manner in a test of an internal block of a conventional IC.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Test circuit (internal circuit test means) 2 Test circuit (internal circuit test means) 3 Block under test (operation processing circuit, circuit under test) 20a RAM (first RAM) 20b RAM (second RAM) 4 Multiport RAM 4a A port (first port) 4b B port (second port)

Claims (2)

[Claims] An internal circuit test means for testing an arithmetic processing circuit using an arithmetic processing circuit for performing predetermined arithmetic processing as a circuit under test is formed integrally with the arithmetic processing circuit. Inputs a time-divided test input signal from the outside, expands the test input signal in parallel, inputs them to the circuit under test, and time-divides the test output signal output from the circuit under test. Wherein the internal circuit test means stores the test input signals developed in parallel and outputs them at a system clock frequency used during normal operation of the circuit under test. A first RAM that outputs to the circuit under test; and a test output signal that is output from the circuit under test is input at the system clock frequency. That the first of RA
A semiconductor integrated circuit, comprising: a second RAM that can be accessed independently of M. 2. An internal circuit test means for testing an arithmetic processing circuit using an arithmetic processing circuit for performing a predetermined arithmetic processing as a circuit under test, wherein the internal circuit testing means is formed integrally with the arithmetic processing circuit. Inputs a time-divided test input signal from the outside, expands the test input signal in parallel, inputs them to the circuit under test, and time-divides the test output signal output from the circuit under test. Wherein the internal circuit test means stores the test input signals developed in parallel and outputs them at a system clock frequency used during normal operation of the circuit under test. A first port that outputs to the circuit under test, and the test output signal that is output from the circuit under test is input at the system clock frequency A semiconductor integrated circuit comprising one or more multiport RAMs having a second port.