JPH10339763A - Detection method and system of input terminal competing pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily detect test patterns having a possibility of input terminal competition without using large disk capacity. SOLUTION: A system has a net list 1 showing the connection relation of an internal circuit; a terminal attribute library 2 distinguishing between data system and clock system of the terminal of internal block; a clock system/data system terminal judging part 3 going back the input from the clock terminal of each block based on the content of the net list 1 and the terminal attribute library 2, and making the input terminal connected to the clock terminal of the block among the input terminal of semiconductor integrated circuit to be a clock system terminal and the other to be a data system terminal; and a hazard pattern searching part 6 investigating whether there is a part changing in the same timing in the test pattern between the clock system terminals and between the clock system terminal, and the data system terminal based on the judgment results, and defining the test pattern with the part changing in the same timing to be an input terminal competing pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system and method for detecting an input terminal competition pattern in a tester for performing an electrical characteristic test of a semiconductor integrated circuit, for example, an LSI test.

[0002]

2. Description of the Related Art In a function test of an LSI, it is very difficult to generate a test pattern for operating all of the circuits of the LSI.
Input must be performed under complicated timing conditions. Therefore, in the LSI tester, if the drive timing on the input terminal side deviates, the sequential circuit inside the LSI may malfunction. To prevent this, a test pattern that operates differently due to the departure of the input timing may be used. Must not be given. Conventionally, the following method has been used to check whether there is a possibility of such a conflict between input terminals in a test pattern.

In a test pattern, with the same pattern number,
If there is a portion where a plurality of input patterns or bidirectional patterns are changing at the same time, the pattern is inserted and shifted so as to change one by one. This shifting pattern is
Create two books in ascending order and descending order. A simulation is performed on the pattern created in this way, and it is verified whether or not there is an expected value mismatch. If there is an expected value mismatch,
It is considered that the cause is that the pattern is shifted, that is, the original test pattern is a pattern that may cause a malfunction due to a shift in input timing. In order to identify the terminal that caused the failure, the simulation result of the original pattern and the shifted pattern is analyzed.

FIG. 5 is a block diagram showing a schematic configuration of a conventional input terminal competition pattern detection system. The input terminal competition pattern detection system includes a test pattern file 101, a shifted pattern creating unit 102, a shifted pattern file 103, a netlist 104, a simulation unit 105, a simulation result file 106,
An output unit 107 is provided.

A test pattern file 101 is a file in which test patterns for performing an electrical characteristic test of a semiconductor integrated circuit, for example, an LSI test, etc., are described in advance. The shift pattern creation unit 102 checks the possibility of conflict between the input terminals with respect to the test pattern described in the test pattern file 101, and shifts the timing of the test pattern that may possibly conflict so as not to conflict. Create Here, a test pattern (shifted pattern) in which the timing is shifted is created for a test pattern in which a test pattern input to each terminal changes at the same timing among a plurality of external terminals. The shift pattern file 4 is a file for describing the shift pattern created by the shift pattern creation unit 102.

The net list 104 shows the configuration of a circuit network of a semiconductor integrated circuit to be tested. The simulation unit 105 is a unit that reads a test pattern (shift pattern) described in the shift pattern file 4 and executes a simulation according to the netlist 104. Simulation result file 10
Numeral 6 is for describing the result executed by the simulation unit 105.
8 (printer, display, etc.).

Hereinafter, the operation of the input terminal competition pattern detection system will be described.

First, a shifted pattern creating unit 102 reads a test pattern described in a test pattern file 101, creates a pattern in which simultaneous change input terminals are shifted, and stores the shifted pattern in the shifted pattern file 103 in ascending or descending order. Describe. This shift pattern is created, for example, as follows.

FIG. 6A is a timing chart of a test pattern input to an external terminal of the semiconductor integrated circuit, and FIG. 6B is a timing chart of a shift pattern created from the test pattern shown in FIG. It is a timing chart. In the figure, C1 to C3 are clock system external terminals, and D1 to D4 are data system external terminals. In the test pattern of the external terminal C1, the rising (change) of the first clock coincides with the rising (change) of the first clock of the test pattern of the external terminal C2 (broken line a),
The rising of the third clock coincides with the rising of the second clock of the test pattern of the external terminal C2 (broken line c), and the rising of the fifth clock is the external terminal C2.
3, the rising edge of the second clock of the test pattern coincides with the rising edge of the second clock (broken line e), and the rising edge of the sixth clock coincides with the falling edge of the first clock of the test pattern of the external terminal D2. (Dashed line g). In the test pattern of the external terminal D3, the rising of the first clock coincides with the rising of the first clock of the test pattern of the external terminal D4 (broken line b), and the falling of the first clock is external. It coincides with the rising edge of the first clock of each test pattern of the terminals D1 and D2 (broken line d),
The rising of the second clock coincides with the falling of the first clock of the test pattern of the external terminal D4 (broken line g).

The pattern shifting process shown in FIG.
In the case of the ascending order, with respect to the simultaneous change pattern of the input terminals from the broken line a to the broken line g, a pattern in which the portion that changes at the same timing is shifted is created without considering the attribute of the input terminal. For example, as for the input terminal simultaneous change pattern at the broken line a, the change of the external terminal C2 is made one pattern later, whereby the inserted pattern length is increased. The input terminal simultaneous change pattern indicated by the broken line d is a case where the data system terminals are simultaneously changing. In this case, the pattern is also subject to shifting, and in each pattern, the pattern length increases by the number of simultaneously changing terminals minus one pattern. become.

When the shift pattern is created as described above, the simulation unit 105 executes a simulation according to the netlist 104 using the created shift pattern, and the result is described in the simulation result file 106. . The designer analyzes the expected value mismatched portion based on the simulation result described in the simulation result file 106, and corrects the pattern if it can analyze which terminal shift caused the expected value mismatch.

[0012]

However, the above-mentioned prior art has the following problems.

The first problem is that a very large amount of disk capacity is used to create a shift pattern. If ten input terminals are changing at the same time,
The number of patterns additionally inserted there is nine.
In particular, when a multi-bit data bus exists, since it generally changes simultaneously on a test pattern, the pattern length after insertion may be several tens of times.
For example, in the system shown in FIG. 5, in the operation of the data system terminal of the real circuit, several tens of
More than 100 terminals operate and the pattern length becomes enormous. In addition to the ascending pattern shown in FIG. 6, a descending pattern (a pattern in which C2 is changed first and C1 is shifted later) is also created. Affects increase in capacity. In addition, a useless pattern is created such that a shift pattern is created for data on the data bus, which should not cause a problem in operation even if there is a timing shift, which affects the increase in disk capacity. .

[0014] The second problem is that the operation of identifying the terminal causing the trouble is troublesome and time-consuming. It is necessary to determine the order of change in the terminals that caused the mismatch when expected values did not match in the simulation.
Since the patterns are shifted, it is necessary to correspond to the order of the pattern number where the expected value mismatch occurs in the original pattern. In addition, if there are many terminals that are changing at the same time, it is difficult to identify which terminal shift caused the malfunction. Otherwise, the terminal cannot be specified in many cases. Converting a pattern simply by using only a change in an input pattern as a key without considering a circuit and performing a simulation using the pattern causes this complexity.

An object of the present invention is to provide a system and a method capable of easily detecting a test pattern having a possibility of input terminal conflict without using a large amount of disk capacity.

[0016]

In order to achieve the above object, an input terminal competition pattern detecting method according to the present invention comprises the steps of: inputting a signal of a predetermined test pattern to each of input terminals of a semiconductor integrated circuit to form an internal circuit; A method for detecting an input terminal conflict pattern which may cause an input terminal conflict among the test patterns when verifying the operation of each block to be executed, the connection information of the internal circuit and the internal circuit being The input is traced back from the clock terminal of each block based on the terminal attribute information for distinguishing the data system and the clock system of the terminal of each block constituting the block and connected to the clock terminal of the block among the input terminals of the semiconductor integrated circuit. The input terminal is determined as a clock terminal, and the other input terminals are determined as data terminals. Among children, checks whether there is a portion that changes at the same timing in the test pattern, characterized in that the test pattern was a portion that changes at the same timing as the input terminal competition patterns.

An input terminal conflict pattern detection system according to the present invention is an input terminal tester for inputting a signal of a predetermined test pattern to each input terminal of a semiconductor integrated circuit to verify the operation of each block constituting an internal circuit. A system for detecting an input terminal conflict pattern that may cause a conflict between terminals, a file in which a test pattern input to each of the input terminals is described, and a netlist indicating a connection relationship of the internal circuit. A terminal attribute library for distinguishing a data system and a clock system of a terminal of each block constituting the internal circuit, and based on the contents of the netlist and the terminal attribute library, the input is traced back from the clock terminal of each block, The input terminal connected to the clock terminal of the block among the input terminals of the semiconductor integrated circuit is clicked. A clock system / data system terminal discriminating means for discriminating a clock system terminal and the other as a data system terminal; and a clock system / data system terminal discriminating means. Between the system terminal and the data system terminal, check whether there is a portion that changes in the test pattern at the same timing, a dangerous pattern search means as the input terminal competition pattern a test pattern that has a portion that changes at the same timing, It is characterized by having.

In the above case, the dangerous pattern searching means recognizes a portion of the input terminal competition pattern in which the clock system terminals or the clock system terminal and the data system terminal operate at the same time, and then adds a skew to these simultaneously operated terminals. The apparatus may further include a simulation unit configured to generate a pin delay command to be given, and performing a simulation according to a netlist using the pin delay command.

(Operation) If the connection relation of the internal circuit and the distinction between the data system and the clock system of the terminal of each block constituting the internal circuit are known, the input is traced for the clock terminal of each block in the internal circuit. This makes it possible to determine whether the input terminal of the semiconductor integrated circuit is a clock system or a data system.

In the present invention as described above, the conflict between the test patterns is checked after the clock-related terminals and the data-related terminals are distinguished based on the connection relationships of the circuits and the terminal attributes of the internal blocks. Such a waste that a conflict check between data is performed is avoided.

Further, the target is narrowed down by distinguishing the clock system terminal and the data system terminal in advance.
Using the key as a key to search for a dangerous part on the pattern (a part where there is a possibility of conflict), only necessary parts can be checked, and analysis can be performed easily.

In the present invention which generates a pin delay command, the input timing to the terminal can be shifted without creating a shift pattern as in the conventional case, so that the disk capacity becomes enormous as in the conventional case. It will not be.

Also, when a check is desired to be performed by simulation, since a combination of terminals which causes a conflict is obtained in advance, it is possible to analyze only a pin delay at a necessary portion.

[0024]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an input terminal conflict pattern detection system according to one embodiment of the present invention. This input terminal competition pattern detection system is a system that detects an input terminal competition pattern in a tester that performs an electrical characteristic test of a semiconductor integrated circuit, such as an LSI test. The configuration includes a netlist 1, a terminal attribute library 2, a clock / data terminal grouping unit 3, a clock / data terminal name file 4, a test pattern file 5, a dangerous pattern detection unit 6, and a report file 7.

The net list 1 shows the configuration of the circuit network of the semiconductor integrated circuit to be tested. The input can be traced back from the clock terminal of the internal block based on this list. The terminal attribute library 2 describes whether a terminal of a block used in the semiconductor integrated circuit is a data terminal or a clock terminal. These netlist 1 and terminal attribute library 2 are described in advance before the test.

The clock / data terminal discriminating section 3 discriminates the external terminal of the semiconductor integrated circuit into a clock terminal and a data terminal based on the contents described in the netlist 1 and the terminal attribute library 2. Here, since the clock system terminal can be determined by tracing the input from the clock terminal of the internal block, the other terminals are data system terminals.

The clock / data terminal name file 4 is
This is a file for describing the clock / data terminals determined by the clock / data terminal determination unit 3. The test pattern file 5 is a file in which test patterns for performing an electrical characteristic test of a semiconductor integrated circuit, for example, an LSI test, are described in advance.

The dangerous pattern detection unit 6 determines the input terminal between the input terminals based on the clock terminal name and data terminal name described in the clock / data terminal name file 4 and the test pattern described in the test pattern file 5. Search for test patterns that could cause a conflict. The test pattern searched for by the dangerous pattern detection unit 6 that may cause a conflict between input terminals is a report file 7.
Is described. The description content of the report file 7 can be output by the output unit 8 (a printer, a display, or the like).

Hereinafter, the operation of the input terminal competition detection pattern detection system will be described in detail.

First, the clock / data terminal discriminator 3
Reads the contents described in the netlist 1 and the terminal attribute library 2 and traces back the input of the clock system terminal of the block used inside the semiconductor integrated circuit, thereby obtaining the clock system for the external terminal of the semiconductor integrated circuit. And the data system is determined. The result of this determination is described in the file 4 of the file name of the clock / data system, for example, in a form in which each of the external terminals is grouped into a clock system and a data system.

Subsequently, the dangerous pattern search unit 6 reads the contents described in the clock / data terminal name file 4 and the test pattern file 5, and selects the external clock system from among the test patterns input to each external terminal. A test pattern having a portion that changes at the same timing in a test pattern input to each terminal is searched for between terminals and between a clock external terminal and a data external terminal. The search result is described in the report file 7 as a portion where a clock number (pattern number) corresponding to, for example, a portion that operates at the same timing as the terminal name may have an input conflict. The designer refers to the report information and corrects only necessary portions of the test pattern described in the test pattern file 5.

Next, a clock / data terminal determination unit 3
The discrimination between the clock system and the data system of the external terminal of the semiconductor integrated circuit in the above will be specifically described.

FIG. 2 is a diagram showing connections between internal blocks and external terminals of a semiconductor integrated circuit to be measured. As can be seen from FIG. 2, when the input of the clock terminal of FF1 constituting the internal block is traced back, the external terminals C1, C2
The clock terminal of the FF2 is connected to the external terminal C3 when its input is traced back. Similarly, when the input of the data terminal of FF1 is traced back, the external terminals D1, D2
And the data terminal of FF2 is connected to external terminals D3 and D4 when the input is traced back. From this,
The clock system and data system of the external terminal can be known by tracing the net list of the clock system terminal or the data system terminal of the internal block in the input direction until reaching the external terminal. In the present embodiment, the external terminals (C1 to C3) connected to the clock system terminals of the internal block when the netlist is traced in the input direction are determined to be the clock system, and the other external terminals (D1 to D4), that is, A terminal which has not been reached from any of the clock system terminals of the internal block is determined to be a data system.

Next, the search for a test pattern which may cause a conflict between input terminals in the dangerous pattern search unit 6 will be specifically described.

FIG. 3 is a timing chart of a test pattern input to each external terminal of the circuit shown in FIG. In FIG. 3, the test pattern of the external terminal C1 is such that the rising (change) of the first clock is the external terminal C1.
2 coincides with the rising (change) of the first clock of the test pattern (broken line a), and the rising of the third clock coincides with the rising of the second clock of the test pattern of the external terminal C2. (Dashed line c), the rising of the fifth clock coincides with the rising of the second clock of the test pattern of the external terminal C3 (dashed line e),
The rising of the sixth clock coincides with the falling of the first clock of the test pattern of the external terminal D2 (broken line g). In the test pattern of the external terminal D3, the rising of the first clock coincides with the rising of the first clock of the test pattern of the external terminal D4 (broken line b), and the falling of the first clock is external. Terminal D1,
D2 coincides with the rising edge of the first clock of each test pattern (broken line d), and the rising edge of the second clock coincides with the falling edge of the first clock of the test pattern of the external terminal D4. (Broken line g).

In the broken line a, the respective inputs of the clock-system external terminal C1 and the clock-system external terminal C2 are simultaneously activated, and when there is a skew in the input terminal, which clock operates first. The operation may change depending on the timing. Therefore, the test pattern of the external terminal C1 and the test pattern of the external terminal C2 are reported as dangerous patterns that may cause a conflict between input terminals at the rising edge (change portion) of the first clock. Similarly, in the dashed line c, the clock-system external terminal C1 and the clock-system external terminal C2 are simultaneously operating,
In the broken line e, the clock-system external terminal C1 and the clock-system external terminal C3 are operating at the same time, and in each case, if there is a skew in the input terminal, the operation depends on the timing of which clock operates first. May change. Therefore, the test pattern of the external terminal C1 and the test pattern of the external terminal C2 are reported as danger patterns that may cause conflict between input terminals at the rising of the third clock and the rising of the second clock. Test pattern of external terminal C1 and external terminal C3
Is reported as a dangerous pattern that may cause a conflict between input terminals at the rising edge of the fifth clock and the rising edge of the second clock.

On the other hand, the broken line b indicates the external terminal D of the data system.
No. 3 and the data system external terminal D4 are operating at the same time, but are not reported because they are data system external terminals and do not need to be regarded as a dangerous pattern. Dashed lines d and g
Similarly, is a pattern in which only the external terminals of the data system are operating at the same time, and there is no need to regard it as a dangerous pattern, so no report is made.

In the dashed line f, the clock-system external terminal C1 and the data-system external terminal D2 are operating simultaneously.
In this case, whether the data is taken in or not depends on the delay of the input terminal, and is reported as a dangerous pattern.

(Other Embodiments) FIG. 4 is a block diagram showing a schematic configuration of an input terminal conflict pattern detection system according to another embodiment of the present invention. In the figure, the same components as those shown in FIG. 1 are denoted by the same reference numerals.

This input terminal conflict pattern detection system is almost the same as the system shown in FIG. 1, except that the dangerous pattern search unit 6 'determines whether clock system external terminals or clock system data terminals and data system external terminals are simultaneously connected. A pin delay command file 17 that gives skew to simultaneously operating terminals after recognizing the operating part
Is different.

The simulation unit 10 executes a simulation according to the netlist 1 using the pin delay command generated by the dangerous pattern search unit 6. This simulation result can be output by the output unit 8. This allows the designer to analyze the effect of skew from the simulation results.

[0043]

According to the present invention configured as described above, it is possible to avoid the waste of checking the conflict between the data terminals as in the prior art, and it is not necessary to create a shift pattern. There is an effect that a huge disk capacity is not required.

Only where there is a possibility of conflict between input terminals, for example, a pattern number and a terminal name are reported.
Since the designer only has to check the pattern correction based on this information, there is an effect that the work of identifying the terminal causing the problem is easy and can be performed in a short time.

Furthermore, since a simulation can be performed with a pin delay added, there is an effect that it is easy to check how the expected value does not match if the deviation occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an input terminal conflict pattern detection system according to an embodiment of the present invention.

FIG. 2 is a diagram showing connections between internal blocks and external terminals of a semiconductor integrated circuit to be measured.

FIG. 3 is a timing chart of a test pattern input to each external terminal of the circuit shown in FIG.

FIG. 4 is a block diagram illustrating a schematic configuration of an input terminal conflict pattern detection system according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a conventional input terminal competition pattern detection system.

FIG. 6A is a timing chart of a test pattern input to an external terminal of the semiconductor integrated circuit;
FIG. 6B is a timing chart of a shift pattern created from the test pattern shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Net list 2 Terminal attribute library 3 Clock system / data system terminal discriminating part 4 Clock system / data system terminal name file 5 Test pattern file 6, 6 'Danger pattern search part 7 Report file 8 Output part 9 Pin delay command file 10 Simulation section

Claims (3)

[Claims] When a signal of a predetermined test pattern is input to each of input terminals of a semiconductor integrated circuit to verify the operation of each block constituting an internal circuit, a conflict between input terminals is checked from among the test patterns. A method for detecting an input terminal conflict pattern that may occur, based on connection information of the internal circuit and terminal attribute information for distinguishing a data system and a clock system of a terminal of each block constituting the internal circuit. The input is traced back from the clock terminal of each block, and among the input terminals of the semiconductor integrated circuit, the input terminal connected to the clock terminal of the block is determined as a clock terminal, and the other terminals are determined as data terminals. Check if there are any parts that change at the same timing in the test pattern between the terminals and between the clock and data terminals. Input terminals competing pattern detection method which is characterized in that the test pattern was a portion that varies in timing between the input terminal competition patterns. 2. A tester which inputs a signal of a predetermined test pattern to each input terminal of a semiconductor integrated circuit and verifies the operation of each block constituting an internal circuit may cause a conflict between input terminals. A system for detecting an input terminal conflict pattern, wherein a file in which a test pattern input to each of the input terminals is described, a netlist indicating a connection relationship between the internal circuits, and each block constituting the internal circuit A terminal attribute library for distinguishing a data system and a clock system of the terminal, and based on the contents of the netlist and the terminal attribute library, the input is traced back from the clock terminal of each block, and among the input terminals of the semiconductor integrated circuit, The input terminal connected to the clock terminal of the block is the clock terminal, and the other terminals are the data terminals A clock / data terminal discriminating means for discriminating between the clock-system terminals and between the clock-system terminals and the data-system terminals based on the result of the discrimination by the clock / data-terminal discriminating means. Danger pattern search means for examining whether there is a portion that changes at the same timing in the pattern, and using a test pattern having the portion that changes at the same timing as the input terminal competition pattern. Detection system. 3. The input terminal conflict pattern detection system according to claim 2, wherein the dangerous pattern search means recognizes a part of the input terminal conflict pattern in which clock-related terminals or clock-related terminals and data-related terminals operate simultaneously. And a simulation unit configured to generate a pin delay command for giving a skew to these simultaneously operating terminals, and further performing a simulation according to a netlist using the pin delay command. Terminal conflict pattern detection system.