JPH10335470A - Method for designing semiconductor integrated circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor integrated circuit that can control the delay of a clock signal with a high accuracy for the clock supply system of the semiconductor integrated circuit. SOLUTION: A design method includes a sequence circuit cell that is synchronized to a clock signal, a combination circuit cell that is operated by receiving the sequence circuit cell, an arrangement wiring treatment (S1) for a clock buffer cell for supplying a clock signal to the above sequence circuit cell, a treatment (S2) for analyzing the drive load of the clock buffer in a clock supply system that is obtained by the arrangement wiring treatment, and treatments (S3 and S4) for setting the drive capacity of the clock buffer according to the drive load of the clock buffer. The driving capacity is set according to the load of the clock buffer cell that is gripped by the arrangement wiring of the clock buffer cell, thus accurately controlling the skew of the clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock and signal supply technique in a semiconductor integrated circuit, and more particularly to a technique effective when applied to a semiconductor integrated circuit such as a microprocessor, a microcomputer and a data processor and a design method thereof. is there.

[0002]

2. Description of the Related Art In a clock synchronous type semiconductor integrated circuit, clock skew must be considered. The clock skew is a time difference between an edge change or a level change of a clock signal reaching a plurality of state elements such as flip-flops. For example, when the flip-flops disposed before and after the combinational logic circuit are operated using a non-overlapping two-phase clock signal, if the clock skew of the two-phase clock signal is too large, the flip-flop is input to the preceding flip-flop. Before the data passes through the combinational logic circuit, the subsequent flip-flop performs a latch operation, causing a malfunction.

In designing a clock supply system, in order to suppress the occurrence of undesired clock skew, the types of clock buffer cells and the number of cell stages arranged in the same system clock supply system are unified, and the length of clock wiring is reduced. With respect to the above, a method can be adopted in which a short wiring length is adjusted to a long wiring length, and a dummy delay gate is inserted into a clock wiring.

As an example of a document describing the clock supply method, see Nikkei BP (April 19, 1996).
"Computer Configuration and Design [1]", pp. 692-6
There are 96 pages.

[0005]

However, the method of matching a large propagation delay time with a small propagation delay time in a clock supply system or inserting a dummy delay gate increases the overall driving load of the clock buffer. This leads to an increase in power consumption.

Also, for a clock supply system with strict timing constraints and a cell forming a critical path,
It has been found by the inventor that it is difficult to adopt the above method. In that case, the arrangement and wiring of the cells must be changed.

Also, regarding the signal path constituting the critical path, if the signal delay on the path exceeds the allowable limit, it is necessary to change the cell arrangement and wiring.

An object of the present invention is to provide a method of designing a semiconductor integrated circuit which can control the delay of a clock signal and a transmission signal with high accuracy for a clock supply and a signal transmission system of the semiconductor integrated circuit. .

Another object of the present invention is to provide a semiconductor integrated circuit and a method of designing a semiconductor integrated circuit which can reduce wasteful power consumed in a clock supply system and a signal transmission system.

Another object of the present invention is to provide a method of designing a semiconductor integrated circuit which can shorten a design period for optimizing clock skew.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a design method focusing on a clock supply system of a semiconductor integrated circuit includes a sequential circuit cell operated synchronously with a clock signal, a combination circuit cell operated by receiving an output of the sequential circuit cell, A placement and routing process for arranging a clock buffer cell for supplying a clock signal to a cell, and connecting the sequential circuit cell, the combinational circuit cell and the clock buffer cell to each other with a signal wiring and a clock wiring; The processing includes analyzing the driving load of each clock buffer cell in the clock signal supply system obtained by the processing, and setting the driving capability of the clock buffer in accordance with the analyzed driving load of the clock buffer.

According to this method, since the driving capability of the clock buffer cell is set according to the driving load of the clock buffer cell grasped by the arrangement and wiring of the clock buffer cell, the skew of the clock signal is controlled with high precision. Can be. At this time, since the rearrangement of the circuit cells is not required, it contributes to shortening of the design period. In addition, since it is not necessary to adjust the clock wiring to the one having the largest load and to dispose the dummy gate, it is possible to contribute to low power consumption.

Each of the clock buffer cells may include a plurality of driver units arranged in parallel. The process of setting the driving capability of the clock buffer cell includes connecting all or a part of the plurality of driver units to a clock wiring in the clock buffer cell according to the driving load of the clock buffer cell. can do. By using such a clock buffer cell, the wiring change portion for setting the driving capability of the clock buffer cell can be limited to a local portion in the clock buffer cell. Becomes extremely simple. Since the clock buffer cell itself is not rearranged in the determination of the driving capability, the driving load of the clock buffer once analyzed is not changed, which also guarantees that the design of the clock system is facilitated.

Further, the processing for setting the driving capability of the clock buffer is performed by selecting from among a plurality of clock buffer cells having the same cell size and terminal position and different driving capabilities according to the driving load of the clock buffer. , And a process of replacing the clock buffer cell by selecting the clock buffer cell.

The above-described design method can be applied to a semiconductor integrated circuit including a plurality of sequential circuits operated synchronously with a clock signal. In the semiconductor integrated circuit, a clock buffer is interposed in a clock wiring for guiding the clock signal to the sequential circuit. And
The clock buffer includes a plurality of driver units arranged in parallel, and all or a part of the plurality of driver units are connected to a clock line according to a load to be driven by the clock buffer. Become. As is clear from the above, this semiconductor integrated circuit achieves low power consumption in the clock supply system. When the driver unit is configured by a CMOS circuit, the power consumption is further reduced by forcing the input terminal of the driver unit, which is not connected to the clock wiring, to the power supply voltage or the ground voltage.

The means relating to the clock supply system can be applied to a signal supply system for connecting a sequential circuit and a combinational circuit.

That is, a design method focusing on a signal transmission system of a semiconductor integrated circuit includes a sequential circuit cell operated synchronously with a clock signal, a combination circuit cell operated by receiving an output of the sequential circuit cell, A clock buffer cell for supplying a clock signal to the cell is arranged, and the arranged circuit cell, combination circuit cell and clock buffer cell to be arranged are connected by a signal wiring and a clock wiring. Placement and wiring processing for arranging driver cells on signal wirings connecting circuit cells, processing for analyzing the driving load of each driver cell in the signal supply system obtained in the placement and wiring processing, and the analyzed driver cells And setting the driving capability of the driver cell according to the driving load of the driver cell.

According to this method, since the driving capability of the driver cell is set in accordance with the driving load of the driver cell grasped by the driver cell layout, the delay of the transmission signal can be reduced without changing the cell layout. It can be controlled with high precision.

[0021]

FIG. 1 is a flowchart showing one example of a method for designing a semiconductor integrated circuit according to the present invention. The flowchart shown in the figure focuses on the clock supply system of the semiconductor integrated circuit. The design method shown in FIG. 1 includes a placement and routing process S1, a clock system evaluation and analysis process S2, and a clock buffer size determination process S
3, and wiring line processing S4 in the clock buffer. Although not specifically shown, the design of the semiconductor integrated circuit is performed using a computer system such as an engineering workstation.

In the placement and routing process S1, for example, assuming a circuit as shown in FIG.
2 and the combination circuit cells 20 to 13 operated in response to the outputs of the sequential circuit cells.
22 and clock buffer cells 30, 31 for supplying clock signals φ1, φ2 to the sequential circuit cells 10, 12, 11, 13; This is a process of connecting the cells 20 to 22 and the clock buffer cells 30 and 31 by wiring. The wiring processing at this time is performed, for example, by determining the signal wirings 40 to 47 of the sequential circuit cells 10 to 13 and the combinational circuit cells 20 to 22, and the clock from the clock buffer cells 30 and 31 to the sequential circuit cells 10 to 13. This is a process for determining the wirings 50 to 53. In FIG. 2, the clock signals φ1 and φ2 are assumed to be non-overlapping two-phase clock signals. The sequential circuit cells 10-1
3 is a D-type flip-flop as an example, where D is a data input terminal, Q is a data output terminal, and C is a clock input terminal. Although the circuit configuration shown in FIG. 2 is extremely simplified, this is for facilitating understanding, and in fact, an enormous amount of logic is configured.

FIG. 3 shows another example of the placement and routing process S1. 3, reference numerals 60 to 67 denote sequential circuit cells, reference numerals 70 to 75 denote clock buffer cells, and reference numerals 80 to 87.
Is a clock wiring. In FIG. 3, the combination circuit cell and the signal wiring are not shown. φ3 is a clock signal.

Evaluation and analysis processing S2 of the clock system
Is a process of analyzing the driving load of the clock buffer on the result of the placement and routing illustrated in FIGS. 2 and 3. For example, according to the example of FIG.
The load of each clock line is analyzed in consideration of the length of the clock lines 80 to 87, the number of sequential circuits connected to the clock lines 80 to 87, and the capacitance component parasitic on the clock lines 80 to 87. In the placement and routing process S1, the same clock line of the same system is made equal length, or if the same length cannot be made, a short wire is combined with a long wire, or a dummy gate constituting a delay component is interposed in the clock wire. No action is taken. Therefore, the clock skew is not controlled at this stage.

The clock skew is controlled by the clock buffer size determination processing S3 and the wiring processing S4 in the clock buffer. Both processes S
Steps S3 and S4 are processing for determining the driving capability of the clock buffer (the transistor size of the clock buffer) according to the analyzed driving load of the clock buffer, as described in detail below.

FIG. 4 shows an example of the clock buffer cells 30, 31, 70 to 75 used in the design method of FIG. In the figure, OUT is an output terminal of the clock buffer cell, and IN is an input terminal of the clock buffer cell.
The clock buffer cell includes a plurality of driver units arranged in parallel, for example, four CMOS inverter units IV1 to IV4. Initially, for the input terminals i1 to i4 and the output terminals o1 to o4 of the respective CMOS inverter units IV1 to IV4, the connection state between the input terminal IN and the output terminal OUT of the clock buffer cell is not determined (determined).

In the clock buffer size determining process S3, four CMOS inverter units IV1 to IV4 are used in accordance with the load to be driven by the clock buffer cell.
Are connected to the input terminal IN and the output terminal OUT. As the number of CMOS inverter units connected to the input terminal IN and the output terminal OUT increases, the transistor size of the circuit constituting the clock buffer increases, and accordingly, the load driving capability of the clock buffer cell increases.

For example, according to the example of FIG. 3, in order to reduce the skew of the clock signal reaching each sequential circuit cell, the clock wiring 81 is longer than the clock wiring 82 for the clock buffers 70 and 71 at the preceding stage. A larger transistor size is set for the clock buffer 70. Post-stage clock buffers 72 to 7
For 5, the larger the driving capability is required in the order of 72, 73, 75, 74, the transistor sizes of the clock buffers 72 to 75 are determined accordingly.

The wiring process S4 in the clock buffer is a process of connecting the CMOS inverter unit to the input terminal IN and the output terminal OUT according to the result of the process S3. The input terminal of the CMOS inverter unit whose connection is not selected is connected to the power supply voltage or the ground voltage, and generation of a through current is prevented.

FIG. 5 shows an example of a device structure of the clock buffer cell. In FIG. 5, MTL1 is a first metal wiring layer, MTL2 is a second mental wiring layer, PS
i is a polysilicon layer, DIF is a diffusion layer, CTH is a contact hole, and TRH is a through hole. Power supply voltage V
The power supply line 90 to which cc is supplied is a p-channel type MOS.
Diffusion layers 92 and 93 constituting the source of the transistor are coupled via contact holes CTH. Ground voltage G
The power supply line 91 to which ND is supplied is an n-channel type MOS
Diffusion layers 94 and 95 constituting the source of the transistor are coupled via contact holes CTH. 96-99
Is a gate electrode common to the p-channel MOS transistor and the n-channel MOS transistor. FIG.
As is clear from the device structure of the clock buffer described above, it is sufficient to connect the input terminal IN and the output terminal OUT to the input terminal and the output terminal of the CMOS inverter unit locally in the area of the clock buffer cell.

According to the above-described design method, the driving capability of the clock buffer cell is determined according to the driving load of the clock buffer cell which is grasped after the clock buffer cell is arranged and wired. Therefore, the skew of the clock signal is controlled with high precision. be able to. In addition, since there is no need to rearrange circuit cells, it contributes to shortening the design period. Further, since it is not necessary to adjust the clock wiring to the one with the largest load and to dispose the dummy gate, it is possible to contribute to low power consumption. In particular, by using a clock buffer cell whose transistor size can be selected as illustrated in FIG.
The wiring change portion for setting the driving capability of the clock buffer cell can be limited to a local portion in the clock buffer cell, and the processing for determining the driving capability of the clock buffer cell can be performed extremely easily. Since the clock buffer cell itself is not rearranged in the determination of the driving capability, the driving load of the clock buffer once analyzed is not changed, which also guarantees that the design of the clock system is facilitated.

The above-described design method can be applied to a semiconductor integrated circuit including a plurality of sequential circuits that are operated in synchronization with a clock signal, and the semiconductor integrated circuit, as apparent from the contents of FIGS. φ1 and φ2 are connected to a sequential circuit (1
Clock buffers (30, 31) are interposed in clock wirings (50-53) leading to 0-13). The clock buffers have a plurality of CMOS inverter units (IV1-IV4) arranged in parallel. All or some of the CMOS inverter units (IV1 to IV4) are connected to the clock wiring according to the driving load of the clock buffer. This semiconductor integrated circuit
As is clear from the above, low power consumption is achieved in the clock supply system.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, when the clock buffer cell is composed of a plurality of CMOS inverter units, the number of CMOS inverter units arranged in parallel is not limited to four, but may be two, eight, or the like. Also,
The type of the clock buffer cell used in the design of the semiconductor integrated circuit is not limited to one type, but may be plural types. That is, clock buffers having different maximum driving capacities can be selected and used. For example, it is also possible to adopt a process in which clock buffers having different maximum driving capacities are assigned according to the number of branches of the output of the clock buffer, and the transistor size of each clock buffer is determined later according to the driving load of the buffer. Alternatively, it is also possible to use clock buffer cells selectively on the upstream side and the downstream side of the clock wiring.

In the above example, the wiring in the clock buffer cell is determined so that the transistor size is selected according to the buffer driving load. However, a plurality of cells having the same cell size and terminal position and different driving capabilities are determined in advance. When determining the driving capability of the clock buffer cell, a plurality of clock buffers having the same cell size and different terminal positions and different driving capabilities depending on the driving load of the clock buffer cell are prepared. An optimal clock buffer cell may be selected from the cells to replace the clock buffer cell.
Also in this case, since the cell arrangement is not changed, the same effect as in the above case can be obtained.

In the above example, the clock supply system is exclusively used as an example. However, the above description can also be applied to delay control of signal transmission on signal wiring connecting the sequential circuit and the combinational circuit. For example, the signal wirings 40 to 40 illustrated in FIG.
A driver cell having the same configuration as that of the circuit illustrated in FIG. In the same manner as described above, the driving capability of the driver cell is determined according to the load to be driven by the driver cell. For example, by taking such measures in the signal transmission path that constitutes the critical path, without rearranging cells and wiring,
The signal transmission delay on the critical path can be within an allowable limit.

[0037]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the driving capability of the clock buffer cell is set in accordance with the load on the clock buffer cell which is grasped by the arrangement and wiring of the clock buffer cell.
The skew of the clock signal can be controlled with high precision. Moreover, since it is not necessary to rearrange the circuit cells, the design period for optimizing the clock skew can be shortened.
Further, since it is not necessary to adjust the clock wiring to the one with the largest load and to dispose the dummy gate, it is possible to contribute to low power consumption.

Further, by adopting a method of determining the transistor size in accordance with the driving load of the clock buffer cell, a wiring change portion for determining the driving capability of the clock buffer cell can be locally changed within the clock buffer cell. The driving capacity of the clock buffer can be easily set.

Further, since the driving capability of the driver cell is determined according to the driving load of the driver cell which is grasped by the arrangement and wiring of the driver cell, it is possible to control the signal delay in a signal transmission system such as a critical path with high precision. it can. At this time, there is no need to rearrange circuit cells.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an example of a method for designing a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram illustrating an example of a circuit configuration obtained by a placement and routing process illustrated in FIG. 1;

FIG. 3 is a block diagram showing another example of a circuit configuration obtained by the placement and routing processing shown in FIG. 1;

FIG. 4 is a logic circuit diagram showing an example of a logic configuration of a clock buffer cell.

FIG. 5 is a plan view showing an example of a device structure of a clock buffer cell.

[Explanation of symbols]

 10-13 Sequential circuit cell 20-22 Combination circuit cell 30, 31 Clock buffer cell 40-47 Signal wiring 50-52 Clock wiring 60-67 Sequential circuit cell 70-75 Clock buffer cell 80-87 Clock wiring OUT Clock buffer cell Output terminal IN Input terminal of clock buffer cell IV1 to IV4 CMOS inverter unit o1 to o4 Output terminal of CMOS inverter unit i1 to i4 Input terminal of CMOS inverter unit φ1, φ2, φ3 Clock signal

Claims (7)

[Claims] 1. A sequential circuit cell operated synchronously with a clock signal, a combinational circuit cell operated in response to an output of the sequential circuit cell, and a clock buffer cell for supplying a clock signal to the sequential circuit cell. Placement and wiring processing for arranging and connecting the sequential circuit cells, combinational circuit cells, and clock buffer cells with signal wiring and clock wiring, and respective clock buffers in a clock supply system obtained by the placement and wiring processing A method for designing a semiconductor integrated circuit, comprising: a process of analyzing a load to be driven by a cell; and a process of setting a driving capability of the clock buffer cell according to the analyzed driving load of the clock buffer cell. 2. Each of the clock buffer cells has a plurality of driver units arranged in parallel, and the processing for setting the driving capability of the clock buffer cells is performed in accordance with the driving load of the clock buffer cells. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein the whole or a part of the driver unit is connected to a clock wiring in the clock buffer cell. 3. The process of setting the driving capability of the clock buffer cell includes the step of setting a driving capacity of a plurality of clock buffer cells having the same cell size and terminal position and different driving capabilities according to the driving load of the clock buffer cell. 2. The method for designing a semiconductor integrated circuit according to claim 1, further comprising the step of selecting another clock buffer cell from the list and replacing the clock buffer cell. 4. A semiconductor integrated circuit including a plurality of sequential circuits operated in synchronization with a clock signal, wherein a clock buffer is interposed in a clock line for guiding the clock signal to the sequential circuit, and the clock buffers are arranged in parallel. A plurality of driver units, and all or some of the plurality of driver units are connected to a clock wiring according to a load to be driven by the clock buffer. Semiconductor integrated circuit. 5. The driver unit according to claim 1, wherein the driver unit is a CMOS circuit, and an input terminal of the driver unit which is not connected to a clock wiring is connected to a power supply voltage or a ground voltage. 5. The semiconductor integrated circuit according to item 4. 6. A sequential circuit cell operated in synchronization with a clock signal, a combinational circuit cell operated in response to an output of the sequential circuit cell, and a clock buffer cell for supplying a clock signal to the sequential circuit cell. And arranging the sequential circuit cells, the combination circuit cells, and the clock buffer cells by a signal line and a clock line, and arranging a driver cell on a signal line connecting the combination circuit cell and the sequence circuit cell. Processing to analyze the load to be driven by each driver cell in the signal supply system obtained by the above-described layout and wiring processing; and the driving capability of the driver cell according to the analyzed driving load of the driver cell. And a process for setting a semiconductor integrated circuit. 7. Each of the driver cells has a plurality of driver units arranged in parallel, and the processing for setting the driving capability of the driver cells is performed in accordance with the driving load of the driver cells. 7. The method for designing a semiconductor integrated circuit according to claim 6, wherein the process is a process of connecting all or a part of the above to the signal wiring in the driver cell.