JP3437748B2 - Clock supply circuit and enable buffer cell - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply circuit having a multistage buffering structure formed on a semiconductor chip and designed by a gated clock designing method for supplying a clock to elements such as registers. And an enable buffer cell for controlling on / off of the propagation of the clock signal.

[0002]

2. Description of the Related Art Recently, the frequency of a clock supplied to an LSI circuit or the like has been dramatically improved, but with this increase in power consumption of the circuit has become a serious problem. Specifically, there is a problem in that heat is generated by exceeding the heat radiation limit of the package of the LSI circuit due to the increase in power consumption, and the battery life in the battery drive system is significantly shortened.

When the power consumption source in the LSI chip is divided into parts such as a data transfer system, a clock system, an input / output interface system, and a functional module, the most power consuming part is usually It is a clock system. Therefore, in order to reduce the power consumption of the LSI chip, it is most effective to reduce the power consumption of the clock system.

As a most effective method for reducing the power consumption of the clock system, a design method called a gated clock has been known in the past. In this method, it is possible to design a clock supply circuit capable of controlling the propagation of a clock so as to supply the clock signal to the corresponding register only at the timing when the data transfer is really necessary in the register-to-register transfer.

FIG. 9 is a circuit diagram showing an example of a conventional clock supply circuit designed by this gated clock design method. An enable buffer cell 2 is inserted between the root driver cell 1 and a register (flip-flop) 3 to form a tree, and each enable buffer cell 2 is turned off by enable signals E1 to E3. . In addition, in this example, the register 3 is directly connected to the root driver cell 1 and also has a tree in which a clock is always supplied.

In the clock supply circuit designed by the above-mentioned gated clock design method, in general, the register 3
As the clock signal to be supplied, control signals E1 to E3 called enable signals and the original clock signal CLK are used.
A signal obtained by taking a logical product (AND) or a logical sum (OR) with is used, and in the example of FIG. 9, the enable buffer cell 2 of the logical product type is used.

Therefore, for example, only when the enable signal E1 is "1", the clock signal output from the root driver cell 1 passes through the enable buffer cells 2 in the first row and is connected to the final stage of this subtree. Is supplied to the registered register 3. However, in this example, the clock signal input to the route driver cell 1 is referred to as a clock signal CLK, and the clock signal that passes through the buffer cells and the like thereafter and enters the register 3 is simply referred to as a clock signal.

FIG. 10 is a circuit diagram for explaining the operation of the AND-type enable buffer cell 2 described above. The clock signal is input to one terminal of the enable buffer cell 2, the enable signal EN is input to the other terminal, and the output signal is supplied to the group of registers 3. The output of the buffer cell 2 is the enable signal E.
When N is "1", it is turned on and the waveform of the clock signal is propagated to the output side. Conversely, when it is "0", it is cut off and the clock signal is not propagated to the output side. The propagation of the clock signal can be controlled by the signal value of the enable signal EN. The same thing can be done by using an OR-type enable buffer cell, in which case the waveform of the clock signal propagates only when the enable signal is "0".

As described above, if the combinational circuit for generating the enable signal EN and the buffer cell for taking the logical product (or logical sum) of the enable signal and the clock signal are inserted in advance in the tree forming the clock supply circuit. The frequency of clock signal propagation can be minimized, and as a result, power consumption can be reduced.

A problem that arises when adopting such a gated clock designing method is that "even if there are many enable signals of different types in the same clock system, a clock clock is guaranteed so as to guarantee a desired operating frequency. Is it possible to make the queue smaller? "

Normally, it is realized by forming a subtree having a minimum clock skew separately for each buffer cell controlled by each enable signal. In this case, how to align the delays between these subtrees. Is a problem.

As an orthodox method, first, the circuit shown in FIG. 9 is constructed. Usually, since the driving force is insufficient in this circuit, the buffer cell 4 is inserted to modify the tree structure as shown in FIG. First, a tree having the minimum delay is generated in advance for each subtree, and the subtree Tm having the maximum delay is found from the tree. In the example of FIG. 11, it is assumed that the subtree including the enable buffer cell 2 controlled by the enable signal E1 is the maximum delay subtree Tm.

When the maximum delay subtree Tm is known, next, as shown in FIG. 12, the subtrees other than the maximum delay subtree Tm have the same delay as the subtree Tm in the first row. For example, a relay buffer cell 4 may be inserted in multiple stages after the buffer cell 4 controlled by the enable signals E2 and E3, or a buffer cell 4a having a large driving force such as the subtree of the fourth row may be inserted. Then, modify the tree structure to increase the delay to minimize clock skew.

At this time, as a method of increasing the delay, in addition to the method of inserting the relay buffer cells 4 in multiple stages as described above, the driving force of the buffer may be decreased. In the subtree of the fourth row, the delay is increased by inserting the three buffer cells 4a and 4 in series. However, this delay increases too much, so that the driving force is the same as that of the buffer cell 4a. By using a buffer cell having a large size, the delay that has increased too much is reduced to obtain the same delay as the subtree in the first row.

However, the driving force of the buffer cell can be changed only discretely, and the buffer cell for relay 4
Since the number of insertion stages can be changed only one by one, the amount of delay increase is discrete, and it is difficult to finely adjust the delay for each subtree. Therefore, as shown in FIG. 12, the greater the number of enable signal sequences, the more difficult it is to adjust the delay between subtrees, resulting in much time and labor for trial and error due to manual design. As described above, the conventional gated clock system always has problems of complexity of design and extension of design period.

[0016]

Conventionally, in order to reduce the power consumption of the entire chip such as an LSI, a circuit for controlling the supply of the clock signal to the register 3 only at the timing necessary for the inter-register transfer of the clock signal, It is designed by the gated clock design method. In the clock supply circuit designed by this gated clock designing method, the clock signal is supplied to the register 3 through the buffer cell 2 which is cut off by the enable signal. However, the difficulty in such a design is how to reduce the skew of the clock signal which reaches the register 3 through each buffer cell when there are a large number of AND (enumeration) type enable buffer cells 2 controlled by different enable signals. The point is whether to guarantee the desired operating frequency. As a normal process for this, in order to make the delays as uniform as possible, a process of additionally inserting the relay buffer cell 4 or a logical product (logical sum) is performed according to the downstream load capacity for each buffer cell. ) Type enable buffer cells are changed, but as the series of enable signals increases, it becomes more difficult to adjust the delay between the subtrees, and the CAD part in the above design is a part. There is a problem that it takes a lot of time and effort for trial and error by manual design.

Further, when the AND-type enable buffer cells and the OR-type enable buffer cells are mixed in the same clock system to perform gate control, the delay characteristics of both buffers are not uniform and the clock skew becomes large. there were.

The present invention has been made to solve the above-mentioned conventional problems, and minimizes clock skew,
A first object of the present invention is to provide a clock supply circuit configured to easily and quickly design a gated clock that satisfies the characteristic of suppressing an increase in signal delay of an enable signal. A second object of the present invention is to provide an enable buffer cell in which the mold delay characteristics can be made substantially the same.

[0019]

According to the first aspect of the invention, the route of the clock signal input from the root driver cell is branched into a plurality of paths, and the route is maximized via the enable buffer cell to which the enable signal is applied or the enable buffer cell to which the fixed signal is applied. It is supplied to a clocked element such as a register or a flip-flop on the downstream side. At this time, when the enable buffer cell is a logical product type, when the enable signal is "1", the enable buffer cell is rendered conductive and the clock signal is supplied to the clocked element. On the other hand, the enable buffer cell to which the fixed signal is applied is always conductive and relays the clock to supply the clocked element. Therefore, when the enable signal is set to "1" at the timing of operating the clocked element connected to the subsequent stage of the enable buffer cell, the clock signal is supplied to the clocked element. At this time, the next stage of the upstream route driver cell is either an enable buffer cell to which an enable signal is given or an enable buffer cell to which a fixed signal is given, and the clocked element is connected to the next stage of these enable buffer cells. Therefore, the number of buffer stages is one, and since this one stage has only the same type of enable buffer cells, the clock signal is connected to the most downstream, with almost no signal delay deviation due to different buffer types. The clocked element being clocked.

[0021]

In order to achieve the above object, a feature of the invention of claim 1 is to transmit a clock signal to the downstream side of a route driver cell for inputting a clock signal by interrupting conduction by an enable signal. , A clock supply circuit having a multi-stage buffering tree structure for supplying a clock signal to at least one or more clocked elements located on the most downstream side by providing an enable buffer cell for non-transmission. As a buffer for simply relaying a signal, at least one or more of the enable buffer cells are provided in the tree structure so that a fixed signal is constantly applied to keep the clock signal conductive, and each buffer on the downstream side of the root driver cell is provided. The buffer cells for each stage are the same type of enable buffer. Aseru is to only to.

According to the first aspect of the present invention, the route of the clock signal input from the route driver cell is branched into a plurality of routes, and the clock signal branched into each route is provided by an enable buffer cell to which an enable signal is given or a fixed signal. It passes through the enabled buffer cell and is supplied to the clocked element such as the most downstream register or flip-flop. At this time, when the enable buffer cell is a logical product type, when the enable signal is "1", the enable buffer cell is rendered conductive and the clock signal passes from upstream to downstream. On the other hand, the enable buffer cell to which the fixed signal is applied always conducts and operates as a mere relay buffer. Therefore, when the enable signal is set to "1" at the timing of operating the clocked element connected to the most downstream side of the enable buffer cell, the clock signal is supplied to the clocked element. In addition, since the buffer cells inserted between the upstream route driver cell and the most downstream clocked element are only the same type of enable buffer cells for each buffer stage, the buffer type may differ. The clock signal of each branch path reaches the clocked element connected to the most downstream with almost no deviation of the signal delay.

A feature of the second invention is that a fixed signal is given to all the enable buffer cells located on the downstream side of the enable buffer cell for giving the enable signal.

According to the second aspect of the invention, since there is no enable buffer cell for providing the enable signal downstream of the enable buffer cell for providing the enable signal, the number of enable buffer cells for providing the enable signal is reduced. At the same time, the wiring length of the enable signal is shortened.

The feature of the third invention is that the enable buffer cell is not inserted in the middle of reaching the root driver cell by tracing the upstream side of the enable buffer cell which gives the enable signal, or when the enable buffer cell is inserted, the enable buffer cell is enabled. A fixed signal is given to the buffer cell.

According to the third aspect of the invention, since there is no enable buffer cell for providing the enable signal upstream of the enable buffer cell for providing the enable signal, the number of enable buffer cells for providing the enable signal is reduced. At the same time, the wiring length of the enable signal is shortened.

The feature of the fourth invention is that, as seen from the driving cell P in the preceding stage which supplies a clock signal to a certain enable buffer cell A, at least one of the buffer cells in the succeeding stage which is directly driven by this driving cell P. An enable signal different from the enable signal given to the enable buffer cell A or a fixed value signal is given to one enable buffer cell B.

According to the fourth aspect of the present invention, one preceding buffer cell does not drive only a plurality of enable buffers that are turned off by one type of enable signal. This eliminates redundant enable signal connections and optimizes the number of enable buffer cells.
The wiring length of the enable signal becomes the shortest.

A fifth aspect of the present invention is characterized in that an enable buffer cell for transmitting and non-transmitting a clock signal is provided on the downstream side of a route driver cell for inputting a clock signal to cut off conduction by an enable signal, thereby providing a clock signal. In a clock supply circuit having a multi-stage buffering tree structure for supplying at least one clocked element located at the most downstream when required, an enable signal is given to a stage immediately before all clocked elements. Buffer cells are inserted, and a fixed signal is applied to a part of these enable buffer cells instead of the enable signal, and each clocked device is directly driven by these enable buffer cells.

According to the fifth aspect of the present invention, all the clocked elements in the lowermost stage are provided with an enable buffer cell to which a fixed signal is applied and a remaining enable buffer cell to which an enable signal is applied. Since it is configured, the types and the number of stages of the buffer cells forming each stage are easily unified, and the delays of the branch paths are easily aligned.

[0031]

[0032]

[0033]

[0034]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a clock supply circuit of the present invention. The root driver cell 1 is located at the upstream of the clock supply tree structure, amplifies the input clock signal CLK, and enables the enable signal E1 and the fixed signal VDD which are located at the subsequent stage.
Is output to two AND-type enable buffer cells 2 to which is applied. A plurality of enable buffer cells 2 are connected to the downstream side of these two enable buffer cells 2. An enable signal of any one of E1, E2, and E3 is input to one terminal of the logical product type enable buffer cell 2, and when the enable signal is "1", it conducts and amplifies the clock signal input from the previous stage. And output to the latter stage. On the other hand, of the AND type enable buffer cells 2, the one to which the fixed signal VDD (“1”) is input to one terminal is always conductive, the input clock signal is amplified and output to the subsequent stage. Operates as a mere relay buffer.

Registers (flip-flops) 3 located on the most downstream side are connected to the succeeding stages of the enable buffer cells 2 corresponding to the leaves of the clock supply tree structure, and finally the enable buffer cells immediately before the clock signal is supplied to these registers 3. Supplied from 2.

Next, a method of constructing a clock supply tree that constitutes the above-described clock supply circuit of the present embodiment will be described. When constructing a clock supply circuit having a multi-stage buffering tree structure, the simplest method for avoiding the problems of the prior art is as shown in FIG. It suffices to use the enable buffer cells 2 to which the enable signal E1 is applied to the buffer cells and to directly drive the enable buffer cells 2 by the root driver cell 1.

When the tree is constructed in this way, buffers of the same type can be arranged in the same row of the tree structure, delays up to the registers 3 can be easily aligned, and clock skew can be minimized.

FIG. 3 shows that when the driving force of the route driver cell 1 shown in FIG.
The buffer cell 4 is inserted between the enable buffer cell 2 and the enable buffer cell 2. Also in this case, buffers of the same type can be arranged in the same row of the tree structure, delays up to the registers 3 can be easily aligned, and clock skew can be minimized. However, the buffer cell 4 is a buffer cell that only has an amplifying function, and performs the relay operation of the clock signal.

However, from the viewpoint of low power consumption,
It is better to arrange the enable buffer cell 2 receiving the control of the enable signal on the upstream side as much as possible so as to reduce the power consumption inside the buffer cell in the middle stage and the charge / discharge power of the wiring driven by the buffer cell. By doing so, it is possible to reduce the number of enable buffer cells 2 that receive the same enable signal, suppress the wiring length of the enable signal and shorten the delay of the enable signal.

Nevertheless, in the tree structure shown in FIG. 2 or 3, since the register 3 is directly driven by the lowest enable buffer cell 2, the number of enable buffer cells 2 used becomes large. As a result, the power consumption increases, the wiring length of the enable signal becomes long, and the delay of the enable signal becomes large.

Therefore, in order to realize a multi-stage buffering tree which avoids the problem of the tree structure of FIG. 3, the tree is first constructed by using the enable buffer cell 2 to which a fixed signal is given as the buffer cell 4. It is required to make the delay cells uniform by using the same type of buffer cell constituting each buffer stage. To this end, an enable buffer cell 2 with an enable terminal is always inserted at each stage, and when it is desired to operate as a simple buffer cell, a fixed signal VDD having a logical value 1 (or 0) is supplied as an enable signal. The buffer used in the tree may be the enable buffer cell 2 only.

That is, a plurality of buffer cells of one or more stages are inserted between the root driver cell 1 for supplying the clock signal CLK and the most downstream register 3 for supplying the clock signal in a tree structure. The enable buffer cell 2 having the enable terminals attached to all the buffer cells may be used.

Next, conditions and effects to be satisfied by the multistage buffering tree for avoiding the problem of the tree structure shown in FIG. 3 will be considered in advance.

(1) The buffer cell to which the enable signal is applied and the buffer cell for relay are made the same type of buffer cell so that the delay characteristics of both are made uniform and the clock skew is finally minimized.

(2) By minimizing the number of buffer cells to which the enable signal is connected, the wiring length for transmitting the enable signal is shortened as much as possible, the delay of the enable signal is reduced, and the reduction rate of power consumption is increased. .

In the above (1), there is an advantage that the degree of freedom of buffer insertion is improved when constructing a multi-stage buffering tree, which makes it very easy to handle as CAD processing.

By the way, assuming that a tree having a multistage buffering structure that satisfies the condition (2) is constructed,
It must meet the following properties: That is, in order to minimize the number of the enable buffer cells 2 used, (a) the enable signal is not given to the enable buffer cells 2 on the downstream side of the enable buffer cells 2 to which the enable signal is given, that is, the fixed signal is given to the enable terminal. To give to. (B) If the enable buffer cell 2 is not inserted or the enable buffer cell 2 is inserted on the way from the enable buffer cell 2 which provides the enable signal to the upstream side to reach the route driver cell 1, Apply a fixed signal to the enable terminal.

Further, as a condition for minimizing the power consumption,
(C) Regarding the enable buffer cell 2, "at least one of the buffer cells in the other subsequent stage which the drive cell P directly drives when viewed from the previous drive cell P which supplies the clock signal to the relevant buffer cell 2A" In the cell 2B, a signal Eb (this may be a fixed value signal) different from the enable signal Ea given to the enable terminal of the buffer cell 2A is given to the enable terminal of the buffer cell 2B. To do.

Among the above, the conditions (a) and (b) are necessary conditions for correct clock gating. The condition (c) is a condition for minimizing power consumption, and one pre-driving cell does not drive only a plurality of buffer cells to which one type of enable signal is applied. In other words, this is to prevent redundant enable signals from being distributed.

Next, a specific procedure for constructing a clock supply tree that realizes the above conditions and effects will be described. First, in step l, the group of registers 3 which is controlled by the same enable signal to control the clock supply from the state of the tree structure shown in FIG. 3 is divided into a plurality of subgroups (indicated by solid lines) as shown in FIG. This division is performed so that the sum of the wiring capacitance and the terminal capacitance due to the connection wiring in each subgroup becomes substantially equal (in other words, the clock skew becomes small). Then, this division operation is performed for each of the enable signals E1, E2, E3, one enable buffer cell 2 is inserted for each sub group, and the register 3 in the sub group is inserted by the inserted buffer cell. To drive.

Next, in step 2, the above step 1
In consideration of the division operation, the tree having a multistage buffering structure is constructed in which the enable buffer cell 2 is a leaf node and the root driver cell 1 is a root node as shown in FIG. At that time, branches (edges) on the tree are set up for buffer cells controlled by the same enable signal so that the path on the tree connecting them becomes short. Specifically, the buffer cells under the control of the same enable signal are preferentially tree-merged.

After that, in step 3, when the load capacity driven by the root driver cell 1 is too large and the driving force is insufficient, as shown by p and q in FIG. 6, the enable buffer cell 2 for relay is further added. Is inserted in multiple stages to correct the tree structure shown in FIG.

Finally, in step 4, with respect to the buffer cells 2 inserted on the tree of these multistage buffering structures, a vertical tree search is performed from the root driver cell 1 side to the downstream side, and an enable that appears in the middle is performed. Regarding the buffer cell 2, if all the registers 3 existing on the downstream side of the buffer cell are controlled by the same enable signal, the enable signal of the buffer cell 2 is given to the enable terminal of the buffer cell 2. A fixed signal VDD having a logical value of 1 (or 0) is given to the enable terminals of all the buffer cells located downstream of 2 so that the input signal is propagated to the output side as it is. A tree structure as shown in FIG. 1 is constructed from the configuration of FIG.

If the driving force of the root driver cell 1 shown in FIG. 1 is insufficient, at least one enable buffer cell 2 to which a fixed signal VDD as shown by a broken line is applied is inserted at the subsequent stage of the root driver cell 1. Will be done.

Here, in the enable buffer cell 2 described above, a concrete method is to give a fixed signal having a logical value of 1 (or 0) so that the input signal is propagated to the output as it is for a simple relay buffer cell state. There are several possibilities. One of them is a method in which a signal of a power supply potential or a ground potential is set as a connection net and is connected to a common wiring as the same net. The other is a method in which a terminal having a power supply potential or a ground potential is prepared in advance in the enable buffer cell 2 and the terminal and the enable terminal of the buffer cell are short-circuited inside the cell. . As for the area of the buffer cell, the former can be made smaller, but the wiring length of the fixed signal line can be made shorter in the latter. Therefore, which one to choose depends on their area penalties.

According to the present embodiment shown in FIG. 1, all the buffer cells to which the enable signal is to be supplied and the relay buffer cells which do not need to be supplied with the enable signal are the same kind of cells as the enable buffer cell 2. Therefore, the delay characteristics of each line are uniform, and the clock skew can be finally minimized. In addition, a fixed signal V is applied to the enable buffer cell 2 on the downstream side of the enable buffer cell 2 which provides the enable signal E1.
The fixed signal VDD is also given to the enable buffer cell 2 which is in the middle of reaching the route driver cell 1 by tracing the upstream side from the buffer cell 2 which gives the DD and further the enable signal E1 and is driven by the route driver cell 1. The buffer cells are the enable buffer cells 2 to which the enable signal E1 is applied and the enable buffer cells to which the fixed signal VDD is applied, and one preceding drive cell does not drive only a plurality of buffer cells to which one type of enable signal is applied. Since the condition is satisfied, it is possible to minimize the number of use of the enable buffer cells 2 that input the enable signal and also to minimize power consumption. Further, since the number of enable buffer cells 2 for inputting the enable signal is minimized, the wiring length for transmitting the enable signal can be minimized and the delay of the enable signal can be minimized.

Therefore, in the gated clock designing method, the degree of freedom in position selection when inserting the buffer cell 2 which provides the enable signal on the clock tree is improved, thereby improving the performance and minimizing the clock delay and skew. Since the method can be simplified, the design method can be easily CAD, and the clock supply circuit by the gated clock design method can be easily constructed in a short time. Further, as described above, the wiring length of the enable signal can be minimized, and a layout in which the timing constraint for the enable signal can be easily observed can be realized.

The enable buffer cell 2 has a logical product type and a logical sum type, but it is convenient for the LSI system design that their delay characteristics are substantially the same.
However, it is difficult to match the delay characteristics of both with a conventional configuration in which a cell such as a NAND or N0R and an inverter having a high driving force are connected in series. Because P-type MOS
The on-resistance per gate width is different between the transistor and the N-type MOS transistor, and further, one has a parallel connection and the other has a serial connection. Therefore, it is difficult to arrange the delay characteristics particularly when a NOR cell is used. was there.

FIG. 7 is a circuit diagram showing the first embodiment of the enable buffer cell of the present invention. The inverter 8a, the transmission gate 9, and the inverter buffer 11 are connected in series. Inverter buffer 1
P channel MOS transistor 10 on the input side of 1
The drain of p is connected to this MOS transistor 10
VDD is applied to the source of p. The enable signal E is input to the gate of the MOS transistor 10p, and the enable signal E is directly input to the control terminal of the transmission gate 9 and the inverter 8
It is input to the inversion control terminal of the transmission gate 9 via b.

Next, the operation of this embodiment will be described. The clock signal CLK is input from the inverter 8a, and the enable signal E is input to the control terminal of the transmission gate 9 and the gate of the MOS transistor 10p. At the same time, the enable signal E changes to the inverter 8b.
The polarity is inverted by and input to the inversion control terminal of the transmission gate 9. When the enable signal E is "1", the transmission gate 9 is turned on, the MOS transistor 10p is turned off, and the input clock signal CLK is output through the inverter 8a, the transmission gate 9, and the inverter buffer 11.

On the contrary, when the enable signal E1 is "0",
Since the transmission gate 9 is cut off and the MOS transistor 10p is turned on, the inverter buffer 11
Fixed value VDD is applied to the input of, and its output is "0"
Becomes

According to the present embodiment, the transmission gate 9 is provided immediately after the first-stage inverter 8a inside the two-stage (generally even-numbered) inverter chain.
A logical product type enable buffer cell can be configured by inserting a selector circuit using P and a P channel MOS transistor 10p.

FIG. 8 is a circuit diagram showing a second embodiment of the enable buffer cell of the present invention. The inverter 8a, the transmission gate 9, and the inverter buffer 11 are connected in series. Inverter buffer 1
N channel MOS transistor 10 on the input side of 1
n source is connected to this MOS transistor 10n
The drain of is grounded. The enable signal E is input to the gate of the MOS transistor 10n, and the enable signal E is input to the control terminal of the transmission gate 9 via the inverter 8b and directly to the inversion control terminal of the transmission gate 9. .

Next, the operation of this embodiment will be described. The clock signal CLK is input from the inverter 8a, and the enable signal E is input to the inversion control terminal of the transmission gate 9 and the gate of the MOS transistor 10n. At the same time, the polarity of the enable signal E is inverted by the inverter 8b and input to the control terminal of the transmission gate 9. When the enable signal E is "0", the transmission gate 9 is turned on, the MOS transistor 10n is turned off, and the input clock signal CLK is output through the inverter 8a, the transmission gate 9, and the inverter buffer 11.

On the contrary, when the enable signal E is "1", the transmission gate 9 is cut off and the MOS transistor 10n is turned on, so that the input of the inverter buffer 11 becomes the ground level and the output thereof becomes "1". .

According to the present embodiment, the transmission gate 9 is provided immediately after the first-stage inverter 8a inside the two-stage (generally even-numbered) inverter chain.
An OR-type enable buffer cell can be formed by inserting a selector circuit using the N-channel MOS transistor and the N-channel MOS transistor 10n.

Here, the logical product type enable buffer cell and the logical sum type enable buffer cell shown in FIGS. 7 and 8 differ only in the polarity of the MOS transistor 10 connected to the input side of the inverter buffer 11. Since the structures are similar, both can have almost the same delay characteristics. As a result, the system design can be facilitated when the clock supply circuit of the first embodiment shown in FIG. 1 is implemented as an LSI.

[0068]

As described in detail above, according to the first aspect of the present invention, since the buffer cells of the same type are provided between the root driver cell and the clocked element, the clock skew can be minimized.

According to the second invention, since the downstream side of the root driver cell is the same type of buffer cell for each buffer stage, the clock skew can be minimized. According to the third invention, since the fixed signal is given to all the enable buffer cells on the downstream side of the enable buffer cells to which the enable signal is given, the number of enable buffer cells giving the enable signal is minimized. The power consumption can be minimized and the delay of the enable signal can be suppressed.

According to the fourth invention, the enable buffer cell is not present between the upstream side of the enable buffer cell to which the enable signal is given and the root driver cell, or the enable buffer cell is present even if the enable buffer cell is present. Since a fixed signal is applied to the memory cell, it is possible to minimize the number of enable buffer cells that provide the enable signal to minimize power consumption and suppress the delay of the enable signal.

According to the fifth aspect of the invention, since the drive cells in the preceding stage do not drive only the plurality of enable buffer cells to which one type of enable signal is applied, the power consumption can be minimized.

According to the sixth invention, the number of stages of a plurality of subtrees can be easily adjusted, so that the clock skew can be reduced.

According to the seventh and eighth aspects of the invention, since the structures of the AND buffer type and the OR gate type enable buffer cells can be made similar to each other, the delay characteristics of both types can be easily aligned. Design of a clock supply circuit by a gated clock design method having a multi-stage buffering tree structure using a type enable buffer cell can be extremely facilitated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a clock supply circuit of the present invention.

FIG. 2 is a circuit diagram showing an example of a first stage clock supply circuit for constructing the clock supply circuit shown in FIG.

FIG. 3 is a circuit diagram showing an example of a second stage clock supply circuit for constructing the clock supply circuit shown in FIG.

FIG. 4 is a diagram showing an example of division when dividing the register group shown in FIG. 2 into a plurality of subgroups.

5 is a circuit diagram showing an example of a third stage clock supply circuit for constructing the clock supply circuit shown in FIG.

6 is a circuit diagram showing an example of a fourth stage clock supply circuit for constructing the clock supply circuit shown in FIG. 1;

FIG. 7 is a circuit diagram showing a first embodiment of an enable buffer cell of the present invention.

FIG. 8 is a circuit diagram showing a second embodiment of an enable buffer cell of the present invention.

FIG. 9 is a circuit diagram showing an example of a conventional clock supply circuit designed by the gated clock method.

FIG. 10 is a circuit diagram illustrating an operation of the enable buffer cell shown in FIG.

11 is a circuit diagram in which a buffer cell is inserted in the clock supply circuit shown in FIG. 9 to preliminarily generate a tree having a minimum clock propagation delay.

12 is a circuit diagram showing an example of a conventional clock supply circuit reconfigured so that clock propagation delays of respective lines of the clock supply circuit shown in FIG. 11 are aligned.

[Explanation of symbols]

1 root driver cell 2 Enable buffer cell 3 registers 4 buffer cells 8a, 8b inverter 9 Transmission gate 10p, 10n MOS transistor 11 Inverter buffer

Claims (5)

(57) [Claims] 1. A downstream side of a route driver cell for inputting a clock signal is provided with an enable buffer cell for conducting and non-transmitting a clock signal by interrupting conduction by an enable signal so that the clock signal is at the most downstream side when needed. In a clock supply circuit having a multistage buffering tree structure for supplying to at least one or more clocked elements located at, a state in which a fixed signal is applied to always make the clock signal conductive as a buffer for simply relaying the clock signal. In the clock structure, at least one or more enable buffer cells are provided in the tree structure, and the buffer cells for each buffer stage on the downstream side of the root driver cell are only enable buffer cells of the same type. Supply circuit. 2. The clock supply circuit according to claim 1, wherein a fixed signal is applied to all the enable buffer cells located on the downstream side of the enable buffer cell for applying the enable signal. 3. An enable buffer cell is not inserted in the middle of reaching the root driver cell by tracing the upstream side of the enable buffer cell which gives the enable signal, or when the enable buffer cell is inserted, a fixed signal is inserted in the enable buffer cell. The clock supply circuit according to claim 1 or 2, wherein 4. The enable buffer cell B of at least one of the other subsequent buffer cells directly driven by the drive cell P when viewed from the previous drive cell P supplying a clock signal to a certain enable buffer cell A.
4. The clock supply circuit according to claim 1, wherein an enable signal or a fixed value signal different from the enable signal applied to the enable buffer cell A is applied to the clock supply circuit. . 5. An enable buffer cell for conducting and non-transmitting a clock signal is provided on the downstream side of a route driver cell for inputting the clock signal, the conduction buffer being cut off by the enable signal, so that the clock signal can be transmitted when necessary. In a clock supply circuit having a multi-stage buffering tree structure for supplying at least one clocked element located downstream, an enable buffer cell to which an enable signal is applied is inserted in a stage immediately before all clocked elements. A clock supply circuit characterized in that a fixed signal is applied to a part of these enable buffer cells instead of the enable signal, and each clocked element is directly driven by these enable buffer cells.