JP2005251862A - Semiconductor integrated circuit and method of designing its layout - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, in an MTCMOS-applied block, a useless area which is not usable for a logic circuit nor power supply control tends to occur. <P>SOLUTION: A semiconductor integrated circuit has a cell arranging structure in which a plurality of gate array regions GA is dispersedly arranged in a standard cell region SC. The logic circuit is formed of standard cells constituting the standard cell region SC, and the switching transistor of an MTCMOS which controls the power supply and leak route interruption of an adjacent logic circuit is formed of the basic cells of gate arrays constituting each gate array region GA. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a logic circuit connected between a virtual power supply voltage supply line and a virtual reference voltage supply line, such as a so-called multi-threshold CMOS (MTCMOS) integrated circuit, a virtual power supply voltage supply line, and a power supply. A semiconductor integrated circuit having a switch transistor connected between a voltage supply line or between a virtual reference voltage supply line and a reference voltage supply line and turned on when a logic circuit is operated and turned off when the logic circuit is not operated, and layout design thereof Is.

With the recent high integration and miniaturization of CMOS integrated circuits, the power supply voltage has been lowered. Lowering the power supply voltage is necessary from the viewpoints of both ensuring reliability associated with miniaturization and reducing power consumption. However, if the power supply voltage is lowered, the operating speed of the MOS transistor is reduced, so that the operating speed is reduced. It is necessary to lower the threshold voltage of the CMOS transistor from the viewpoint of improvement and securing of circuit operation margin. For example, in an LSI having a minimum dimension of 100 nm or less as in recent years, the power supply voltage Vdd needs to be lowered to about 1.0 V, and in that case, the threshold voltage of the transistor needs to be lowered to about 0.3 V.
However, as is well known, an increase in leakage current in the subthreshold region becomes a problem as the threshold voltage decreases, and how to reduce this leakage current is a major issue.

In order to solve these problems, MTCMOS (Multi-threshold Complementary Metal Oxide Semiconductor) can be used as a device in addition to the approach from the process such as improving the leakage characteristics or reducing the parasitic capacitance to increase the operation speed. ) Has been proposed.
In a logic LSI composed of MTCMOS, a logic circuit connected between a virtual power supply voltage supply line (hereinafter referred to as “V-Vdd line”) and a virtual reference voltage supply line (hereinafter referred to as “V-Vss line”). Connected between the block and the V-Vdd line and the power supply voltage supply line (Vdd line) or between the V-Vss line and the reference voltage supply line (Vss line). And a switch transistor which is sometimes turned off. The switch transistor has a higher threshold voltage than the logic transistor of the logic circuit, and is a kind of power transistor.

Since the switch transistor is provided to turn off when the logic circuit block is not operating and cut off the leak current path, the threshold voltage is sufficiently high in that sense. However, if the threshold voltage is too high, the internal power supply voltage cannot be sufficiently turned on, and sufficient voltage is not supplied to the V-Vdd line or V-Vss line, resulting in an unstable voltage value. .
In order to cope with this problem, a latch circuit is provided between the Vdd line and the Vss line, and a capacitor is connected between the V-Vdd line and the Vdd line and between the V-Vss line and the Vss line, thereby stabilizing the characteristics. A technique is known (for example, refer to Patent Document 1).

The problem to be solved by the invention described in Patent Document 1 is that the manufacturing period is prolonged in the layout design of the standard cell system, and therefore, the entire application part of the MTCMOS is realized by the gate array system. Further, Patent Document 1 discloses an example in which the capacitor is formed by diode-connecting a transistor in a unit cell that is not used during wiring processing of MTCMOS among unit cells (also referred to as basic cells) constituting a gate array. Has been described.
Japanese Patent No. 3209972

  When all gate arrays are used, the circuit configuration can be changed simply by changing the wiring, so there is an advantage that the development period can be shortened, but on the other hand, a wasteful area that is not used as a logic circuit is likely to occur. It is inferior in terms of downsizing and effective use of area.

In the example described in Patent Document 1, in an MTCMOS application region, an arrangement region (unit cell array) of a unit cell of a low threshold transistor constituting a logic circuit and a unit cell of a high threshold transistor constituting a latch circuit Is provided with a switch transistor arrangement region called a power switch. For this reason, this arrangement | positioning area | region is prescribed | regulated previously with the maximum value of the gate width of a required switch transistor (power switch). Therefore, in many cases, the gate width of the power switch that is finally required is less than the maximum gate width defined by the arrangement region prepared in advance, and in this case, there is a disadvantage that area is wasted. suffer.
In addition, since the capacitor, which is a circuit element for adjusting characteristics, is formed using unused unit cells in the unit cell, the disadvantage that the area is wasted in the arrangement region of the power switch cannot be solved.
Furthermore, in the layout in which the power switch is arranged around, the wiring resistance of the V-Vdd line and the V-Vss line tends to increase. Therefore, in Patent Document 1, a configuration in which a part of the power switch is arranged inside the unit cell array is also shown as another example of the first embodiment. In this case, the power specified around the unit cell array is shown. This is at the expense of additional area waste in the original switch placement area.

Further, the layout design of the semiconductor integrated circuit that predetermines the arrangement region of the switch transistor (power switch) has the following disadvantages.
Although the detailed procedure of layout design is not disclosed in Patent Document 1, according to a general layout design method, a placement area of a logic circuit and a power switch is determined, provisional wiring is performed after logic synthesis and layout, After that, the delay and the leakage current value are analyzed by simulation and the like, the layout and wiring are revised according to the analysis result, and further verified by simulation. If a satisfactory result is obtained, the final layout and wiring are determined. At that time, if satisfactory results are not obtained by reworking, the above procedure is repeated from the beginning.
In such a general layout design method, the delay gate, the leakage current value, etc. must be analyzed by simulation after logic synthesis to determine the total gate width and arrangement position of the switch transistors. Therefore, it takes time for simulation, and not only does it take a long time for reworking and actual verification and turnaround time (TAT), but also the automatic design adaptation in that the placement position cannot be determined until simulation is performed. Is difficult.
In addition, since the total gate width and placement position of the switch transistor are uniquely determined, if there is a problem in the delay of the logic circuit after the placement of the logic circuit or latch circuit cell, the total gate of the switch transistor There is a drawback that design flexibility is poor, such as making it difficult to change the width.

A first problem to be solved by the present invention is that a semiconductor integrated circuit having a logic circuit and a switch transistor whose size of an appropriate arrangement region is determined according to the logic circuit, such as MTCMOS, It is easy to generate a useless area that is not used for the circuit or the power supply control.
The second problem to be solved by the present invention is a general layout design method for first determining the arrangement area of the circuit block, and the semiconductor integrated circuit in which the optimum value of the arrangement area changes. When it is applied to the layout design, it takes time and labor to verify characteristics by simulation or the like, and it is difficult to adapt flexibly to the change, so it is difficult to adapt to design automation.

A semiconductor integrated circuit according to the present invention is for solving the first problem, and includes a logic circuit connected between a virtual power supply voltage supply line and a virtual reference voltage supply line, and a virtual power supply voltage supply. A semiconductor integrated circuit having a switch transistor connected between a line and a power supply voltage supply line or between a virtual reference voltage supply line and a reference voltage supply line and turned on when the logic circuit is operating and turned off when the logic circuit is not operating The basic cell array has a cell arrangement structure in which a plurality of gate array regions are dispersedly arranged in the standard cell region, a logic circuit is formed by the standard cells constituting the standard cell region, and the gate array constituting each gate array region The cell forms a switch transistor that controls power supply and leakage path interruption of adjacent logic circuit portions.
In this semiconductor integrated circuit, preferably, the number of basic cells in each gate array region is defined as a number corresponding to the scale of the logic circuit part to be controlled for power supply voltage supply, and the number of basic cells is smaller than the specified number. When the power supply control with the necessary characteristics can be performed by the number, circuit elements for characteristic adjustment are formed by basic cells other than the necessary number.

  According to the semiconductor integrated circuit having the above configuration, the logic circuit is formed of standard cells, and has a cell arrangement structure in which a plurality of gate array regions are distributed in the arrangement region. The basic transistor in each gate array region forms a switch transistor that controls power supply and leakage path blocking of adjacent logic circuit units. Further, as a more preferable case, the number of basic cells in each gate array region is defined to be a number corresponding to the scale of the logic circuit part that is the control target of power supply voltage supply. In this case, when power supply control with necessary characteristics can be performed with a smaller number of basic cells than the specified number, circuit elements for characteristic adjustment are formed with basic cells other than the necessary number.

A method for designing a layout of a semiconductor integrated circuit according to the present invention is to solve the second problem described above, and includes a logic circuit connected between a virtual power supply voltage supply line and a virtual reference voltage supply line. A semiconductor having a switch transistor connected between the virtual power supply voltage supply line and the power supply voltage supply line or between the virtual reference voltage supply line and the reference voltage supply line and turned on when the logic circuit is operating and turned off when the logic circuit is not operating A method for designing a layout of an integrated circuit, comprising: a logic design step for designing a logic circuit with standard cells; a standard cell region in which the logic circuit is formed; A region determining step for determining a plurality of gate array regions each capable of forming a number of power supply voltage control transistors according to the scale; A layout step in which standard cells constituting a logic circuit are arranged in the dead cell area, and a power supply voltage control transistor is arranged in each gate array area so that the signal delay amount corresponding to the arrangement information is the minimum necessary number, And a wiring step for connecting the power supply voltage control transistor.
In this layout design method, preferably, when the maximum number of power supply voltage control transistors are arranged in each of the plurality of gate array regions in the layout step, the signal delay amount of the logic circuit section corresponding to each gate array region And the number of power supply voltage control transistors to be reduced in each gate array region is determined from the signal delay amount, thereby optimizing the number of power supply voltage control transistors individually in each gate array region.
More preferably, when there is an unused area in the gate array area when the number of power supply voltage control transistors is optimized in the layout step, in the next wiring step, the basic of the gate array in the unused area is determined. Wiring in which circuit elements for characteristic adjustment are formed in the cell is performed.

  According to the semiconductor integrated circuit of the present invention, since the logic circuit showing the most area is formed by the standard cell, it is actually used in the circuit configuration as compared with the case where the logic circuit is formed from the gate array. There is an advantage that there is almost no wasted area, and as a result, the occupied area as a whole is small. Further, since the switch transistors are formed from the basic cells of the plurality of gate array regions distributed in the standard cell region, the virtual power supply voltage supply line and the power supply voltage supply line are compared with the case where the power supply transistors are arranged around the logic circuit. There is an advantage that the wiring resistance to the power supply point of the logic circuit of the virtual reference voltage supply line can be reduced. In addition, since the wiring resistance can be reduced, the gate width of the switch transistor can be reduced to the necessary minimum, and as a result, the leakage characteristics can be improved and the delay penalty of the logic circuit section can be improved. .

  According to the layout design method for a semiconductor integrated circuit according to the present invention, there is almost no wasted area in the logic circuit as described above, and the wiring resistance to the power supply point of the logic circuit of the virtual power supply voltage supply line and the virtual reference voltage supply line There is an advantage that the leakage characteristic and the delay penalty of the logic circuit section are improved. In addition, the voltage value supplied to the power supply point of the actual logic circuit can be accurately estimated, and the signal delay amount of the logic circuit can be analyzed from this and the arrangement information of the logic circuit. Based on the result, each gate can be analyzed. It is possible to determine the number of switch transistors required in the array area. Therefore, there is an advantage that the layout accuracy of the switch transistor is high.

FIG. 1 is a layout diagram of a semiconductor integrated circuit using MTCMOS according to an embodiment of the present invention. The semiconductor integrated circuit 1 is provided with a circuit block to which MTCMOS is applied.
Although the details will be described later, the circuit block to which the MTCMOS configuration is applied has a virtual power supply voltage supply line (V-Vdd line) and a virtual reference separately from a normal power supply voltage supply line (Vdd line) and a reference voltage supply line (Vss line). A voltage supply line (V-Vss line) is provided, and a logic circuit having a necessary function is connected to the V-Vdd line and the V-Vss line. The V-Vdd line and the V-Vss line are supplied with voltages from the Vdd line and the Vss line, respectively, and are electrically connected by an MTCMOS switch transistor as a switch transistor. In addition, when the MTCMOS switch transistor is in the OFF state, the V-Vdd line or the V-Vss line is in an electrically floating state, but if the data of the logic circuit is not held in that state, there is a problem in operation. It is also necessary to provide a latch circuit.
As described above, when the MTCMOS configuration is applied, the circuit block becomes redundant in terms of circuit. Therefore, it is desirable to apply the MTCMOS configuration only to a circuit portion in which a leakage current is a problem during a low voltage operation.

  In the layout example shown in FIG. 1, in the circuit region 3 located inside the chip from the arrangement region of the pad 2 at the peripheral edge of the semiconductor integrated circuit 1, a specific functional circuit block among the functional circuit blocks 4A to 4E, which is a function in this example, The MTCMOS configuration is applied only to the circuit blocks 4A and 4E, and the MTCMOS configuration is not applied to the remaining functional circuit blocks 4B, 4C, and 4D. In the remaining circuit area 3 excluding these functional circuit blocks 4A to 4E, common circuits are arranged in the entire functional circuit blocks such as a power supply circuit, an input / output circuit and a timing control circuit, although not particularly shown. Yes.

FIG. 2 is a diagram showing a configuration of the circuit block 4A or 4E to which the MTCMOS configuration is applied. FIG. 2 is a diagram showing a conceptual configuration, not an actual arrangement. 3A and 3B schematically show an example of an array configuration (an actual arrangement example) in the circuit block 4A or 4E to which the MTCMOS configuration is applied.
As shown in FIG. 2, each of the circuit blocks 4A and 4E to which the MTCMOS configuration is applied includes a group of random logic units 40 in which a logic circuit 41 and a latch circuit 42 are arranged, and a high-level side composed of, for example, PMOS transistors. The group consists of a group of MTCMOS switch transistors 43 and a group of MTCMOS switch transistors 44 on the low level side made of, for example, NMOS transistors.
The logic circuit 41 of the random logic unit 40 realizes a predetermined circuit function by its gate configuration, and is connected to a virtual power supply voltage supply line (V-Vdd line) and a virtual reference voltage supply line (V-Vss line). Yes. The latch circuit 42 is connected between the power supply voltage supply line (Vdd line) and the reference voltage supply line (Vss line), and is connected to be able to hold the data of the logic circuit 41 by being driven by the power supply voltage. In some cases, only the data holding portion is connected to the actual power supply lines (Vdd line and Vss line). In this case, it is not necessary to connect the entire latch circuit 42 to the actual power supply line. Further, depending on the system, there is a case where it is not necessary to retain the data of the MTCMOS application block. In this case, it is not always necessary to connect the latch circuit 42 to the actual power supply. For example, in a system in which a reset or preset is entered when the power is turned off and the power is supplied again, it is not necessary to connect the latch circuit 42 to the actual power source.
Each of the MTCMOS switch transistors 43 and 44 is provided in a single or a predetermined number with respect to one random logic section 40, and the total gate width is defined by the number. Note that the switch transistor may be provided on at least one of the high level side and the low level side, or may be provided on both as illustrated. Hereinafter, the case where it is provided in both is illustrated.

  The high level MTCMOS switch transistor 43 is connected between the Vdd line and the V-Vdd line, and the low level MTCMOS switch transistor 44 is connected between the Vss line and the V-Vss line. These switch transistors 43 and 44 are controlled to be turned on and off by the control gate line CG1 or CG2 connected to the gate, and are turned on when the random logic unit 40 is operated to supply the power supply voltage Vdd to the V-Vdd line. When the random logic unit 40 is not in operation, the random logic unit 40 is turned off to block the leakage current path flowing through the logic circuit 41.

  The random logic section 40 including the logic circuit 41 and the latch circuit 42 is provided as a standard cell region SC arranged and formed by the standard cell method as in the arrangement example shown in FIG. 3, and the MTCMOS switch transistors 43 and 44 are It is provided as a gate array region GA arranged and formed by the gate array method. Here, as is well known, in the standard cell system, for example, logic gates and circuit elements such as AND, NAND, or OR are designed as cells and registered as libraries, and in each cell, the shape of the diffusion layer, Although the positions are not uniform, the terminal positions of input / output signals, power supply voltage supply lines, reference voltage supply lines, and the like are standardized so that they can be connected to each other when cells are selected and arranged. In contrast, in the gate array method, CMOS transistor cells (called basic cells or unit cells) with the same shape and position of the diffusion layer are arranged in an array, and a specific circuit function is realized depending on the wiring shape and the presence or absence of contacts. This is a cell system.

  The MTCMOS application blocks 4A and 4E of the present embodiment are not a cell arrangement structure in which one of different cell systems surrounds the other, but a cell arrangement in which a plurality of gate array areas GA are arranged in a distributed manner in the standard cell area SC. It has a structure. Therefore, the delay due to the virtual wiring (V-Vdd line, V-Vss line) of the power supply voltage Vdd and the reference voltage Vss switched by the MTCMOS switch transistors 43 and 44 formed in the gate array region GA is reduced. The MTCMOS switch transistors 43 and 44 and the logic circuit 41 portion (the portion of the standard cell region SC) that is the object of power supply control can be arranged close to each other at appropriate positions. For example, if the switch transistor closest to an arbitrary standard cell determines the delay speed of power supply control, the distance (or wiring impedance) between the standard cell and the switch transistor is an ideal value for all standard cells. When the distance is shorter than a short distance (or a small wiring impedance), it can be determined that the logic circuit and the switch transistor are properly arranged. In the present embodiment, this proper arrangement is realized by distributing a plurality of gate array areas GA in the standard cell area SC.

  By the way, in the standard cell system, it is defined that the Vdd line and the Vss line are arranged in one direction, and when the V-Vdd line and the V-Vss line are wired in the same direction, they are orthogonal to those wirings. In some cases, the same kind of wiring is appropriately connected in such a direction so that power is supplied as uniformly as possible in the chip. At this time, in the case where a portion where the same kind of wiring is connected is formed by the gate array region GA, the arrangement of the gate array region GA may be a parallel strap as shown in FIG. However, the location where the same type of wiring is connected can also be provided as a special registered standard cell. In such a case, the gate array area GA does not need to be continuous in a direction orthogonal to the wiring direction, and the gate array area GA can be arbitrarily disposed at a necessary position as shown in FIG. In short, it is only necessary that a plurality of gate array regions GA are distributed in the standard cell region SC. As shown in FIGS. 3A and 3B, the present invention is not limited to these diagrams. The size and position of the array area GA and the number thereof are arbitrary.

Here, the total gate width of the MTCMOS switch transistors 43 and 44 (or one of them) to be arranged is about 10% of the total gate width W of all the random logic sections 40 (standard cell regions SC). Alternatively, it is determined according to a value obtained by adding several percent to the delay penalty. The signal delay between the flops (not shown) constituting the various gate circuits in the random logic unit 40 is relatively small when the MTCMOS switches 43 and 44 constituted by the gate array are not provided. Providing MTCMOS switches 43 and 44 tends to increase. This increase in signal delay in the random logic section 40 due to the application of MTCMOS is referred to herein as a “delay penalty”.
The total gate width of these switch transistors may be a value roughly determined by a design policy or the like. When the total gate width of the switch transistor is about 10% of the total gate width of the random logic section, the total gate width value of the random logic section can be easily understood from the estimation of the gate scale at the time of logic synthesis design. There is no need to run a simulation.

FIG. 4 is an enlarged plan view showing, for example, a portion of standard cell region SC adjacent to the gate array region GA in the same row as the range shown in part A of FIG. 3A.
In the example shown in FIG. 4, the portion of the gate array region GA is composed of five basic cells BC1 to BC5, and the basic cells BC3 to BC5 are cells in which a PMOS switch transistor and an NMOS switch transistor are provided in pairs, basic cells BC1 and BC2. Is a cell provided with one capacitor for stabilizing the virtual line potential as a cell for characteristic adjustment.

  Since the basic cells BC3 to BC5 have the same configuration, the basic cell BC5 will be described as a representative example. In the basic cell BC5, an N-type impurity diffusion region 51 in which the PMOS switch transistor 43 is formed and an NMOS switch transistor are formed. P-type impurity diffusion region 52. Two gate lines 53 are arranged so as to cross each of the N-type and P-type impurity diffusion regions 51 and 52. The two gate lines 53 are connected to a control gate line CG1 or CG2 made of an upper wiring layer (not shown).

The V-Vdd line for supplying a voltage to the random logic circuit in the standard cell region SC is composed of a first layer metal wiring (1MT) indicated by hatching in FIG. The V-Vdd line is wired along one of the cell boundaries in the row direction in the standard cell region SC and is shared by adjacent standard cell rows, but is bent inside the basic cell BC5 in the gate array region GA. , And passes between the N-type impurity diffusion region 51 and the P-type impurity diffusion region 52. The V-Vdd line is connected to the drain region D between the two gate lines 53 in the N-type impurity diffusion region 51.
On the other hand, in the gate array region GA, a Vdd line made of 1MT is wired along one of the cell boundaries in the row direction, and two branch lines of the Vdd line extend to the N-type impurity region 51 side for each cell. The two source regions S outside the two gate lines are connected to each other.

Along the other cell boundary in the row direction of the standard cell region SC, a V-Vss line made of 1MT is wired and shared by adjacent standard cell rows. The V-Vss line is bent inside the basic cell BC5 in the gate array region GA and passes between the N-type impurity diffusion region 51 and the P-type impurity diffusion region 52. The V-Vss line is connected to the drain region D between the two gate lines 53 in the P-type impurity diffusion region 52.
On the other hand, in the gate array region GA, a Vss line made of 1MT is wired along the other of the cell boundaries in the row direction, and two branch lines of the Vss line extend to the P-type impurity region 52 side for each cell. The two source regions S outside the two gate lines are connected to each other.

  As described above, the Vdd line (1MT) wired along one cell boundary in the gate array region GA and the Vss line (1MT) wired along the other cell boundary are respectively connected to adjacent cell rows. Shared on. Further, it is connected to the upper second-layer metal wiring (2MT) by an appropriate contact. The Vdd line (2MT) and the Vss line (2MT) are wired along the respective cell boundaries. In the standard cell region SC, the V-Vdd line (1MT) or the V-Vss line (1MT) used for power supply. The upper layer is wired through in parallel.

Next, the configuration of a capacitor composed of basic cells in the gate array region GA will be described.
In the basic cell BC1, a capacitor is configured by connecting a PMOS transistor in a diode connection, that is, by interconnecting a gate and a source. Specifically, one of the two branch lines of the Vdd line (1MT) common to the basic cells BC3 to BC5 constituting the switch transistor extends to the N-type impurity diffusion region 51 side, and the source of the N-type impurity diffusion region 51 In addition to being connected to the region S, it is also connected to one gate line 53. Similarly, the other branch line is connected to the other source region S of the N-type impurity diffusion region 51 and also connected to the other gate line 53. The drain region D of the N-type impurity diffusion region 51 is connected to the V-Vss line (1MT) by a cross connection line 54 made of 2MT.

  In the basic cell BC2, a capacitor is configured by connecting an NMOS transistor in a diode connection, that is, by connecting a gate and a source to each other. Specifically, one of the two branch lines of the Vss line (1MT) common to the basic cells BC3 to BC5 constituting the switch transistor extends to the P-type impurity diffusion region 52 side, and the source of the P-type impurity diffusion region 52 In addition to being connected to the region S, it is also connected to one gate line 53. Similarly, the other branch line is connected to the other source region S of the P-type impurity diffusion region 52 and also to the other gate line 53. The drain region D of the P-type impurity diffusion region 52 is connected to the V-Vdd line (1MT) by a cross connection line 55 made of 2MT.

With such a configuration, a capacitor is connected between the Vdd line and the V-Vss line (basic cell BC1) and between the Vss line and the V-Vdd line (basic cell BC2). The fluctuation component is removed through the capacitor. As a result, the potential of the V-Vdd line and the V-Vss line is stabilized, and the stable operation of the logic circuit is achieved.
As an example of the characteristic adjustment cell other than the capacitor, for example, when it is found that the logic of the logic circuit is inverted after the logic design, an inverter that inverts the logic is used as the basic cell. May be formed.

Next, a layout design method for the semiconductor integrated circuit having such a configuration will be described.
First, the ratio of the gate array region GA is determined by a method typified by the two methods described above. That is, the total gate width of the MTCMOS switch transistor is determined in accordance with, for example, about 10% of the total gate width of all random logic parts (standard cell regions SC) or a value obtained by adding several% to the delay penalty. To do. Then, in order to obtain the determined ratio, for example, the gate array area GA is determined as shown in FIGS. 3A and 3B, and the basic cell shown in FIG. MTCMOS switch transistor cells such as BC3 to BC5 are arranged. At this time, since the random logic cell uses the standard cell system, it has not been arranged yet.

5 to 8 are diagrams illustrating an example of a switch transistor arrangement method. Each figure shows a state when layout design steps are different.
Next, random logic cells are arranged by the standard cell method. At this time, random logic cells are not arranged in the switch transistor arrangement region (gate array region GA) arranged in advance. Further, the switch transistor itself does not change the arrangement position. For example, as shown in FIG. 5, the arranged switch transistor is connected to the random logic cell portion leaving a certain amount.

  When all the connections with the random logic cell unit are completed, the timing and power are analyzed in the same manner as in the conventional design flow. If there is a problem with the delay of the random logic cell portion, the delay penalty can be reduced by connecting the unconnected switch transistor and the random logic cell. Conversely, where there is a margin in the delay penalty, the connection of the connected switch transistor is disconnected in order to suppress the leakage current. As a result, for example, as shown in FIG. 6, the connection and non-connection of the MTCMOS switch transistor to the random logic part are roughly optimized.

  At this time, as shown in FIG. 6, the number of cells in the width direction of the gate array area GA determined first, in this example, there are portions where all four basic cells are already connected, so that the delay penalty is within a desired value. There is no problem if it can be suppressed. Of course, if the delay penalty is still too large, the total gates of the switch transistors to be connected should be larger than the number of cells in the width direction of the gate array area GA that was initially determined by looking at the usage rate of the random logic cell part. A method of controlling the width can be adopted.

  FIG. 7 shows the state after further delay penalty optimization by this method. A portion surrounded by an ellipse shown in FIG. 7 is a portion where the delay penalty is too large even when four specified basic cells are connected and the gate width of the switch transistor is quadrupled. In such a place, as shown in the figure, a basic cell (switch transistor cell) exceeding the specified number (4) is expanded and disposed in an unused portion of the random logic cell portion, and the gate width of the switch transistor is further increased. To do.

On the other hand, when the gate width is too large and the leakage current becomes out of specification, such expansion of the number of cells is limited according to the value.
As described above, the gate width of the switch transistor is determined so as to be optimal at each location so as to satisfy both the delay penalty and the leakage current.
Thereafter, as shown in FIG. 8, the unconnected MTCMOS switch transistor cell (unused basic cell) is replaced with a circuit element for characteristic adjustment, for example, a capacitor cell. Thereby, a useless area is effectively used. Note that in locations where the number of capacitors is small, the use of adjacent standard cell regions may be confirmed, and if unused, the gate array region may be partially expanded and replaced with capacitor cells.

The semiconductor integrated circuit according to the embodiment of the present invention provides the following advantages.
First, since the logic circuit showing a large area is formed of standard cells, there is almost no wasted area that is not actually used in the circuit configuration compared to the case where the logic circuit is formed from a gate array. As a result, there is an advantage that the occupied area as a whole is small.
Second, since the switch transistors are formed from basic cells in a plurality of gate array regions distributed in the standard cell region, the virtual power supply voltage is supplied as compared with the case where the power supply transistors are arranged around the logic circuit. There is an advantage that the wiring resistance to the feeding point of the logic circuit of the line and the virtual reference voltage supply line can be reduced. In addition, since the wiring resistance can be reduced, the gate width of the switch transistor can be reduced to the necessary minimum, and as a result, there is an advantage that the leakage characteristic and the delay penalty of the logic circuit are improved.
Third, since circuit elements for characteristic adjustment are formed by basic cells other than the necessary number, there is less area waste.
Fourth, when the wiring for supplying the power supply voltage or the reference voltage is formed by the two metal wiring layers, the V-Vdd line and the V-Vss line for feeding the standard cell running on the cell boundary are Since the second-layer metal wiring is formed on the first-layer metal wiring layer, the wiring structure is simple and does not occupy a useless area.

Furthermore, the layout design method of the semiconductor integrated circuit according to the present embodiment has a step of analyzing timing and power, and in that respect, is not different from the conventional method, but in this step, it is not always necessary to perform a simulation. The analysis can be easily performed from the arrangement information of the random logic. Of course, a simulation may be performed, but even in this case, in this embodiment, it is not necessary to perform the simulation many times. At least once, at most, the first simulation and the simulation for checking after the cell change No more than two times. In this way, the number of switch transistors is estimated. Since the accuracy of the estimation is increased, the transition from the logic design to the placement and routing flow can be performed smoothly. Further, since the switch transistors are arranged in advance, the correction after the arrangement and wiring can be easily performed.
For the above reasons, as a result, it is possible to reduce the time required for the overall layout design and to obtain the benefits that TAT can also be shortened.

  Further, in the conventional method, the switch transistors are arranged only for the predetermined total gate width value, so that it is difficult to correct when there is a problem in the delay value or the like. In contrast, in the layout design method according to the present embodiment, the total gate width of the switch transistor can be easily changed only by selecting whether to connect or disconnect. Further, by replacing the space of the transistor that is not connected with a capacitor, it is possible to save space.

  Thus, in the layout design method according to the present embodiment, the total gate width of the switch transistors can be changed even after the random logic cells are arranged, and the design is flexible, such as replacing the remaining switch transistors with capacitors or the like. Since the change is easy, the MTCMOS application block can be designed without much difference from the conventional standard cell design method before applying the MTCMOS.

1 is a layout diagram of a semiconductor integrated circuit using MTCMOS according to an embodiment of the present invention. It is a figure which shows the structure of the circuit block to which MTCMOS structure is applied. (A) And (B) is a figure which shows two examples of the array structures in the circuit block to which the MTCMOS structure is applied. FIG. 5 is an enlarged plan view showing a part of a gate array region and a standard cell region portion adjacent to the same row in the same row. It is a figure which shows the state which has arrange | positioned and connected the switch transistor partially. It is a figure which shows the state after optimizing the gate width of a switch transistor from the state of FIG. It is a figure which shows the state after optimizing the gate width of a switch transistor using the number of switch transistors exceeding the width | variety of the first gate array area | region. It is a figure which shows the state after replacing the cell of an unconnected switch transistor with the cell of a capacitor.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Pad, 3 ... Circuit area | region, 4A, 4E ... MTCMOS application block, 4B-4D ... MTCMOS non-application block, 40 ... Random logic part, 41 ... Logic circuit, 42 ... Latch circuit, 43 ... P-type switch transistor, 44 ... N-type switch transistor, 51 ... N-type impurity diffusion region, 52 ... P-type impurity diffusion region, 53 ... Gate line, 54,55 ... Cross connection line, BC1 to BC5 ... Basic cell, GA: Gate array region, SC: Standard cell region, Vdd: Power supply voltage supply line, V-Vdd: Virtual power supply voltage supply line, Vss: Reference voltage supply line, V-Vss: Virtual reference voltage supply line

Claims (6)

A logic circuit connected between the virtual power supply voltage supply line and the virtual reference voltage supply line, and between the virtual power supply voltage supply line and the power supply voltage supply line or between the virtual reference voltage supply line and the reference voltage supply line. And a switch transistor that is turned on when the logic circuit is in operation and turned off when the logic circuit is not in operation.
A cell arrangement structure in which a plurality of gate array regions are distributed and arranged in a standard cell region,
A logic circuit is formed by the standard cells constituting the standard cell region.
A switch transistor for controlling power supply and leakage path blocking of adjacent logic circuit portions is formed by basic cells of the gate array constituting each gate array region. Semiconductor integrated circuit. The number of basic cells in each of the gate array regions is defined as a number according to the scale of the logic circuit unit that is a control target of power supply voltage supply,
2. The semiconductor integrated circuit according to claim 1, wherein a circuit element for adjusting characteristics is formed by a basic cell other than the required number when power supply control with a required characteristic is possible with a smaller number of basic cells than the specified number. circuit. Each of the virtual power supply voltage supply line and the virtual reference voltage supply line for supplying a voltage to the logic circuit extends from the standard cell region where the logic circuit is formed into the gate array region, and the source and drain of the switch transistor. A first wiring layer connected to one of the
Each of the power supply voltage supply line and the reference voltage supply line is connected to the other one of the source and drain of the switch transistor in the standard cell region, and the other first wiring layer. And an upper second wiring layer connected by a contact,
2. The semiconductor integrated circuit according to claim 1, wherein the second wiring layer is arranged along the first wiring layer above the first wiring layer that is arranged in the standard cell region and supplies a voltage to the logic circuit. A logic circuit connected between the virtual power supply voltage supply line and the virtual reference voltage supply line, and between the virtual power supply voltage supply line and the power supply voltage supply line or between the virtual reference voltage supply line and the reference voltage supply line. A layout design method of a semiconductor integrated circuit having a switch transistor that is connected to the switch circuit and is turned on when the logic circuit is operated and turned off when the logic circuit is not operated,
A logic design step of designing a logic circuit with standard cells;
A standard cell region in which a logic circuit is formed and a plurality of gate array regions that are dispersedly arranged in the standard cell region and each of which can form a number of power supply voltage control transistors according to the scale of the corresponding logic circuit unit are determined. An area determination step;
A layout step in which standard cells constituting a logic circuit are arranged in the standard cell region, and power supply voltage control transistors are arranged in each gate array region so as to be a necessary minimum number from a signal delay amount corresponding to the arrangement information;
A layout design method for a semiconductor integrated circuit, comprising: a wiring step for connecting a arranged logic circuit and a power supply voltage control transistor. In the layout step, when the maximum number of power supply voltage control transistors are arranged in each of the plurality of gate array regions, the signal delay amount of the logic circuit unit corresponding to each gate array region is estimated, and each signal delay amount is estimated from the signal delay amount. 5. The layout design method for a semiconductor integrated circuit according to claim 4, wherein the number of power supply voltage control transistors is reduced in each gate array region by determining the number of power supply voltage control transistors to be reduced in the gate array region. If there is an unused area in the gate array area when the number of power supply voltage control transistors is optimized in the layout step, the characteristic adjustment is made to the basic cells of the gate array in the unused area in the next wiring step. The layout design method for a semiconductor integrated circuit according to claim 5, wherein wiring for forming a circuit element is performed.

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