JPH10327159A - Master device used for transmission system, synchronization circuit and clock synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of bit synchronization in a transmitter that receives a burst signal and conducts bit synchronization. SOLUTION: Upon the receipt of a burst signal sent from pluralities of subscriber's devices to a station device, a mask signal generating circuit 21 generates a mask signal for at least part from production of a reset signal till a prior part of a guard area of a succeeding burst signal depending on a phase of the received burst signal. A mask circuit 17 prevents malfunction of a bit synchronization circuit 18 by forcibly fixing the burst signal to a logical '0' when the mask signal is generated. The bit synchronization circuit 18 establishes the synchronization for a preamble area after the guard area.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main device used in a transmission system and a signal receiving method in the main device, and more particularly to a main device used in a PDS transmission system with improved burst signal reception accuracy. And a clock synchronization method in the main device.

[0002]

2. Description of the Related Art PDS (Passive) is a system in which a plurality of home devices (subordinate devices) are connected to a station device (main device) and data is transmitted as a burst signal between the station device and the home device. Double Star) transmission system. The cell format of the burst signal in the PDS transmission system is determined, and a guard area of all 0 signals indicating the head of the burst signal and 1 / necessary for bit synchronization.
It is composed of a 0-alternative preamble area, a delimiter area, a data identification area, and an ATM cell area. On the side of the station device, in order to receive a burst signal of the optical signal, an optical receiving unit that converts the optical signal into an electric signal, and a synchronization that establishes synchronization in a 1/0 alternating preamble area for each received burst signal. And a circuit.

[0003] As a prior art of this synchronous circuit, a "high-speed PDS" described in IEICE Technical Report SSE95-93 (1995-09) is described.
Bit Synchronization Circuit for Burst Signal Transmission in System ".

[0004]

In this prior art synchronous circuit, a reset signal is generated when a new burst signal is input in order to synchronize each burst signal having a different optical level and phase. , The operation of the optical receiver is reset. This will be described with reference to FIG. FIG. 5A shows the output timing of the reset signal, the reception level of the optical signal of the burst signal, and the threshold voltage waveform of the optical level in the optical / electrical conversion inside the optical receiver. As shown in FIG. 5A, since the optical levels of the received burst signals are different from each other, the optical receiver sets the optical level threshold to ATC (Auto).
Threshold controller (automatic threshold control function) is set for each burst signal. In this case, the synchronization circuit
After the reception of the burst signal, a reset signal is output to the optical receiver, and the optical receiver receives the reset signal, sets the optical level threshold to the minimum value, and then responds to the amplitude of the received burst signal. Set a threshold determined by For this reason, the threshold voltage is minimized from the application of the reset signal until the threshold value determined according to the amplitude of the received burst signal is set, and a slight noise signal is erroneously determined to be the logical value “1”. there's a possibility that. FIG. 5 (2) shows that noise is generated in the guard area because the threshold voltage is low, and the logic value “1,
An example of an output signal of the optical receiving unit when an erroneous determination is made as 0, 1, 0, 1, 0 "is shown. In this case, the reset signal 26 is shown.
After the output of, the next preamble area 12 and the superimposed noise cannot be distinguished from each other due to the erroneous determination of the logical value. There was something.

An object of the present invention is to provide a main device, a synchronizing circuit, and a clock synchronizing method for a main device used in a PDS transmission system capable of performing bit synchronization with higher accuracy in order to solve the above problems. .

[0006]

In order to solve the above-mentioned problems, the present invention is used in a transmission system for communicating between a main device and a plurality of other devices, and is determined in advance by a plurality of other devices. Receiving a burst signal transmitted at the same phase, and generating a reset signal each time reception of the burst signal is completed, receiving the burst signal, and synchronizing the burst signal with the data of the burst signal. Discriminating means for discriminating; and suppressing means for suppressing execution of discrimination by the discriminating means in at least a part of a period from the generation of the reset signal to just before an area for detecting the bit synchronization of a next burst signal. Have. For this reason, the execution of the determination by the determination means can be suppressed in at least a part of the period from the generation of the reset signal to just before the area for detecting the bit synchronization of the next burst signal. It can be performed more accurately.

Further, the discriminating means includes a bit synchronization circuit for extracting a clock synchronized with the burst signal from the burst signal, and a head of the data of the burst signal in accordance with the clock extracted by the bit synchronization circuit. It can have a head synchronization circuit for identification.

Further, the suppression means includes a mask signal generation circuit for generating a mask signal in at least a part of the period from the generation of the reset signal to a position before the area for detecting the bit synchronization of the next burst signal. A mask circuit for setting the burst signal to a non-signal state when the mask signal is generated in the mask signal generation circuit.

In addition, as a synchronization circuit, a bit synchronization circuit that extracts a clock synchronized with the burst signal from the burst signal, and a head of the data of the burst signal is identified according to the clock extracted by the bit synchronization circuit. And at least a portion of the clock signal generated by the bit synchronization circuit, from the generation of the reset signal to the portion before the region for the bit synchronization detection of the next burst signal, which is determined by the phase. A means for suppressing extraction may be provided. This synchronization circuit can be formed by an integrated circuit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a P using a burst signal
The configuration of the DS transmission device will be described with reference to FIG.
As shown in FIG. 1, the plurality of home devices (# 1 to #n)
It is connected to a single station device 1 via an optical fiber transmission line 10 and an optical star coupler (optical branch element) 6. Data from the station device 1 is input to the optical star coupler 6 via the optical fiber transmission line 10. The optical star coupler 6 branches this data and transmits the same data to each of the home devices (# 1 to #n). This data is treated as a downstream signal, and a continuous signal is transmitted. As shown in FIG. 1, the uplink signal in the reverse direction is data transmitted from the home devices (# 1 to #n) to the station device 1, and is transmitted for each of the home devices (# 1 to #n). At a predetermined phase (predetermined period), the signal is sent out as a burst signal to the optical fiber transmission line 10 and input to the optical star coupler 6. This predetermined phase is a signal propagation delay on the transmission path between the in-home devices (# 1 to #n) and the station device 1, that is, a fixed delay time determined by the length of the optical fiber transmission line 10. Considering the time and the delay time due to the variation of the transmission path characteristics (temperature and the like) over time, the home device (#
1 to #n) are determined at the time of system configuration so that the data does not collide when the upstream data from each of the optical star couplers 6 merges. For example, as shown in FIG. 1, the data 1 transmitted from the in-home device # 1 to the station device 1 and the data 2 transmitted from the in-home device # 2 to the station device 1 are composed of an optical star coupler 6. Is transmitted with a phase that does not cause a collision when optical multiplexing is performed. Similarly, data 3 transmitted from in-home device # 3 to station device 1 is also
The data is transmitted with a phase that does not collide with data 1 and data 2. In this way, the PDS transmission system is configured so that data transmitted from all home devices does not collide. In the present embodiment, it is assumed that data is transmitted in a phase determined in the order of in-home devices # 1 to #n.

FIG. 2 shows a format of data of an upstream signal transmitted from each home device. This data is
Data called fixed-length cells are transmitted in bursts. The first area of this data is a guard area 11
, And each home device (# 1 to # 1)
This is a buffer area for preventing the cell weight from #n). The next preamble area 12 is composed of continuous signals of 0/1, and is used when a clock signal is extracted in the station apparatus to establish bit synchronization. The delimiter area 13 is configured with a specific pattern and is an area for identifying the head of the data area of the uplink data received by the station device. The data identification area 14 stores information for identifying a predetermined type of data. The data area 15 carries user information.

Next, the configuration of the receiving section of the station apparatus will be described with reference to FIG. 3, and FIGS.

FIG. 3 shows a functional block diagram of the receiving section of the station device. In FIG. 3, a receiving unit is connected to the optical transmission line 10 and converts an optical signal into an electric signal.
A reset signal generating circuit 24 for generating a reset signal each time a burst signal is received; and an area for detecting the bit synchronization of the next burst signal, which is determined by the phase from the generation of the reset signal. A mask signal generation circuit 21 for generating a mask signal in at least a part up to the previous time; a mask circuit 17 for setting a burst signal to a non-signal state when the mask signal is generated in the mask signal generation circuit; Area 1
2. A bit synchronization circuit 1 for extracting a clock synchronized with the data from the data pattern 2 and retiming the received data
8, a cell synchronization circuit 19 that detects the delimiter area 13 and detects the start position of the user data area 15, a reference clock generation circuit 25 that generates reference phase information based on a system timing signal of the main device, Synchronous circuit 1
9 indicates the temporal position of the head position of the cell received with respect to the reference phase based on the data head identification information output when the head position from No. 9 is detected and the reference phase information from the reference clock generation circuit 25. Cell phase monitoring circuit 2 for calculating phase information and outputting phase information at the position
3, terminal cell phase information circuit 22 for accumulating phase information for each in-home device and outputting phase information of in-home devices (# 1 to #n) corresponding to data to be received next to mask signal generation circuit 21 And

The detailed configuration of each block is shown in FIGS.
Shown in

FIG. 7 shows the configuration of the optical / electrical converter 16. In FIG. 7, the light / current conversion unit 302 outputs the light signal 3
01 is converted to a signal indicated by the current. The preamplifier 305 converts a signal represented by a current into a signal represented by a voltage. The reset conversion unit 303 receives the reset signal 26 generated from the reset signal generation circuit 24, and converts a pulse of the reset signal into a predetermined pulse width. The reference voltage generation unit 304 includes a discriminator 306
To generate a reference voltage for pulse determination in. Therefore, the reference voltage generator 304 receives a signal indicated by the voltage output from the preamplifier 305, and generates a reference voltage from the peak value and the average value of the voltage. Also,
Upon receiving the reset signal from the reset converter 303, the reference voltage generator 304 resets the reference voltage to a minimum value. The discriminator 306 compares the reference voltage from the reference voltage generation unit 304 with the voltage value of the signal indicated by the voltage output from the preamplifier unit 305, and uses the comparison result as a pulse signal 201 to generate a mask signal 17
To the bit synchronization circuit 18 via the.

Next, the configuration of the bit synchronization circuit 18 will be described with reference to FIG. In FIG. 8, the bit synchronization circuit 18
Extracts a clock synchronized with the data from the data pattern of the preamble area 12 and re-times the received data. In the bit synchronization circuit 18 shown in FIG. 8, the high-speed clock generator 203 generates a clock synchronized with the clock in the device and higher in speed than the optical signal 301. The multi-phase clock generation unit 204 uses the high-speed clock generated by the high-speed clock generation unit 203,
The multi-phase clocks having different phases are output. For example, when the number of phases is 8, eight clocks having different phases are output. The multi-phase data generator 202 samples the pulse signal 201 with the multi-phase clock generated by the multi-phase clock generator 204, and outputs the sampled data in synchronization with each of the multi-phase clocks. The change point detection unit 205 outputs a detection signal when detecting a change point of the sampling data. The optimum phase calculation unit 206 calculates the position and the number of the change points within two periods of the system clock for each change point of the sampling data, and determines the optimum retiming position. The optimum retiming position can be determined in advance based on the position and number of change points, for example, an intermediate position between the change points. The synchronization protection unit 207 includes the selector unit 2
At 08, control is performed so that sampling data synchronized with the retiming position is selected and output from the multi-phase sampling data. In this way, bit synchronization can be achieved.

Next, the cell synchronization circuit 19 will be described with reference to FIGS.

In FIG. 9, a cell synchronizing circuit 19 receives a bit-synchronized signal, detects a delimiter area 13 composed of a specific pattern sequence, and detects a head position of a user data area 15. This operation of detecting the start of the user data area is called cell synchronization. FIG.
As indicated by 0, the cell synchronization circuit 19 compares the specific pattern (fixed data) of the delimiter area 13 with the input synchronization pulse signal 209 in the pattern monitoring unit 401 bit by bit, and when they match, A cell synchronization pulse for indicating a cell synchronization position is generated. The cell synchronization pulse output from the cell synchronization circuit 19 is input to the cell phase monitoring circuit 23. The data area in which the cell synchronization has been established is input to the next stage circuit 20 and processed as a main signal in the station device.

Next, the cell phase monitoring circuit 23 will be described with reference to FIGS. The cell phase monitoring circuit 23 sends phase information indicating the phase of the cell synchronization pulse to the terminal cell phase information circuit 22 based on the cell synchronization pulse from the cell synchronization circuit 19 and the reference clock and reference phase from the reference clock generation circuit 25. Output.

In FIG. 11, a counter section 501 counts up by a reference clock output from a reference clock generation circuit 25, and holds a count value in a holding circuit 502.
Output to The counter section 501 counts up to the number of bits of one cell, sets the count value to 0 as a reference phase, and indicates phase information by the count value. The holding circuit 502 holds the count value output from the counter section 501, and outputs the held count value phase information 504 when the cell synchronization pulse 403 is input.

Next, the configuration of the terminal cell phase information circuit 22 will be described with reference to FIG. In FIG. 13, the cell phase holding circuit 601 holds the phase information from the cell phase monitoring circuit 23 in association with the identification number of the home device corresponding to the phase information. In addition, the holding circuit 601 outputs phase information corresponding to the in-home device that transmits the cell input next to the phase information 504 among the held phase information. For example, when receiving the data of the in-home device # 1 shown in FIG. 1, the phase information 504 is held in association with the in-home device # 1. Further, at that time, the phase information 604 stored in association with the in-home device # 2 that transmits the next data is output. In the cell phase generator, the home device (# 1) to which the next data to be received belongs according to the phase information 604.
To #n), outputs a guard area signal 605 indicating the guard area portion of the cell to the mask signal generation circuit 21.

The reference clock generation circuit 2 shown in FIG.
5 receives a system timing signal for controlling the operation of the main device from the next-stage circuit 20, generates a reference clock based on the information, and outputs it to the cell phase monitoring circuit 23 and the reset signal generation circuit 24.

In the mask signal generation circuit 21 shown in FIG.
From the guard area signal 605 output from the terminal cell phase information circuit 22 and the reset signal output from the reset signal generation circuit 24, the input signal is set to a no-signal state from the generation of the reset signal to the end of the guard area. To generate a mask signal for performing the operation. In the next stage mask circuit 17,
Due to the mask signal, the end point of the guard area (preamble area 1)
2) is output as a logical value "0".

Next, the relationship between data and the mask signal 27 will be mainly described with reference to FIGS.

FIG. 4A shows a relationship between a burst signal and a reset signal. FIG. 4B shows a plurality of home devices (#).
7 shows output waveforms from the optical / electrical conversion circuit 16 when a data string of a burst signal is continuously received from 1 to #n). In FIG. 4A, a preamble area in which a reset signal 26 for initializing the optical / electrical conversion circuit 16 is located at the center of the guard area 11 which is a non-signal area, and 0/1 alternately follows thereafter. It is continuing. FIG. 4 (2)
As shown in (1), the reset signal is located substantially at the center of the guard area provided between the burst data received from the home devices (# 1 to #n). FIG. 6 shows the relationship between the mask signal 27 generated in this embodiment and the burst reception data. As shown in FIG. 6A, the mask signal 27 is forcibly a no signal, that is, a logical value “0” during a period from when the reset signal 26 is generated in the guard area 11 to when the preamble area 12 starts. To the area. This mask signal 27 corresponds to mask signal generation circuit 2 shown in FIG.
1, is generated based on the guard area signal from the terminal cell phase information circuit 22 and the reset signal. Therefore, even if the burst data received from the in-home devices (# 1 to #n) deviates from the reference phase, a mask signal having an appropriate time width can be generated accordingly, and the superimposed noise signal can be masked. It is. By completely securing the no-signal area, it is possible to prevent a malfunction of bit synchronization. FIG. 6 (2) shows reception of burst reception data from the in-home devices (# 1 to #n) in chronological order. In FIG. 6 (2), the station apparatus receives three burst data signals of data 10, 20, and 11, and the phase information of each burst data is represented by P1 to P3. When data 10 and data 11 among these three burst data are received from the same in-home device # 1, it can be expected that their phase information P1 and P3 have the same value. Therefore, the terminal cell phase information circuit 22 generates a guard area signal of the data 11 based on the phase information P1 obtained at the time of receiving the data 10, whereby the mask signal generation circuit generates the mask signal m3 Can occur.

As described above, according to the present embodiment, the noise signal which may occur in the no-signal section (guard area 11) of the burst data received from the in-home devices (# 1 to #n) is masked. As a result, malfunction of the bit synchronization circuit 18 can be prevented.

Further, in the above embodiment, the mask signal is generated from the time when the reset signal is generated to the time when the guard area ends, but the mask signal is generated in the entire guard area or a part of the guard area. Is also good.

Furthermore, instead of the mask signal generation circuit and the mask circuit, a signal indicating the start point of the preamble area is instructed to the bit synchronization circuit, so that the bit synchronization circuit acquires bit synchronization after the instruction is issued. You may start.

[0029]

According to the present invention, it is possible to receive burst data transmitted from a home device to a station device and perform bit synchronization at an accurate position. Thus, stable data transmission can be configured in a PDS transmission system to which a plurality of home devices are connected.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a PDS transmission system.

FIG. 2 is a diagram showing a data structure transmitted by a burst signal.

FIG. 3 is a block diagram of a circuit that receives a burst signal and performs bit synchronization.

FIG. 4 is an explanatory diagram showing a reset signal in a burst signal.

FIG. 5 is an explanatory diagram showing an example of a cause of malfunction of bit synchronization.

FIG. 6 is an explanatory diagram for explaining a bit synchronization operation using a mask signal.

FIG. 7 is a configuration diagram of an optical / electrical conversion unit 16.

FIG. 8 is a configuration diagram of a bit synchronization circuit 18;

FIG. 9 is a configuration diagram of a cell synchronization circuit 19;

FIG. 10 is an explanatory diagram showing a cell synchronization pulse in the cell synchronization circuit 19;

FIG. 11 is a configuration diagram of a cell phase monitoring circuit 23;

FIG. 12 is an explanatory diagram showing the operation of the cell phase monitoring circuit 23;

FIG. 13 is a configuration diagram of a terminal cell phase information circuit 22;

[Explanation of symbols]

1 ... station apparatus, 2 ... home apparatus # 1, 3 ... home apparatus # 2, 4 ... home apparatus # 3, 5 ... home apparatus #n, 6 ... optical star coupler, 7
... Data 1, 8 ... Data 2, 9 ... Data 3, 11 ... Guard area, 12 ... Preamble area, 13 ... Delimiter area, 14 ...
Data identification area, 15 data area, 16 optical / electrical conversion circuit, 17 mask circuit, 18 bit synchronization circuit, 19 cell synchronization circuit, 20 next circuit, 21 mask signal generation circuit, 22 ...
Terminal cell phase information circuit, 23: cell phase monitoring circuit, 24: reset signal generation circuit, 25: reference clock generation circuit 26: reset signal, 27: mask signal.

Claims (5)

[Claims] 1. A transmission system for communicating between a main device and a plurality of other devices, receiving a burst signal transmitted at a predetermined phase from the plurality of other devices,
Each time the reception of the burst signal is completed, the main device that generates the reset signal receives the burst signal,
Determining means for establishing synchronization in an area for detecting bit synchronization of the burst signal and determining data of the burst signal; and determining the bit of the next burst signal determined by the phase from the generation of the reset signal. A main unit for use in a transmission system, comprising: a deterrent unit that deters execution of the discrimination by the discrimination unit in at least a part of a region up to a region for synchronization detection. 2. The main unit used in the transmission system according to claim 1, wherein said inhibiting means detects said bit synchronization of a next burst signal determined by said phase from generation of said reset signal. A mask signal generation circuit for generating a mask signal in at least a part of a region before the region, and a mask circuit for setting the burst signal to a non-signal state when the mask signal is generated in the mask signal generation circuit And a main device used in the transmission system. 3. The main apparatus used in the transmission system according to claim 1, wherein said discriminating means comprises: a bit synchronization circuit for extracting a clock synchronized with the burst signal from the burst signal; A head synchronization circuit for identifying the head of the data of the burst signal in accordance with the extracted clock; and information indicating the head position of the data identified by the head synchronization circuit, for each of the plurality of other devices. Holding means for holding in correspondence with the identification information of the above, wherein the suppressing means uses a phase according to information indicating a head position of data held in the holding means, instead of the predetermined phase. A main device used in a transmission system characterized by the above-mentioned. 4. A transmission system for performing communication between a main device and a plurality of other devices, receiving a burst signal transmitted at a predetermined phase from the plurality of other devices,
A synchronization circuit in the main device that generates a reset signal every time the burst signal is received, wherein the bit synchronization circuit extracts a clock synchronized with the burst signal from the burst signal. A start synchronization circuit for identifying the start of the data of the burst signal in accordance with the clock, and from the generation of the reset signal until the area for the bit synchronization detection of the next burst signal, which is determined by the phase. At least a part of the synchronous circuit, comprising: a suppression means for suppressing extraction of a clock by the bit synchronization circuit. 5. A transmission system for communicating between a main device and a plurality of other devices, receiving a burst signal transmitted at a predetermined phase from the plurality of other devices,
A clock synchronization method in a main device for generating a reset signal every time the reception of the burst signal is completed, the method comprising: determining a bit synchronization of a next burst signal determined from the phase from the generation of the reset signal. In a second period other than the first period before the region, a clock synchronized with the burst signal is extracted from the burst signal, and according to the extracted clock,
A clock synchronization method characterized by identifying a head of data of the burst signal.