JPH10327051A - Balanced clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a balanced clock generating circuit that converts an unbalanced clock signal into a balanced clock signal to generate a waveform-shaped clock signal in a short time. SOLUTION: In this circuit, a non-polar capacitor 1 is inserted between an unbalanced clock signal input terminal 5 and a balanced clock signal output terminal 6, and a resistor 2 and a series circuit consisting of series connection of a resistor 3 and a switching transistor(TR) 4 are connected in parallel between the balanced clock signal output terminal 6 and the non-polar capacitor 1 and the circuit is provided with a control means that controls a voltage of the unbalanced clock signal input terminal 5 and a state of the switching TR 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a balanced clock generation circuit for generating a balanced clock signal from an unbalanced clock signal.

[0002]

2. Description of the Related Art Conventionally, an unbalanced clock signal has been transmitted to an RS-42.
In order to output data to a balanced interface such as the one shown in FIG. 3, an insulating circuit or a dedicated driver is generally used. However, since these methods increase the cost, a circuit using a differentiating circuit as shown in FIG. It is used to generate a balanced clock signal at low cost. In FIG. 3, reference numeral 100 denotes a nonpolar capacitor such as a ceramic capacitor, 101 denotes a resistor, 102 denotes an unbalanced clock signal input terminal, and 103 denotes a balanced clock signal output terminal.

The unbalanced clock signal input terminal 102 shown in FIG.
Input an unbalanced clock signal as shown in FIG.
A balanced clock signal as shown in FIG. 5 is output to a balanced clock output signal terminal 103.

[0004]

However, the conventional balanced clock generation circuit as shown in FIG. 3 has a problem that it takes a long time from the input of the unbalanced clock signal to the output of the balanced clock signal. there were.

The above problem will be described with reference to FIG. The voltage of the unbalanced clock signal input terminal 102 is 0 V before the unbalanced clock signal is input. When the input of the unbalanced clock signal is started, an unbalanced clock signal having a frequency of 1 MHz and a voltage between +5 V and 0 V is input to the unbalanced clock signal input terminal 102. At this time, the capacity of the nonpolar capacitor 100 is 0.47 μF,
1 has a resistance value of 680Ω. As can be seen from FIG.
About 400 μsec is required until a balanced clock signal of +2.5 V to −2.5 V is output.

It is known that, for example, the capacity of the non-polar capacitor 100 can be reduced in order to shorten the time until the output of the balanced clock signal. The clock signal waveform is distorted. FIG. 7 is a diagram showing an output waveform when the capacitance of the nonpolar capacitor 100 is set to 0.01 μF. As can be seen from FIG. 7, the time until the output of the balanced clock signal is shortened (about 20 μsec).
c), the balanced clock signal waveform is distorted as shown in FIG.

Therefore, it takes a certain amount of time after the input of the unbalanced clock signal to obtain a square-wave balanced clock waveform with the conventional balanced clock generation circuit as shown in FIG.

If the balanced clock signal is always output, the above-mentioned time is irrelevant, but wasteful power is consumed, which is not effective for a battery or a device which requires low power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a balanced clock generation circuit capable of generating a balanced clock signal having a uniform waveform in a reduced time. Aim.

[0010]

The balanced clock generating circuit of the present invention is constructed as follows.

(1) In a balanced clock generation circuit for converting an unbalanced clock signal into a balanced clock signal, a capacitor is provided between an input terminal for inputting the unbalanced clock signal and an output terminal for outputting the balanced clock signal. A resistor between the output terminal and the capacitor;
A control means for connecting a series circuit in which a resistor and a switch element are connected in series and for controlling a voltage of the input terminal and a state of the switch element is provided.

(2) In the balanced clock generation circuit of (1), the control means keeps the input terminal at the power supply voltage level for a certain period of time and makes the switch element conductive, and after a certain time, makes the switch element non-conductive; An unbalanced clock signal is input to the input terminal.

[0013]

FIG. 1 is a circuit diagram showing a configuration of a balanced clock generation circuit according to the present invention.

In FIG. 1, 1 is a non-polar capacitor such as a ceramic capacitor, 2 and 3 are resistors, 4 is a switching transistor, 5 is an unbalanced clock signal input terminal for inputting an unbalanced clock signal, and 6 is a balanced clock signal. Is a balanced clock signal output terminal from which is output, and 7 is a control terminal for sending a control signal for controlling the state of the switching transistor.

The operation of the circuit will be described below with reference to FIG.

Before inputting an unbalanced clock signal for generating a balanced clock signal, the control terminal 7 is activated and the switching transistor 4 is turned on. When the switching transistor 4 is turned on and turned on, the resistor 3 is grounded. Then, the voltage V is applied to the unbalanced clock signal input terminal 5. When voltage is applied, non-polar capacitor 1
Is charged by a time constant determined by the resistances of the resistors 2 and 3 and the nonpolar capacitor 1 through the resistors 2 and 3.

When the voltage between both ends of the non-polar capacitor 1 becomes V / 2 after the voltage is applied to the unbalanced clock signal input terminal 5, the control terminal 7 is made inactive and the switching transistor 4 is turned off. At the same time, an unbalanced clock signal is input to the unbalanced clock signal input terminal 5. As a result, the balanced clock signal is output to the balanced clock output terminal 6 simultaneously with the input of the unbalanced clock signal.

FIGS. 2A and 2B are waveform diagrams showing input / output states in the circuit of FIG. 1. FIG. 2A shows an input waveform, and FIG. 2B shows an output waveform.

The operation described above will be described with reference to FIG. In this embodiment, the capacity of the nonpolar capacitor 1 is 0.4
The resistance value of the resistor 2 is 680Ω, and the resistance value of the resistor 3 is 10Ω. The balanced clock signal was output about 4 μsec after the start of the operation, and it can be confirmed that the time until the output of the balanced clock signal is significantly reduced as compared with FIG.

As described above, in the present embodiment, the non-polar capacitor 1 is interposed between the unbalanced clock signal input terminal 5 and the balanced clock signal output terminal 6, and the balanced clock signal output terminal 6 and the non-polar capacitor 1 , A resistor 2 and a series circuit connected in series with the resistor 3 and the switch transistor 4 are connected in parallel, and the voltage of the unbalanced clock signal input terminal 5 and the state of the switch transistor 4 are controlled. At the start of generation of the balanced clock signal, the voltage of the unbalanced clock signal input terminal 5 is maintained at the power supply voltage level for a certain period of time, and the switching transistor 4 is turned on by the control signal. The switching transistor 4 is turned off by a signal, and an unbalanced clock signal is input. Therefore, it is possible to generate a balanced clock signal with a uniform waveform in a reduced time.

[0021]

As described above, according to the present invention,
In a balanced clock generation circuit for converting an unbalanced clock signal into a balanced clock signal, a capacitor is interposed between an input terminal for inputting the unbalanced clock signal and an output terminal for outputting the balanced clock signal, and an output terminal Between the capacitor, a resistor and a series circuit in which the resistor and the switch element are connected in series are connected in parallel, and the control means for controlling the voltage of the input terminal and the state of the switch element is provided, so that the waveform is adjusted. There is an effect that a balanced clock signal can be generated in a reduced time.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a balanced clock generation circuit according to the present invention.

FIG. 2 is a waveform chart showing an input / output state in the circuit of FIG.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a waveform diagram showing an unbalanced clock signal input to the input terminal of FIG.

5 is a waveform diagram showing an ideal balanced clock signal output to an output terminal when input to the input terminal of FIG. 10;

FIG. 6 is a diagram showing a time until a balanced clock signal is output to an output terminal in FIG. 10;

FIG. 7 is a diagram showing a time until a balanced clock signal is output to an output terminal when the capacitance of the capacitor in FIG. 10 is reduced.

8 is a waveform diagram showing a balanced clock signal output to an output terminal when the capacitance of the capacitor in FIG. 10 is reduced.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Non-polar capacitor 2 Resistance 3 Resistance 4 Switching transistor 5 Unbalanced clock signal input terminal 6 Balanced clock signal output terminal 7 Control terminal

Claims (2)

[Claims] 1. A balanced clock generation circuit for converting an unbalanced clock signal into a balanced clock signal, wherein a capacitor is interposed between an input terminal for inputting the unbalanced clock signal and an output terminal for outputting the balanced clock signal. Control means for connecting in parallel a resistor and a series circuit in which a resistor and a switch element are connected in series between the output terminal and the capacitor, and controlling a voltage of the input terminal and a state of the switch element; A balanced clock generation circuit comprising: 2. The control device according to claim 1, wherein the input terminal is kept at the power supply voltage level for a certain period of time, and the switch element is made conductive. The balanced clock generation circuit according to claim 1, wherein: