JPH1032438A - Current mirror circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce deviation from the mirror current of a current mirror circuit by Darlington-connecting an NPN transistor to each PNP transistor(TR) constituting the current mirror circuit so as to remarkably reduce the base current of the NPN transistor. SOLUTION: NPN TRs Q11 and Q21 are respectively Darlington-connected to respective PNP TRs Q1 and Q2 constituting a current mirror circuit. The calculation of a constant current IR in this circuit and a current IL flowing on the load side are conventionally calculated as shown in expressions I and II respective. IE1 and IE2 are respectively current values flowing in resistors R1 and R2 and βN and βP are respectively the current amplification factors of NPN and PNP TRs. The value of |IR-IL| is given by expression III. When calculated by setting βN=200 and βL=50 as general numerical values for βN and βP, |IR-IL| is given by expression IV. Consequently, the expression IV gives 0.02% of IE2 to be not more than a current mirror circuit calculating value to reduce the deviation between the constant current and the current flowing on the loading side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current mirror circuit on an integrated circuit, and more particularly to a current mirror circuit using a lateral type PNP transistor having a low current amplification factor, the accuracy of a current ratio between a reference current and a mirror current. It is about improving.

[0002]

2. Description of the Related Art In a current mirror circuit using PNP transistors in an integrated circuit, the simplest example is shown in FIG. 2, and a so-called Wilson type example in which the accuracy of the mirror current is improved is shown in FIG.

[0003] These circuits when flowing a constant current I _R in to Q ₁ of the pair of transistors Q _1, Q ₂ in which the base in common emitter voltage for Q ₁ caused by the voltage drop across the resistor R ₁ V _E1 equal voltage, the current I _L flows through the load L so as to generate as an emitter voltage V _E2 Q ₂ 'caused by the voltage drop across the resistor R ₂ (= V _E1), if wherein the R ₁ = R ₂ The current I _L flowing from Q ₂ to the load L is configured to be equal to I _R.

When these current mirror circuits are formed on a general integrated circuit, the PNP transistor has a lateral structure having a current amplification factor β _P lower than 1/2 that of an NPN transistor having a vertical structure. Are often used, and in this case, the base current of the PNP transistor necessarily increases. The deviation between the current I _L and the constant current I _R flowing into the load side by the effect shown for 2, 3. However, PNP,
The current amplification factors β _P and β _N of the NPN transistor are each constant. Emitter currents I _E1, I _E2 of FIG. 2 the current I _L flowing in the load and the constant current I _R transistors Q _1, Q _2, if indicated by the base current I _B1, I _B2 and current amplification factor beta _P, FIG. 2
From

[0005]

(Equation 1)

Equation (1)

[0007]

(Equation 2)

Equation (2) is obtained, and if the resistances R ₁ and R ₂ are equal, the emitter voltages V _E1 and V _E2 of the transistors Q _{1 and} Q ₂ are V _E1 = V _E2 and therefore I _E1 = I _E2. . as a result,
Deviation between the current I _L flowing in the load and the constant current I _R, i.e. the difference

[0009]

(Equation 3)

It is expressed by equation (3). Also, when calculating the current I _L and the difference flows in the same manner as the load and the constant current I _R also FIG. 3, since the new transistor Q ₃ is applied, from FIG. 3, I _R is

[0011]

(Equation 4)

Equation (4) Also, I _L is given by equation (5)

[0013]

(Equation 5)

As a result, I _R -I _L is given by the formula (6)

[0015]

(Equation 6)

## EQU1 ##

When the difference between the constant current I _R and the current I _L flowing into the load is calculated by specifically entering numerical values, the PNP transistor has a low current amplification factor β _P and β _P = 50. , Equation (7)

[0018]

(Equation 7)

Approximately 4% of _IE2 . Also, in the case of FIG.

[0020]

(Equation 8)

The next, it can be seen that approximately 0.08% of I _E2.

[0022]

In the current mirror circuits shown in FIGS. 2 and 3, when a lateral type having a low current amplification factor is used for the PNP transistor, the difference between the constant current and the current flowing into the load side is reduced. It cannot be avoided that much, and even the considerably improved Wilson-type circuit example of FIG. 3 may be insufficient when it is desired to suppress the deviation as much as possible. Further, in the case of a lateral PNP transistor, the current amplification factor is particularly susceptible to manufacturing lot variation on an integrated circuit, and may fluctuate by 1/2 to 2 times. In the numerical calculation examples shown in FIGS. 2 and 3, if the current amplification factor of the PNP transistor is reduced by half, the difference between the constant current and the current flowing into the load side is further increased.

An object of the present invention is to minimize the difference between the above-described constant current and the current flowing to the load side in a current mirror circuit using a lateral PNP transistor.

[0024]

According to the present invention, in order to achieve the above object, in a current mirror circuit of PNP transistors, an NPN transistor is connected to each of the reference side and load side PNP transistors by Darlington connection.

The operation of the present invention will be described. In general, the difference between the reference constant current and the current flowing into the load side in the current mirror circuit is almost entirely due to the base current of the transistor forming the current mirror circuit. Therefore, if the base current is reduced, the above-described current deviation is reduced as it is.

In the present invention, in order to achieve the above object,
An NPN transistor is Darlington-connected to each PNP transistor constituting the current mirror circuit. As a result, the current amplification factor of the PNP transistor is substantially increased by multiplying the current amplification factor of the NPN transistor, and the base current of the PNP transistor is greatly reduced. The difference between the current and the current flowing to the load side can be reduced. In the case of a general integrated circuit, NP
The N transistor has a higher current amplification factor than the PNP transistor (lateral type), and the PNP of the current mirror circuit
The effect of increasing the current amplification factor by Darlington connection to the transistor is greater.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. As described above, in the circuit of FIG. 1, NPN transistors Q ₁₁ and Q ₂₁ are respectively connected to the PNP transistors Q _{1 and} Q ₂ constituting the current mirror circuit by Darlington connection. Figure 2 a current I _L which the constant current I _R in the circuits flow into the load side, if calculated as in the conventional example of FIG. 3 (9) and (10).

[0028]

(Equation 9)

[0029]

(Equation 10)

Therefore, I _R -I _L is given by equation (11).

[0031]

[Equation 11]

## EQU1 ## Here, the current amplification factors β _N and β _P of the NPN and PNP transistors are given as general values β _N
= 200, β _P = 50,

[0033]

(Equation 12)

In the equation (12), 0.02% of I _E2 is obtained.
The difference between the above constant current and the current flowing into the load can be reduced below the calculated value of the Wilson-type current mirror circuit in FIG.

[0035]

As described above, according to the present invention, P
In the current mirror circuit of the NP transistor, the base current of the PNP transistor that generates the reference constant current can be reduced.

As a result, the difference between the reference constant current and the current flowing into the load side is reduced, so that the current ratio accuracy of the mirror current of the current mirror circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a current mirror circuit using a PNP transistor according to the present invention.

FIG. 2 is a circuit diagram showing an example of a current mirror circuit using a PNP transistor according to a conventional example.

FIG. 3 is a circuit diagram showing an example of a current mirror circuit using a PNP transistor according to a conventional example.

[Explanation of symbols]

Q ₁ , Q ₂ , Q ₃ : PNP transistor (lateral type), Q
₁₁ , Q ₂₁ : NPN transistor, R ₁ , R _2, R ₃ : resistor,
L: load, V _CC : power supply, V _E1 , V _E2 : transistor emitter voltage.

Claims (2)

[Claims] A load connected to a collector of another transistor by connecting a base and a collector of one transistor and flowing a constant current between an emitter and a collector. A current mirror circuit in which a mirror current substantially equal to the constant current flows through the pair of transistors, wherein each of the second and third transistors is Darlington-connected. 2. The current mirror circuit according to claim 1, wherein NPN transistors are used as the second and third transistors.