JPH1032276A - Packaging method of power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of packaging a power semiconductor device, wherein weld splash is prevented from penetrating into a cavity to deteriorate the device in product characteristics. SOLUTION: A weld splash stopper (conical projection) 3 is provided at a prescribed position inside a welding metal 11 located on the outer periphery of a DO stud 1 (or TO header), the flange (rind projection) 9 of a metal cap 7 is pressed down on the above welding metal 11, and metal hermetic seal is carried out by electric resistance welding. The stopper 3 is provided, whereby weld splash is completely and structually prevented from penetrating into a cavity to deteriorate a power semiconductor device in product characteristics, so that a PIND test and a resin cap can be dispensed with.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for packaging a power semiconductor device, and more particularly to a method for packaging DO-4, TO-
DO with a die mount terrace at the center of 3 etc.
The present invention relates to a metal hermetic sealing method for a power semiconductor device using a package or a TO package.

[0002]

2. Description of the Related Art An example of a conventional power semiconductor device packaging method (hereinafter referred to as "conventional method 1") will be described with reference to FIGS. FIG. 6 is a cross-sectional view of a metal hermetic seal structure showing the conventional method 1, and FIG. 7 is an enlarged partial detailed view of a portion A in FIG. 6 before welding.

In the conventional method 1, as shown in FIGS. 6 and 7,
DO stud 1 with die mount terrace 2 in the center
The DO stud 1 surrounding the die mount terrace 2 and provided with the weld metal portion 11 corresponding to the joint portion of the flange 9 of the metal cap 7 is used.

[0006] As shown in FIG. 6, a semiconductor chip 5 is die-mounted on the die mount terrace 2 via a Mo plate 4, and wiring by wire-bonding 6 is performed. Subsequently, as shown in FIG. 7, a metal cap 7 having a flange 9 and a projection 10 (for performing welding joining with the welding metal portion 11) is attached, and the metal cap 7 is formed using an electric resistance welding machine. 7 and the weld metal portion 11 of the DO stud 1 are press-pressed, and the projection 10 of the flange 9 is formed by electric welding.
And sealing is performed. Thereafter, the packaging method is to remove products having a weld splash that has entered the interior of the cavity by a PIND test (see FIG. 10A).

The conventional method 1 will be further described with reference to FIG. FIG. 10A is a view showing a manufacturing flow in the packaging method of the conventional method 1.
In the conventional method 1, as shown in FIG.
The flow consists of "wire-bonding" → "cap attachment" → "sealing" → "PIND test" → "cleaning and drying" → "characteristic check".

In addition to the conventional method 1, for example, Japanese Utility Model Application Laid-Open No. 4-10954
The TO package method disclosed in Japanese Patent Publication No. 0 (hereinafter referred to as "conventional method 2") is also known. The conventional method 2 will be described with reference to FIGS. FIG. 8 is a sectional view of a seal structure showing the conventional method 2, and FIG.
It is an enlarged detail view of B part in a middle.

In the conventional method 2, as shown in FIGS. 8 and 9, a resin cap 19 that fits inside the metal cap 7 is covered by covering the upper surface of the semiconductor chip 5 of the wire-bonded TO header 18 as shown in FIG. To wear. Subsequently, a packaging method is used in which a metal cap 7 is attached and the peripheral portion of the TO header 18 and the flange 9 of the metal cap 7 are joined and sealed.

The second conventional method will be further described with reference to FIG. FIG. 11A is a view showing a manufacturing flow in the packaging method of the conventional method 2.
In the conventional method 2, as shown in FIG.
"Wire-bonding" → "Resin cap attached" →
It consists of a flow of "bake" → "metal cap attachment" → "sealing" → "characteristic check".

[0009]

By the way, in the above-mentioned prior art, for example, in the above-mentioned conventional method 1, "a work process related to a PIND test [see FIG. 10 (A)]" is required. 2 requires a “resin cap attaching work process [see FIG. 11 (A)]”, and all have various problems including an increase in manufacturing cost accompanying these work processes (man-hours).

That is, in the conventional method 1, a metal cap is directly attached and sealed, and it is impossible to prevent “weld splash from scattering into the inside of the cavity” during the sealing. Implementation is essential. Further, in the conventional method 2, the “weld splash intrusion” of the conventional method 1 is prevented by attaching with a resin cap. Therefore, the cost of the resin cap and the attachment of the resin cap are reduced. There is a problem that a work process is required.

Further, the conventional method 2 has a problem that it cannot be applied to a DO package or a highly reliable product. The reason is that in the DO package, an extraction electrode that penetrates the metal package upward from the upper electrode surface of the semiconductor chip is necessary, and it is difficult to attach a resin cap, and a highly reliable product is required. In this case, it is impossible to use an organic substance inside the metal cavity for reliability.

The present invention has been made in view of the above problems of the prior art (conventional methods 1 and 2), and an object of the present invention is to eliminate the problems. That is, an object of the present invention is to provide a method of packaging a power semiconductor device for preventing "weld splash from entering a cavity" which may hinder product characteristics.
It does not require the attachment of a resin cap, and does not require the removal of a product having a weld splash by a PIND test, so that the manufacturing cost is low and the DO package, the TO package, and the It is an object of the present invention to provide a packaging method applicable to high reliability products.

[0013]

In order to achieve the above object, the present invention has the following objects: A weld splash stopper is provided at a predetermined position inside a weld metal portion on the outer periphery of a DO stud or a TO header.
DO stud or TO header with (convex protrusion) formed
The method is characterized in that the welding metal portion and the flange portion (ring projection) of the metal cap are pressurized and metal hermetic sealing is performed by electric resistance welding.

That is, the present invention relates to a power semiconductor DO package or TO package DO stud or TO package.
A DO stud or a TO header in which a weld metal portion is formed on an outer peripheral portion of a header and a weld splash stopper is formed inside the weld metal portion, and is attached to the DO stud or the TO header. Using a DO stud or a TO header in which the stopper is formed at a position where the minimum distance between the flange arc of the metal cap and the outer tapered surface of the stopper is smaller than the minimum dimension between the electrodes of the die chip, A packaging method for a power semiconductor device, comprising: pressing a weld metal portion and a flange portion of a metal cap to perform a metal hermetic seal by welding. (Claim 1).

[0015]

According to the packaging method of the present invention, a "weld splash stopper" is provided at a weld metal portion of a DO stud or a TO header, that is, a "metal cap" to be joined to the above weld metal portion. Since a “weld splash stopper” is provided between the “projection provided on the flange portion” and the “daiterasu mount”, the “weld splash” generated at the time of resistance welding is scattered into the cavity by the stopper. Since the distance between the flange arc of the metal cap and the outer peripheral surface of the stopper is smaller than the minimum dimension between the electrodes of the die chip, the "weld splash" larger than the minimum dimension between the electrodes of the die chip is caused in the cavity. The effect of blocking intrusion into the die terrace mount is produced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a packaging method according to the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a packaging method according to the present invention.
As shown in FIG. 3, specifically, a weld metal portion 11 provided on the outer peripheral portion of the DO stud 1 (or the TO header) is provided.
A convex projection having a height of about 0.1 to 2.5 mm as a weld splash stopper -4 is formed inside the DO stud 1 (or the TO header-). Outer peripheral tape of stopper-4
The DO stud 1 (or TO header) is formed at a position where the maximum distance from the die surface 12 (taper angle 2 to 30 degrees) is smaller than the minimum dimension (10 to 200 μm) between the electrodes of the die chip. And metal hermetic sealing by electric resistance welding. The stopper-4 has a function as a weld splash stopper.

1 to 3 show an embodiment of the present invention.
This will be described in more detail with reference to FIG. As shown in FIG.
The O stud 1 is provided with a weld splash stopper -3 on the outer periphery of the die mount terrace 2. This D
A structure in which a Mo plate 4 is spread on a die mount terrace 2 of an O stud 1, a semiconductor chip 5 is die-mounted, wire bonding 6 is performed, a metal cap 7 is applied, and a pinch weld is further performed to form a lead electrode 8. It has become.

Next, a description will be given with reference to FIG. FIG. 2 is an enlarged detailed view of a portion A in FIG. 1 and is an enlarged partial detailed view when a cap is attached before sealing. As shown in FIG. 2, around the die mount terrace 2 of the DO stud 1 and the Mo plate 4, and inside the weld metal part 11 to which the projection 10 provided on the flange 9 of the metal cap 7 is joined. A weld splash stopper-3 (hereinafter simply referred to as "stopper-3") is formed. A taper process is applied to the outer peripheral portion of the stopper 3 to form a stopper taper surface 12, and a distance from the flange arc 13 on the inner surface of the cap is formed at the time of sealing with the metal cap 7. It has a structure that is only small.

The stopper 3 is provided on the same surface as the die mount terrace 2 (hereinafter simply referred to as "terrace 2") and the weld metal portion 11. Can be easily processed only by changing the above, and the cost is almost the same as the conventional DO stud.

Next, the operation of the embodiment of the present invention will be described.
This will be described with reference to FIG. FIG. 3 is an enlarged detailed view of the portion A in FIG. 1 and is an enlarged partial detailed view after sealing. As shown in FIG. 3, the ideal fitting of the DO stud 1 and the metal cap 7 is such that the inner wall surface 14 of the cap is a stopper.
The sealing is performed in a state in which the outer periphery of the taper processing starting point 15 of FIG. 3 coincides with the outer circumference of the taper processing start point 15. Becomes

Considering the occurrence of weld splash at the time of sealing, when the flange 9 of the metal cap 7 and the weld metal portion 11 of the DO stud 1 are brought into contact with each other, press-pressing is performed using an electric resistance welding machine. At the same time as the provided projection 10 (see FIG. 2) is crushed, a predetermined voltage is applied to this portion, a welding current is applied to melt the projection 10, and the outer peripheral side of the flange 9 and the weld metal 11 are joined.

At this time, the crushed state of the projection 10 does not become constant, and over-melting occurs partially in the joint melting portion 16 transiently, and the weld splash 17 scatters. The weld splash 17 is blocked by the stopper 3, and is confined in a gap between the stopper taper surface 12 and the welded portion 16. Further, in the mechanical stress during manufacturing, inspection, and actual use after sealing, “penetration of weld splash into cavity” toward die mount terrace 2 on which semiconductor chip 5 is mounted.
Is prevented by the minimum distance "a" between the stopper taper surface 12 of the stopper 3 and the flange arc 13.

Here, referring to FIGS. 10A and 10B,
The production flow of the conventional method 1 and the method of the present invention will be described in comparison. FIG. 10A is a diagram illustrating a manufacturing flow according to the conventional method 1, and FIG. 10B is a diagram illustrating a manufacturing flow according to the method of the present invention in comparison with the conventional method 1.

In the conventional method 1, as shown in FIG.
“Chip mount” → “Wire-bonding” → “Cap attachment” → “Sealing” → “PIND test” → “Cleaning,
It consists of the flow of "dry" → "characteristic check". On the other hand, in the method according to the present invention, as shown in FIG. 10B, the step of “PIN test” → “washing and drying” in the conventional method 1 can be omitted. .

Referring to FIGS. 11 (A) and 11 (B), the manufacturing flow of the conventional method 2 and the method of the present invention will be described in comparison. FIG. 11A is a diagram showing a manufacturing flow according to the conventional method 2, and FIG. 11B is a diagram showing a manufacturing flow according to the method of the present invention in comparison with the conventional method 2.

In the conventional method 2, as shown in FIG.
"Chip mount" → "Wire-bonding" → "Resin cap attached" → "Bake" → "Metal cap attached"
→ "Seal" → "Characteristic Check"
On the other hand, in the method according to the present invention, as shown in FIG. 11 (B), the process of "attaching a resin cap" → "bake" in the above-mentioned conventional method 2 is not involved.

[0028]

Next, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiments and does not depart from the gist of the present invention. Various changes and modifications are possible.

(Embodiment 1: First Embodiment of the Present Invention) FIG. 1 shows a DO-4 type package structure of a power diode according to a first embodiment (Example 1) of the present invention. FIG. 2 and 3 are enlarged detailed views of a portion A in FIG. 1. FIG. 2 is an enlarged partial detailed view before sealing, and FIG. 3 is an enlarged partial detailed view after sealing.

In the first embodiment, the material of the DO stud 1 is manufactured by pressing or cutting each of the die mount terrace 2, the stopper 3, and the mounting screw 20 also serving as an electrode from a copper material. A welding metal 11 is formed on the material of the DO stud 1 by using cup nickel having a higher electric resistance than copper for resistance welding.
Mo board 4 whose thermal expansion coefficient is close to that of semiconductor chip 5 made of material
Is stuck on a die mount terrace 2 with a silver braze or the like to produce a DO stud (a stud for DO-14) 1.

Using the obtained DO stud 1, the semiconductor chip 5 is mounted on the upper surface of the Mo plate 4 using a solder such as AgPbSn. Next, the upper electrode (lead electrode 8) of the semiconductor chip 5 is bonded to the upper electrode (lead electrode 8) with an Al wire or the like.
Wiring.

After that, as shown in FIG. 2, the metal cap 7 is attached so that the flange 9 and the projection 10 thereof coincide with the position of the weld metal 11 provided on the outer peripheral portion of the stopper-3. Subsequently, a predetermined press pressure is applied to the flange 9 and the weld metal 11 by an electric resistance welding machine, and a predetermined voltage is applied at the same time as the projection 10 is crushed. Is melted, and the DO stud 1 and the metal cap 7 are hermetically sealed.

The stopper 3 according to the first embodiment is formed as follows. That is, as shown in FIG. 3, the inner wall surface 14 of the metal cap 7 and the outer peripheral taper starting point 15 of the stopper 3 coincide with the outer periphery of the die mount terrace 2 of the DO stud 1 in the vertical direction. The maximum distance “a” between the flange arc 13 of the metal cap 7 and the stopper-taper surface 12 is smaller than the minimum distance “b” between the electrodes of the semiconductor chip 5 (power semiconductor chip 20 to 400 μm). To reduce the size, height is about 0.1 to 2.5 mm, taper angle is 2 to 3
The stopper 3 is formed by providing a convex protrusion having a dimension of 10 to 100 μm at the maximum distance “a” of 0 °.

Next, the function of the first embodiment will be described in detail with reference to FIG. Referring to FIG. 3, the taper surface 12 of the stopper 3 and the flange arc 1 of the metal cap 7 are shown.
3 so that the maximum distance “a” (10 to 100 μm) with respect to 3 is smaller than the minimum dimension “b” (20 to 400 μm) between chip electrodes.
Since the inner wall surface 14 of the metal cap 7 and the taper surface 12 of the stopper 3 are fitted and sealed, a weld splash larger than the maximum distance "a" generated at the time of electric resistance welding is generated. 17 is prevented from entering the interior of the cavity.

If the taper angle of the stopper 3 is less than 2 degrees, the fitting tolerance of the metal cap 7 is so severe that it becomes difficult to attach the metal cap 7 by an automatic machine. Conversely, if the angle is larger than 30 degrees, It is not preferable because the width of the stopper 3 becomes large and the package dimension becomes large.

(Embodiment 2: Second Embodiment of the Present Invention) FIG. 4 shows a TO-3 type packaging structure of a power transistor according to a second embodiment (Example 2) of the present invention. FIG. 5 is a cross-sectional view, and FIG. 5 is an enlarged detailed view of a portion B (welded portion) in FIG.

In the second embodiment, as shown in FIGS. 4 and 5, on the surface of the die mount terrace 2 of the header 18 for the TO-3, the outer periphery surrounding the semiconductor chip 5 and the wire-bonding 6 is formed. , Stopper-3. Using the TO-18 header 18, the semiconductor chip 5 is mounted at the center with a solder such as AgPbSn, and then the wiring between the upper electrode and the lead electrode 8 of the semiconductor chip 5 is performed by wire bonding 6, and , Metal cap 7
And hermetically sealed by electric resistance welding.

The function of the second embodiment is the same as that of the first embodiment. That is, as shown in FIG. 5, the stopper-3 is provided between the flange 9 of the metal cap 7 and the header-1.
8 has a function of preventing weld splash generated by electric resistance welding with the inside 8 from entering the inside of the cavity.

[0039]

As described in detail above, the present invention has the following advantages: a weld splash stopper is provided at a predetermined position inside the weld metal portion on the outer periphery of the DO stud or the TO header.
Using a DO stud (or a TO header) with (convex protrusions) formed, pressurize the welding metal part and the flange part (ring projection) of the metal cap, and form a metal hermetic seal by electric resistance welding. And thus, the “P” which has been performed in the conventional packaging.
The "IND test-related work (refer to the conventional method 1)" becomes unnecessary, and the "resin cap attachment (refer to the conventional method 2)" becomes unnecessary, thereby producing an effect of reducing the manufacturing cost. This is because the provision of the weld splash stopper completely prevents the weld splash, which is an obstacle to the product characteristics, from entering the interior of the cavity due to the design structure, so that the PIND test and the attachment of the resin cap are not required.

Further, according to the present invention, the present invention can be applied to a DO package and a highly reliable product. Therefore, it is possible to take measures against a weld splash on a packaging structure for a wide range of products. The following effects occur. The reason is that the weld splash stopper according to the present invention is provided around the flange in the package. In addition, since it is formed of a stud or a header-base material, there is no restriction on the package structure and product use.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a DO-4 type package structure of a power diode according to a first embodiment (Example 1) of the present invention.

FIG. 2 is an enlarged detailed view of a portion A in FIG. 1 and is an enlarged partial detailed view before sealing.

FIG. 3 is an enlarged detailed view of a portion A in FIG. 1 and is an enlarged partial detailed view after sealing.

FIG. 4 is a sectional view showing a TO-3 type packaging structure of a power transistor according to a second embodiment (Example 2) of the present invention.

FIG. 5 is an enlarged detailed view of a portion B (welded portion) in FIG. 4;

FIG. 6 is a sectional view of a metal hermetic seal structure showing a conventional method 1.

FIG. 7 is an enlarged partial detailed view of a portion A in FIG. 6 before welding.

FIG. 8 is a sectional view of a seal structure showing a conventional method 2.

FIG. 9 is an enlarged detailed view of a portion B in FIG. 8;

FIG. 10 is a diagram showing a comparison between the production flow of the conventional method 1 and the method of the present invention, in which (A) is a diagram showing the production flow by the conventional method 1, and (B). This conventional method 1
FIG. 3 is a diagram showing a manufacturing flow of the method of the present invention in comparison with FIG.

11 is a diagram showing the production flow of the conventional method 2 and the method of the present invention in comparison, in which (A) is a diagram showing the production flow by the conventional method 2, and (B) This conventional method 2
FIG. 3 is a diagram showing a manufacturing flow of the method of the present invention in comparison with FIG.

[Explanation of symbols]

 Reference Signs List 1 DO stud 2 Die mount terrace 3 Weld splash stopper 4 Mo plate 5 Semiconductor chip 6 Wire bonding 7 Metal cap 8 Lead electrode 9 Flange 10 Projection 11 Weld metal part 12 Stopper taper surface 13 Flange arc 14 Inside metal cap Wall 15 Starting point of taper processing 16 Joint fusion part 17 Weld splash 18 TO header 19 Resin cap 20 Screw

Claims (3)

[Claims] A DO package or TO for a power semiconductor.
A DO stud or a TO header in which a weld metal portion is formed on an outer peripheral portion of a DO stud or a TO header of a package and a weld splash stopper is formed inside the weld metal portion, wherein the DO stud is provided. Alternatively, a DO stud formed with the stopper at a position where the minimum distance between the flange arc of the metal cap attached to the TO header and the outer peripheral taper surface of the stopper is smaller than the minimum dimension between the electrodes of the die chip. Alternatively, a method for packaging a power semiconductor device, comprising pressing a welded metal portion and a flange portion of a metal cap using a TO header and performing metal hermetic sealing by welding. 2. The packaging method for a power semiconductor device according to claim 1, wherein the taper angle of the outer peripheral surface of the weld splash stopper is 2 to 30 degrees. . 3. The weld splash stopper according to claim 1, wherein a distance between an outer peripheral taper surface of the stopper and a flange arc surface of the metal cap is 10 to 100 μm. A packaging method for a power semiconductor device.