JPH10322712A - Digital convergence device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform optimum digital convergence correction by linearly interpolating a vertical target value data string and eliminating the inclination non- continuity of the result by using a digital filter provided with a variable filter constant. SOLUTION: Data linearly interpolated in a linear interpolation circuit 12 are inputted to the digital filter 13 and an optimum filter constant corresponding to a vertical line number is multiplied with the result of a full adder in a multiplier. By storing the one for which the filter constant is multiplied with the difference value of input from the linear interpolation circuit 12 and the output of the digital filter 13 in an accumulator for each timing clock, the value of the output of the digital filter 13 gradually approaches the value of the input from the linear interpolation circuit 12, and even when a non-continuous part is present in the inclination of an input waveform linearly interpolated in the linear interpolation circuit 12, the output of the digital filter 13 is made continuous by the action of the accumulator. It is sent to a horizontal processing circuit 2 and the digital convergence is corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an apparatus for performing digital convergence correction in a vertical deflection direction of a display monitor using a CRT (CRT).

[0002]

2. Description of the Related Art FIG. 4 shows a conventional digital convergence device. In FIG. 4, vertical waveform generating circuits 21-1, 21-2 to 21-n generate digital convergence correction waveforms in the vertical direction, and have the same functions.

The horizontal processing circuit 22 performs digital convergence correction in the horizontal deflection direction in which the correction waveform in the vertical direction is switched at an arbitrary position of the horizontal deflection in a time division manner. Digital/
The analog (D / A) converter 23 converts the digital signal subjected to the digital convergence correction into an analog signal. Then, the analog signal is sent to the convergence coil 25 of the CRT 24, and digital convergence is performed in the CRT 24.

Each vertical waveform generating circuit 21 includes a vertical target value data string memory 26 for storing an amount to be corrected in the vertical deflection direction, and a linear interpolation circuit 27 for linearly interpolating between vertical target value data strings. It is composed of

In the digital convergence apparatus having such a configuration, when the waveform 5-A shown in FIG. 5 is necessary for convergence correction, a target value data sequence of black points shown in 5-B is used to generate a timing clock. An output equivalent to approximately 5-A is obtained by linearly interpolating between the target value data strings through the linear interpolation circuit 27 every time.

[0006]

In this digital convergence apparatus, in order to obtain an output waveform approximate to a required waveform, the number of vertical target value data is increased, and the waveform at a data position associated with linear interpolation is increased. The generation of discontinuous portions of the slope is avoided. If the number of vertical target value data is reduced as shown by 5-C in FIG. 5, the target waveform (5-
Not only does not maintain the similarity with A), but the discontinuity of the waveform slope at the data position becomes significant, and horizontal lines are disturbed on the screen.

When the number of target value data is increased as described above, a large capacity register group and memory are required in system design, and there is a problem that a software program for setting data becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a digital convergence apparatus that can obtain an optimum vertical digital convergence correction waveform with a small circuit configuration and no disturbance on the screen at any display timing. The purpose is to provide.

[0009]

In order to solve the above problems, the present invention takes the following measures. That is, according to the first aspect of the present invention, the storage means for storing correction data for the vertical deflection direction, the linear interpolation means for linearly interpolating between the correction data, the filter constant is variable, and A configuration including a digital filter for filtering the output is adopted.

According to this configuration, even when the number of vertical target value data is small, it is possible to obtain a digital convergence correction waveform having no discontinuous portion of the waveform slope.

According to a second aspect of the present invention, in the first aspect of the invention, when the output from the linear interpolation means is input, the digital filter generates an output waveform irrespective of the number of lines at the display timing. A configuration is adopted in which the correction data sequence is tracked and filtering processing is performed so as not to have discontinuous points on the slope.

According to this configuration, the amount of vertical target value data can be reduced, so that the hardware configuration is simplified and a circuit with reduced software processing can be realized.

According to a third aspect of the present invention, the digital filter inverts a result obtained by dividing an output of an accumulator constituted by a full adder and a register by an arbitrary value, and fully adds input data from a linear interpolation means. The result is multiplied by a filter constant to produce an output.

According to this configuration, the value of the output from the digital filter approaches the value of the input from the linear interpolation circuit.
Further, even if there is a discontinuity in the slope of the input waveform from the linear interpolation circuit, the slope of the output of the digital filter becomes continuous due to the operation of the accumulator.

[0015]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a schematic configuration diagram showing one embodiment of a digital convergence device of the present invention. In FIG. 1, vertical waveform generating circuits 1-1 and 1-2 are provided.
1 to 1-n generate a digital convergence correction waveform in the vertical direction, and are functionally the same.

The horizontal processing circuit 2 performs digital convergence correction in the horizontal deflection direction in which the correction waveform in the vertical direction is switched in an arbitrary position of the horizontal deflection by time division. The D / A converter 3 converts the digital signal subjected to the digital convergence correction into an analog signal. Then, this analog signal is sent to the convergence coil 5 of the CRT 4,
Digital convergence is performed on the CRT 4.

Each of the vertical waveform generating circuits 1 has a vertical target value data string memory 11 for storing an amount to be corrected in the vertical deflection direction, and sequentially reads the values of the vertical target value data string to form a straight line between the data strings. Linear interpolation circuit 12 for performing interpolation
And a digital filter 13 for removing a slope discontinuity portion of the output waveform from the linear interpolation circuit 12. The digital filter 13 receives an optimum filter constant according to the number of vertical lines.

The digital filter 13 in each vertical waveform generating circuit 1 includes a full adder 14 and a register 15
, A divider 16 for dividing the output from the accumulator by an arbitrary value, an inverter 17 for inverting the result in the divider 16, and a result in the inverter 17 and an input from the linear interpolation circuit 12. Full adder 1 to add
8 and a multiplier 19 for multiplying the result of the full adder 18 by a filter constant. The timing clock is input to the linear interpolation circuit 12 and the register 15.

Next, a case where a digital convergence correction waveform is actually obtained in the digital convergence apparatus having the above configuration will be described. First, the linear interpolation circuit 12 performs linear interpolation using the target value data string stored in the vertical target value data string memory 11. Then
The data linearly interpolated by the linear interpolation circuit 12 is input to the full adder 18 of the digital filter 13.

Next, in the multiplier 19, the full adder 1
8 is multiplied by an optimum filter constant according to the number of vertical lines, and the result is sent to a full adder 14 constituting an accumulator. Then, the output from the accumulator is divided by an arbitrary value in the divider 16, and the result is used as the output from the digital filter 13.

In this case, the difference between the input from the linear interpolation circuit 12 and the output of the digital filter 13 is obtained by the configuration of the inverter 17 and the full adder 18. Therefore,
By accumulating the difference value multiplied by the filter constant for each timing clock by the accumulator, the output value of the digital filter 13 asymptotically approaches the value of the input from the linear interpolation circuit 12, and the linear interpolation circuit 12 Even if there is a discontinuity in the slope of the interpolated input waveform, the slope of the output waveform from the digital filter 13 becomes continuous due to the operation of the accumulator.

As described above, the data of the output waveform from which the discontinuous portion of the slope of the output waveform from the linear interpolation circuit 12 has been removed by the digital filter 13 is sent to the horizontal processing circuit 2. Next, in the horizontal processing circuit 2, the digital convergence correction in the horizontal deflection direction is performed by switching the correction waveform in the vertical direction at an arbitrary position of the horizontal deflection in a time division manner. Furthermore, D / A
The digital signal subjected to the digital convergence correction by the converter 3 is converted into an analog signal. Then, this analog signal is sent to the convergence coil 5 of the CRT 4 and
Digital convergence is performed on CRT4.

In the digital convergence apparatus having such a configuration, when the waveform of 3-A shown in FIG. 3 is necessary for convergence correction, a target value data string having few black points as shown in 3-B is used. However, since the discontinuous portion of the slope of the output waveform can be removed, an output waveform almost equivalent to that of 3-A can be obtained as shown in 3-C.

Further, in the digital convergence device of the present invention, by varying the filter constant of the digital filter 13, the asymptotic degree between the output waveform from the digital filter 13 and the input waveform from the linear interpolation circuit 12, The curvature and the like of the change in the slope of the output waveform from the digital filter 13 can be adjusted.

[0025]

As described above, the digital convergence device according to the present invention comprises a linear interpolation circuit for linearly interpolating a vertical target value data sequence and a digital filter having a variable filter constant for removing the resulting gradient discontinuity. Since it is provided, it is possible to fundamentally eliminate the gradient discontinuity of the output waveform in linear interpolation, and to perform optimal digital convergence correction for display timings of various numbers of vertical lines with a small circuit configuration. .

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a digital convergence device of the present invention.

FIG. 2 is a schematic configuration diagram of a digital filter of the digital convergence device of the present invention.

FIG. 3 is a diagram showing a digital convergence waveform in the digital convergence device of the present invention.

FIG. 4 is a schematic configuration diagram showing a conventional digital convergence device.

FIG. 5 is a diagram showing a digital convergence waveform in a conventional digital convergence device.

[Description of Signs] 1 vertical waveform generation circuit 2 horizontal processing circuit 3 D / A converter 4 CRT 5 convergence coil 11 vertical target value data string memory 12 linear interpolation circuit 13 digital filter 14, 18 full adder 15 register 16 divider 17 Inverter 19 Multiplier

Claims (3)

[Claims] 1. A storage means for storing correction data for a vertical deflection direction, a linear interpolation means for linearly interpolating between the correction data, a digital filter having a variable filter constant, and filtering an output from the linear interpolation means. A digital convergence device comprising a filter. 2. The digital filter, when an output from the linear interpolation means is input, regardless of the number of lines at the display timing, the output waveform tracks the correction data sequence, and has no discontinuity in the slope. 2. The digital convergence apparatus according to claim 1, wherein the digital convergence processing is performed in the following manner. 3. The digital filter inverts the result obtained by dividing the output of an accumulator composed of a full adder and a register by an arbitrary value, adds the input data from the linear interpolation means, and multiplies the result by a filter constant. 3. The digital convergence device according to claim 1, wherein the digital convergence device outputs the data.