JP2520414B2 - Digital convergence circuit - Google Patents

Description

The present invention relates to a digital convergence circuit capable of calculating correction data required for convergence correction in a short time.

[Prior Art] A projection-type television receiver that synthesizes images projected from three monochromatic projection tubes corresponding to three primary colors on a screen is compared to a direct-view television receiver that directly looks at the screen on the picture tube. However, it is easy to be affected by the earth's magnetism, and it is necessary to correct the focusing deviation of the scanning lines which occurs when the direction of the projection tube is changed or the posture is adjusted by the convergence adjustment. The digital convergence circuit 1 shown in FIG.
The present invention is applied to a projection television receiver 4 that projects an image from each RGB single-color projection tube 2r, 2g, 2b onto a screen 3 in front of the projection tube 2r, 2g, 2b. The convergence coil (not shown) is included in the focusing deviation correction circuit 5. The focus shift correction circuit 5 is connected to a storage circuit 6 for storing correction data necessary for convergence correction, which is collected in advance on the screen 3 for each sample point divided into a matrix, and is connected to the read control circuit. The correction data 7 is read from the storage circuit 6 in synchronization with the deflection scanning, and is supplied to the focus shift correction circuit 5.

[Problems to be Solved by the Invention] The above-mentioned conventional digital convergence circuit 1 is used for adjusting a crosshatch pattern or a dot pattern on the screen 3 during convergence adjustment for collecting correction data necessary for convergence correction. It is necessary to display an image and to obtain the optimum correction data by trial and error while changing the correction data given to the focusing deviation correction circuit 5 for each individual sample point at that time. Therefore, if the number of sample points is increased. As the number is increased, it is inevitable that the working time becomes long and the memory circuit 6 has a large capacity. Especially, in a projector such as a multi-scan projector, the deflection mode is automatically switched according to the horizontal deflection frequency of 15 to 41 kHz. Memory must be stored because different correction data must be stored for each horizontal deflection frequency. Additional capacity of road 6 has a problem of equal is inevitable.

By the way, Japanese Patent Application Laid-Open No. 60-130288 "Digital Convergence Device" has a correction data storage circuit (frame memory) for storing correction data for each sample point, and a device configured to perform convergence correction based on the correction data. Is disclosed. However, this is a configuration in which all the convergence correction data for each sample point for dividing one screen in a matrix manner is stored in the correction data storage circuit, and therefore the correction data storage circuit is required to have a considerable storage capacity. Also, when the number of scanning lines increases or decreases according to the deflection frequency, the number of scanning lines between preset sampling points is obtained, and the coefficient for each scanning line between sampling points is multiplied to obtain the sampling points on the screen. Although it is said that convergence correction can be performed with high accuracy without increasing the distance, the reality is that the correction data collected in a specific deflection mode cannot support other deflection modes only by linear conversion. In the end, from the viewpoint of maintenance, the correction data must be stored for each deflection mode. In that case, a huge storage capacity is required for the correction data storage circuit, and the deflection frequency that can be actually supported is naturally limited. There was a problem such as being destroyed.

Further, Japanese Unexamined Patent Publication No. 57-140091 “Convergence control device” discloses a device in which correction data is composed of a plurality of basic correction waves and coefficients. This is a special function waveform that becomes zero at the center and both ends of the scanning line, such as Y, after being corrected by the parabolic waveform of the horizontal period or the vertical period (Y = X ² ) when performing dynamic convergence adjustment. = X ³ −X and Y = X ⁴ −X ² are used to correct the residual error, so the time required for convergence correction can be shortened. However, a composite wave Cc (X) that defines the convergence correction data, that is, Cc (X) = K + K ₁ (X ³ −X) + K ₂ (X ⁴ −X ² ) + K ₃ X ² (X ≦ 0) Cc (X ) = K + K ₁ (X ³ −X) + K ₂ (X ⁴ −X ² ) + K ₄ X ² (X> 0) weighting factors K, K ₁ , K ₂ , K ₃ , K ₄ are scanned. Although it differs depending on the position of the line and the position of the sampling point on the scanning line, it is not stored and saved in the memory. This is done on the premise that the deflection frequency is constant in the convergence correction, and once the convergence adjustment has been performed for the display of a specific model, the convergence correction can continue to use the same weighting coefficient. Because. Therefore,
Whenever the deflection frequency was switched, the convergence adjustment had to be performed from the beginning, which was very inefficient.

Further, in the "digital convergence correction device" disclosed in JP-A-61-72491 and JP-A-61-73491, the distortion of the screen display is suppressed by accessing the correction data during the blanking period. A convergence correction device configured to do so is shown. However, in the former convergence correction device, one screen is divided into two, a dedicated correction data storage circuit is provided, and while correction data is being written in one correction data storage circuit, correction is performed from the other correction data storage circuit. The data is read out, and the effect thereof is only to the extent that a large amount of correction data can be rewritten in a fixed period as compared with the method of rewriting correction data in the vertical blanking period. Also, as the memory for storing the correction data, two memories that can store the correction data for 1/2 screen are used, and the memory for one screen is required in total. As a disadvantage peculiar to the method of storing the correction data itself, there is a limit to the reduction of the memory capacity of the correction data storage circuit. Especially when applied to a multi-scan display that supports a plurality of deflection frequencies, it depends on the deflection mode. Therefore, it is necessary to prepare a plurality of sets of two memories for each set, and it is inevitable that the memory capacity is enlarged.

In the latter Japanese Patent Laid-Open No. 61-73491, "Digital Convergence Correcting Device", correction data for convergence correction is converted into difference data and stored in a memory. For example, even if an 8-bit memory is used, A convergence correction device is disclosed which is capable of generating bit correction data. However, this method is based on the assumption that there is no large difference in the correction data between adjacent sample points (adjustment points), so that, for example, when performing convergence correction using a parabolic waveform, there is a difference between adjacent sample points. There is a problem that the difference data is saturated around the screen where the correction data is likely to have a large difference, and the corresponding correction may not be performed sufficiently.

[Means for Solving Problems] The present invention is to solve the above problems, and a convergence deviation correction circuit for performing convergence correction based on correction data, and sample points for dividing a screen into a matrix, Final adjustment at the time of convergence adjustment that is performed while adjusting the correction data that is stippled on the composite wave obtained by combining the basic correction waves by changing the weighting coefficient that is multiplied by the basic correction wave of the horizontal scanning cycle or the vertical scanning cycle. A coefficient storage circuit for storing the weighting coefficient corresponding to the corrected data for each deflection mode, and a weighting coefficient corresponding to the deflection mode is read from the coefficient storage circuit at the time of convergence correction, and each corresponding basic correction wave is multiplied and multiplied. A central processing unit that adds up the results to calculate correction data, and the central processing unit calculates when the convergence correction is performed. The correction data is written in a predetermined access period included in a small period obtained by dividing the horizontal scanning period according to the number of horizontal sampling points, and a correction data storage circuit that stores the correction data for one screen; The address required for reading the correction data is designated in the remaining address designation period excluding the access period from the period, and the correction data read from the correction data storage circuit is synchronized with the deflection scan to correct the focusing deviation. And a read address generating means for supplying to the circuit.

[Operation] According to the present invention, correction data for convergence correction is given as data to be stippled on a composite wave of basic correction waves of a horizontal cycle or a vertical cycle multiplied by a weighting coefficient optimally set at the time of convergence adjustment. , The amount of basic data required for convergence correction is kept to a minimum, and the horizontal scanning period is divided according to the number of horizontal sampling points for the read address generation means required for reading correction data. The time required for convergence correction is shortened by allocating the period excluding the period for accessing the correction data storage circuit by the central processing unit to the address designation period for each of the plurality of small periods.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit configuration diagram showing an embodiment of a digital convergence circuit of the present invention, and FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG.

In FIG. 1, the digital convergence circuit 11 varies the weighting coefficient by which the basic correction wave of the horizontal scanning period or the vertical scanning period is multiplied for each sample point for dividing the screen into a matrix, and synthesizes the basic correction wave. At the time of convergence adjustment performed while adjusting the correction data stippled on the obtained composite wave, a coefficient storage circuit 12 for storing the weighting coefficient corresponding to the final adjusted correction data for each deflection mode.
Have. The weighting coefficient stored in the coefficient storage circuit 12 is read by the central processing unit 14 at the time of convergence correction, multiplied by the corresponding basic correction wave, and added to the multiplication result to be converted into correction data.

In addition to the coefficient storage circuit 12, a correction data storage circuit 13 for storing correction data for one screen is connected to the central processing unit 14 via a buffer circuit 19, and the central processing unit 14 calculates it at the time of convergence correction. The corrected data is sequentially written in a predetermined access period and stored in screen units.
The correction data read from the correction data storage circuit 13 is
The signal is once latched by the latch circuit 16, supplied to the DA converter 17, converted into an analog signal, and then supplied to the focus shift correction circuit 5 via the low pass filter circuit 18 for removing aliasing distortion.

Further, a read address generation circuit 15 is connected to the correction data storage circuit 13 via a buffer circuit 20,
This read address generation circuit 15 is a correction data storage circuit.
Specify the address required to read the correction data from 13. The address generation circuit 15 is a phase locked loop circuit 21.
Operates with a frequency-divided signal phase-locked to the horizontal synchronizing signal generated by the operation clock.

Here, a buffer circuit 19 interposed between the correction data storage circuit 13 and the central processing unit 14, and a buffer circuit 20 interposed between the correction data storage circuit 13 and the address generation circuit 15.
Plays a role of a buffer for adjusting both the access period of the central processing unit 14 for the correction data storage circuit 13 and the address designation period for the correction data storage circuit 13 by the address generation circuit 15 so as not to overlap. That is, in order to adjust the operation timing of each of the central processing unit 14, the address generation circuit 15, or the buffer circuits 19 and 20, it is necessary to use a phase-locked loop circuit 21 that generates a frequency-doubled signal that is phase-locked to the horizontal synchronization signal , A timing generating circuit 22 for generating a timing pulse in response to the vertical synchronizing signal and the frequency-doubled signal, and for adjusting the operation of the central processing unit 14 and the buffer circuit 19, these and the timing generating circuit 22 are also provided.
A gate circuit 23 is provided between them. The gate circuit 23 receives the output timing pulse of the timing generation circuit 22 and the chip select signal of the central processing unit 14 as an input, and a NAND gate circuit 23a which uses the AND negation output thereof as a weight input to the central processing unit 14 and a timing generation circuit. The output timing pulse of 22 is inverted in polarity in the inverter circuit 23b and the chip select signal of the central processing unit 14 is input, and the NAND gate circuit 23c is used as the gate input to the buffer circuit 19 by the NAND output. It

By the way, in this embodiment, 16 sample points are provided by dividing the screen into 16 in the horizontal direction. For this reason,
As shown in FIG. 2 (A), the timing generation circuit 22 divides one horizontal scanning period by 1 / the number of sample points in the horizontal direction.
It is configured to output a timing pulse indicating the beginning of a small period divided into 16. In this timing pulse, the low level period corresponds to the address designation period by the read address generation circuit 15, and the high level period corresponds to the access period to the correction data storage circuit 13 by the central processing unit 14. The buffer circuit 20, which has received the timing pulse, immediately opens its gate for a period T necessary for addressing, as shown in FIG.
The address where is generated is supplied to the correction data storage circuit 13. On the other hand, the central processing unit 14, which has been supplied with the timing pulse via the NAND gate circuit 23a, receives the wait input during the period when the timing pulse is at the low level, and the second
The buffer circuit 19 also closes the gate, as shown in FIG.

When the period T elapses and the timing pulse becomes high level, the weight input to the central processing unit 14 disappears,
Instead of the buffer circuit 20, the buffer circuit 19 opens the gate. As a result, the reading of the correction data from the correction data storage circuit 13 is prohibited, and at the same time, the central processing unit 14
Allows the correction data storage circuit 13 to be accessed. Therefore, during the period when the timing pulse is at the high level, the central processing unit 14 can execute the calculation of the correction data and the transfer of the calculation result without concern about the competition with the read address generating circuit 15.

In the embodiment, the read address generation circuit 15 and the buffer circuit 20 specify an address necessary for reading the correction data in the address specifying period T and supply the address to the focusing deviation correction circuit 5 in synchronization with the deflection scanning. And an address generating means for performing the operation.

Further, in the embodiment, the correction data used for the convergence correction is defined by the composite wave in which the seven types of basic correction waves are weighted and added. Therefore, the weighting coefficient of each basic correction wave is set to the convergence correction target and the convergence correction target. It must be collected as data specific to the deflection mode. The seven types of basic correction waves are, specifically, parabolic waveform waves f ₁ (x), f ₂ (x) and sawtooth waveform waves f of horizontal scanning period and vertical scanning period.
₃ (x), f ₄ (x) and a parabolic waveform wave f ₅ (x) with a horizontal scanning period and a sawtooth waveform f ₆ (x) amplitude-modulated with a sawtooth waveform wave with a vertical scanning period, and a vertical scanning period 2 is a sawtooth waveform wave f ₇ (x) having a horizontal scanning period and amplitude-modulated by the parabolic waveform wave of FIG. Thus, convergence correction amount Y at the distance x from the scan start end of one line of the scanning line, Y = ΣKjfj (x) = K 1 f 1 (x) + K 2 f 2 (x) ·· + K 7 f 7 ( x).

In the above equation, the weighting coefficients K _{1 to} K ₇ are values determined by trial and error, and in the convergence adjustment, the coefficient K of the basic correction wave f ₁ (x) that has the most influence on the convergence correction. _{From 1} , change the convergence deviation on the screen while visually observing it. Then, at this time, the central processing unit 14 calculates correction data at each point where the screen is divided into a matrix with respect to the temporarily set coefficient K ₁ , and the calculated correction data is sequentially corrected during the access period. It is stored in the memory circuit 13. The correction data storage circuit 13 into which the correction data has been written reads out the correction data just stored in synchronization with the horizontal deflection scanning and supplies it to the focusing deviation correction circuit 5 successively.

The convergence adjuster varies the value of the coefficient K ₁ ,
The value of the coefficient K ₁ , which is considered to have the smallest focusing deviation on the screen, is stored in the coefficient storage circuit 12, and the other basic correction waves f ₂ (x), f ₃ (x) ... f ₇ ( Also for x), the value of the coefficient Kj is gradually determined by visual observation. Thus, while the thrust adjustment range gradually, to determine the optimum values for all of the coefficients K ₁ ~K _7, all the basic data required for convergence correction in a particular deflection mode is collected, even convergence adjusting simultaneously completed To do.

However, once the convergence adjustment is completed in this way, the contents stored in the correction data storage circuit 13 can be erased unless the convergence correction is executed under the same conditions. This is because the data required for convergence correction is transformed into weighting coefficients K _{1 to} K ₇ and the coefficient storage circuit 12
It is stored in the coefficient memory circuit from the next time.
The correction data obtained by multiplying each of the basic correction waves by the weighting factors K _{1 to} K ₇ read from 12 is written in a predetermined address of the correction data storage circuit 13, and the convergence correction is performed based on the correction data written here. Is executed.

Further, since the coefficient storage circuit 12 stores only the weighting coefficient by which the basic correction wave is multiplied in a specific deflection mode, there is sufficient margin in its storage capacity, and therefore convergence adjustment when the deflection mode is changed for the same model. The results can also be stored separately for each deflection mode. In this case, the correction data read from the coefficient storage circuit 12 corresponding to the deflection mode is written in the correction data storage circuit 13 each time, and the correction data storage circuit
13 can fully exert its function as a buffer memory.

As described above, according to the digital convergence circuit 11, the basic correction wave f of the horizontal scanning period or the vertical scanning period is sampled for each sample point that divides the screen into a matrix.
_The weighting factors K _{1 to} K _{7 by} which ₁ (x) to f ₇ (x) are multiplied are varied, and the basic correction waves f ₁ (x) to f ₇ (x) are combined and obtained by stippling on the combined wave. When the convergence adjustment is performed while adjusting the correction data ΣKjfj (x), the weighting coefficients K _{1 to} K ₇ corresponding to the finally adjusted correction data are stored in the coefficient storage circuit 12 for each deflection mode.
Unlike the conventional convergence circuit in which correction data required for convergence correction is stored in every memory point for every sample point, the storage capacity of the memory circuit can be significantly reduced. Also, for the basic correction wave, by determining the coefficient sequentially from the basic correction wave that has a high influence on the correction data, it is much easier to converge compared to the method that determines the correction data for every point on the screen. Adjustments can be made.

On the other hand, at the time of convergence correction, the corresponding basic correction waves f ₁ (x) to f ₇ (x) are multiplied by the weighting coefficients K _{1 to} K ₇ read from the coefficient storage circuit 12 according to the deflection mode, and the multiplication results are summed up. Then, the correction data ΣKjfj (x) is calculated, and the calculated correction data is stored in the correction data storage circuit 13 on a screen-by-screen basis.
In order to supply the correction data read out in synchronization with the deflection scanning to the focusing shift correction circuit 5, the correction data storage circuit 13 is required only to store the correction data for one screen in the specific deflection mode. It will be only the function as. Therefore, it is possible to release the correction data storage circuit 13 from the obligation to semi-permanently store the correction data unique to each display to be the convergence correction target. Even for displays of the same model, different correction data depending on the deflection mode can be reduced by changing the weighting factors K _{1 to} K ₇ that multiply the basic correction waves f ₁ (x) to f ₇ (x). Coefficient memory circuit 12 at burden
Therefore, the single coefficient storage circuit 12 can store the weighting coefficients corresponding to the plurality of deflection modes.

Further, the timing generation circuit 22 sets one horizontal scanning period to the number of sampling points in the horizontal direction with respect to the buffer circuit 20 provided between the read address generation circuit 15 and the correction data storage circuit 13 necessary for reading the correction data. The correction data storage circuit is configured such that the period excluding the access period to the correction data storage circuit 13 by the central processing unit 14 is assigned to the address designation period for each of the plurality of small periods divided according to
Avoid the inconvenience that the timing of reading the correction data from 13 and the access period to the correction data storage circuit 13 by the central processing unit 14 for calculating and outputting the correction data conflict with each other, regardless of the horizontal deflection frequency. It is possible to secure a sufficient access period by the processing device 14.

In this case, if the address designation by the read address generation circuit 15 and the access by the central processing unit 14 conflict, the correction data cannot be read correctly from the correction data storage circuit 13 during the conflict period, so the convergence correction waveform is disturbed and the screen It is known to generate noise above. Further, as one method of avoiding such noise generation, for example, the access period by the central processing unit 14 can be limited to a horizontal or vertical blanking period,
In the case of such a system, there is a disadvantage that a considerable time is required to be waited for the calculation of the correction data by the central processing unit 14 to be completed. In other words, the correction data storage circuit 13 by the central processing unit 14 is provided every 1/16 of one horizontal scanning period.
By allocating the period excluding the access period to the address designation period, it is obvious that the time required for convergence correction is significantly reduced.

In the above embodiment, the projection television receiver 4 is used.
However, the convergence correction target may be another direct-viewing type television receiver that directly looks at the image projected on the picture tube, for example.

[Effects of the Invention] As described above, according to the present invention, the weighting coefficient by which the basic correction wave of the horizontal scanning period or the vertical scanning period is multiplied is varied for each sample point for dividing the screen in a matrix form. When the convergence adjustment is performed while adjusting the correction data that is stippled on the composite wave obtained by combining the correction waves, the weighting coefficient corresponding to the final adjusted correction data is stored in the coefficient storage circuit for each deflection mode. Therefore, unlike the conventional convergence circuit that stores the correction data necessary for convergence correction in every memory point for every sample point, the memory capacity of the memory circuit can be significantly reduced, and the basic correction wave can also be corrected. By sequentially determining the coefficient from the basic correction wave that has a high impact on the data, every point on the screen is corrected Compared to the method of determining the data, convergence adjustment can be performed very easily, while at the time of convergence correction, the corresponding basic correction wave is multiplied by the weighting coefficient read from the coefficient storage circuit according to the deflection mode, The correction results are calculated by adding the multiplication results, the calculated correction data is stored in the correction data storage circuit on a screen-by-screen basis, and the correction data read from the correction data storage circuit, which is a buffer memory, in synchronization with the deflection scanning is focused. Since the data is supplied to the deviation correction circuit, the correction data storage circuit is required only to have a function as a buffer memory for storing the correction data in a specific deflection mode. Freed from the obligation to store the correction data peculiar to each display semi-permanently Rukoto can, In addition,
Even for displays of the same model, different correction data depending on the deflection mode can be stored in the coefficient storage circuit with a smaller load by changing the weighting coefficient by which the basic correction wave is multiplied, and thus a single coefficient can be stored. A weighting coefficient corresponding to a plurality of deflection modes can be stored in the memory circuit, and the timing generating circuit determines the horizontal scanning period according to the number of horizontal sampling points for the read address generating means necessary for reading the correction data. For each of the plurality of divided small periods, the period excluding the period for accessing the correction data storage circuit by the central processing unit is assigned to the address designation period. The central processing unit that calculates and outputs the correction data conflicts with the access period to the correction data storage circuit. For convenience, it is possible to secure a sufficient access period by the central processing unit regardless of the horizontal deflection frequency. Therefore, for example, noise is generated on the screen due to competition between the read address generating circuit and the central processing unit. For the purpose of avoiding, unlike the method in which the access period by the central processing unit is limited to the horizontal or vertical blanking period, the time until the calculation of the correction data by the central processing unit is completed can be much shortened. And so on.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a digital convergence circuit of the present invention, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a conventional digital convergence circuit. It is a circuit block diagram which shows an example. 5: Focus shift correction circuit 11: Digital convergence circuit 12: Coefficient storage circuit 13: Correction data storage circuit 14: Central processing unit 15: Read address generation circuit 19, 20 ... Buffer circuit 22 ... Timing Generator 22a …… Counter 22b …… Monostable multivibrator

Claims (1)

(57) [Claims] 1. A convergence deviation correction circuit for performing convergence correction based on correction data, and a weighting coefficient for multiplying a basic correction wave of a horizontal scanning period or a vertical scanning period for each sample point for dividing a screen into a matrix. A coefficient storage circuit for storing the weighting coefficient corresponding to the final adjusted correction data for each deflection mode at the time of convergence adjustment performed while adjusting the correction data stippled on the combined wave obtained by combining the basic correction waves And a central processing unit that reads out a weighting coefficient corresponding to a deflection mode from the coefficient storage circuit at the time of convergence correction, multiplies the corresponding basic correction waves, and sums the multiplication results to calculate correction data, and the central processing unit. The correction data calculated during convergence correction is calculated according to the number of horizontal sampling points in the horizontal scanning period. A correction data storage circuit that is written in a predetermined access period included in the divided small period and stores correction data for one screen, and a correction data storage circuit that stores the correction data in the remaining address designation period excluding the access period from the small period. A digital addressing means for designating an address required for reading and supplying the correction data read from the correction data storage circuit to the focusing deviation correction circuit in synchronization with deflection scanning. Convergence circuit.