JPH10322644A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To update a monitor image and also to prevent contents from changing through an image that is stored from an external device at the time of monitoring an image from semiconductor memory. SOLUTION: Plural images are stored in semiconductor memory 13, and the image signal that is read from the memory 13 is once stored in semiconductor memory 12, after that, supplied to a monitor device from an output terminal 20 through an encoder 19 and performed image reproduction. When a power source switch 4 is turned on to a broken line side, a switch 5 operates as a regenerative image updation instructing means, and whenever the switch 5 is operated, an image read from the memory 13 is changed and a reproduction image is updated on the monitor device. When an external device that is not shown in the Fig. is connected through a connector 14 and the exchange of an image signal is performed between the external device and the memory 13, a state detection circuit 23 turns off an AND gate 6 and prevents reproduction image updation through the switch 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an imaging apparatus for electronically recording an optical image of a subject as an image information signal,
In particular, the present invention relates to an imaging device with improved operability in a case where the image information signal is exchanged between devices by connecting to peripheral devices.

[0002]

2. Description of the Related Art As a conventional apparatus of this kind, there is a so-called electronic camera, which is described in "Television Society Journal", Vol.
6, No. 3 (1992), pp. 300-307, a digital still camera described in the article "Image coding method for digital still camera" (hereinafter referred to as well-known example 1) by Sasaki et al. Catalog “FUJIX DIGITAL STILL” issued by Co., Ltd.
An example is the DS-100 camera described in "CAMERA SYSTEM" (September 1991) (hereinafter referred to as known example 2).

In the electronic cameras described in the known examples 1 and 2, for example, as shown in FIG. 1 of the known example 1, an image information signal obtained by an image pickup device is digitized (quantized) and a semiconductor memory is manufactured. It is recorded on a mounted card (hereinafter referred to as a memory card).

As described above, in the known examples 1 and 2, since the image information signal is handled as a digital signal, the connection with peripheral equipment such as a personal computer which handles digital signals exclusively (through an analog / digital converter or the like). Instead, it can directly send and receive digital signals.)
It is shown that the connection with other systems is good, for example, it is easy and there is no image quality deterioration due to the transmission path.

[0005] It is to be noted that, although the publicly known example 1 does not describe a specific example relating to connection with a peripheral device, it is understood that a memory card is used as an intermediary medium. Known example 2 includes:
A use example of such a memory card is disclosed. That is, first, a memory card is inserted into an electronic camera to record image information signals. Thereafter, the memory card is detached from the electronic camera and inserted into a peripheral device separate from the electronic camera, and is recorded on the memory card. This peripheral information is read by the peripheral device. Also in this case, as a method of transmitting the image information recorded in the memory by the electronic camera to a peripheral device as a digital signal (not through a digital / analog converter or an analog / digital converter, etc.), the above-mentioned memory card is used as an intermediary. No method other than the medium method is disclosed.

As a known device that is connected to a personal computer or the like to electrically transmit and receive image information signals, “F” issued by FUJIFILM Micro Devices Co., Ltd.
SA2001 Overview Explanation Material "(June 24, 1991)
There is an FSA2001 type still image compression / expansion substrate described in (hereinafter referred to as known example 3). The device described in the prior art 3 has a built-in semiconductor memory for storing digital image information signals, and the semiconductor memory is stored in the semiconductor memory between the device and a personal computer connected via a connector, a cable or the like. In other words, the digital image information signal already stored is transmitted and received as a digital signal.

In the case of the publicly known examples 1 and 2, a camera device is used.
While the imaging device includes an imaging unit that generates an electrical image information signal from an optical image, the known example 3 does not include the imaging unit, and the image information signal is created by a personal computer. The image information signal generated by the personal computer is transmitted to the device described in the publicly known example 3 and temporarily stored in the first memory. Next, the image information signal read from the first memory is subjected to image data compression processing by DCT (Discrete Cosine Transform), and is sent back to the personal computer. Such an operation is similar to the operation of the device block shown in FIG.

Here, the writing or reading operation of the image information signal in the device described in the prior art 3 is executed under the time management of the connected personal computer.
Due to the overlap between the writing and reading of the information data in the first memory, the content is switched to the data of another image while the data of one image is being read, and as a result, Inconveniences such as transformation of image information can be avoided beforehand.

Further, in the device described in the known example 3,
At the time of the above-described image data compression processing and the output of the compressed image information signal, data output from this apparatus to the personal computer is performed in synchronization with a clock output from the personal computer. Since the operation is performed with an independent clock inside the apparatus, that is, a clock asynchronous with the clock output from the personal computer, a so-called FIFO (Fast In) is used.
/ Fast Out) type buffer memory.

Here, the operation of the FIFO type memory will be described with reference to FIG.

In FIG. 1, a FIFO type memory 21 has memory addresses 0, 1, 2,..., N, n + 1,.
It has a data storage area at address m. When the memory 21 starts operating, first, data is written in the order of addresses 0, 1, 2,.... The update of the write address is performed at each repetition timing of the clock in the device. When data is written to address n, data reading is started from address 0 at this timing, and data is read in the order of 1, 2,. The update of the read address is performed at each repetition timing of the external clock supplied from the personal computer to the above device. Thereafter, the read address is also updated so as to follow the sequentially updated write address. In both writing and reading, when the address reaches address m,
At the next clock timing, control is performed so as to return to address 0 again.

When the FIFO type memory is operated as described above, the address offset amount in the initial state of writing and reading is Aos (= n), and writing and reading when the writing address becomes the last m address of the buffer memory. Where A'os (= m−n) and T is the repetition period of the external read clock, the write clock timing with respect to the read clock generation timing is Aos × T in the delay direction. A'o at maximum in the direction of travel
Even if each shift is s × T, data can be read correctly in the order written in the memory. That is, data transfer can be performed correctly between systems operating with asynchronous clocks by interposing a FIFO buffer memory.

However, when the FIFO type memory is used, the write clock (in the compressed data output operation mode of the device described in the third conventional example, the clock inside the device)
And the read clock (in the same mode, the clock supplied from the personal computer to the device) cannot be set without any interrelation. For example, regarding the difference in the repetition frequency between clocks, the address offset amount regulated by the capacity of the buffer memory used is a limiting factor, and the read operation start timing is
Time must be managed for the timing of the write operation.

The device described in the third prior art further receives a compressed image information signal from a personal computer, restores the original uncompressed image information signal by an internal data decompression circuit, and restores the original uncompressed image information signal. It also has a function of storing the restored image information signal in the memory and then sending the restored image information signal back to the personal computer. Even in such an operation, the operation timing of this device is executed under the control of the connected personal computer, so that the writing of the image information signal supplied from the computer and not subjected to the compression processing to the first semiconductor memory is performed. And writing of the restored image information signal into the memory can be avoided beforehand.

In such an operation, the FIFO memory operates using a clock supplied from a personal computer as a write clock and using a clock inside the device as a read clock. The relationship is the same as in the case of the above-described operation of outputting the compressed image information signal.

Incidentally, in the device described in the known example 3,
A personal computer program and the like to be connected and used is configured so that an operation mode in which the writing by the clock in the device and the writing by the clock from the personal computer do not overlap in time in the FIFO type memory.

[0017]

By the way, known example 1,
An electronic circuit for an imaging device such as an electronic camera shown in FIG.
By using recent high-integration LSI technology and high-density substrate mounting technology, it can be realized with an extremely small circuit block. For this reason, particularly when a small camera using a single focus optical lens or the like is to be manufactured, in the method using the memory card described in the above-mentioned known example, a space for accommodating the memory card, a memory card loading The space for mounting the connector or the space for the mechanism for removing the memory card is a major factor that hinders miniaturization.

Further, it is conceivable to reduce the size of the device and the memory card, but it is troublesome to remove a smaller memory card from the miniaturized device. The device may be destroyed by dropping the device.

The inconvenience caused by the insertion / removal of the memory card as described above is to provide a connector for inputting / outputting image information signals in the image pickup apparatus so that signals can be directly transmitted / received to / from external devices via this connector. Can be solved. However, the image pickup apparatus is provided with a recording switch corresponding to a shutter button of a conventional film camera, and by closing the recording switch, an arbitrary operation desired by an operator and an external device connected to the connector are performed. There is a case where an operation of capturing an optical image into the device at a timing not restricted by the operation state of the device and recording it as an electric signal in the semiconductor memory is executed or desired to be executed. For example, when an external device is attached to the connector after the recording switch is closed and the recording operation in the apparatus is not yet completed, or when an image is recorded without missing a photo opportunity at a certain moment. is there. Therefore, in the case where the connector as described above is provided in the image pickup apparatus, in order to prevent the change of the image content due to the overlap of the writing and reading of the information in the semiconductor memory, or to write the information by operating the recording switch. In order to avoid the inconvenience of competing with the writing of information input from an external device in the same semiconductor memory and changing the image content, all the device operations are centrally managed by a computer. A new operation management different from the device described in the above-mentioned known example 3 is required.

Further, a personal computer can be considered as an external device for exchanging image information with the image pickup apparatus. In this case, a clock for information transmission completely uncorrelated with a system operation clock inside the image pickup apparatus is transmitted from the personal computer to the image pickup apparatus. If information can be transmitted and received by inputting the information to the user, it is extremely effective in terms of versatility and operability.

[0021] An object of the present invention is to provide a small-sized image pickup apparatus which prevents malfunctions, is excellent in versatility and operability in consideration of the above points.

[0022]

In order to achieve the above object, the present invention relates to an imaging apparatus to which an external device can be connected, comprising: an imaging means for generating an image signal from an optical image; First memory means for storing the compressed image signal, compression means for compressing the image signal stored in the first memory means to generate a compressed image signal, and second memory means for storing the compressed image signal Memory means, expansion means for expanding the compressed image signal stored in the second memory means, and reproduced image update instructing means for instructing updating of a reproduced image on a monitor device for displaying the expanded compressed image signal And a connector enabling connection of the external device, and when the compressed image signal from the external device connected via the connector is being written to the second memory unit, the reproduced image update instruction unit is Operated Also, a control means for reading out of the second compressed image signal stored in the memory means is controlled so as not performed.

The control means detects whether or not an external device is connected via the connector.
For example, a switch is provided that is closed when an external device is connected via the connector, and the switch outputs an electric signal while the external device is connected via the connector. Alternatively, for example, after an external device is connected via a connector, a signal input from the external device via the connector before execution of at least image signal exchange with the external device is detected, and an electric signal is output.

The compressed image signal stored in the second memory means is read out and decompressed by the decompression means, and then supplied to the monitor device for image reproduction. The reproduced image update instruction means is operated. Each time the compressed image signal of the image read by the second memory means can be changed, whereby the reproduced image on the monitor device can be updated.

However, when an external device is connected via the connector and an image signal is transmitted / received between the external device and the second memory means, this is detected by the control means and reproduced. Even if the image update instruction means is operated, the update of the reproduced image cannot be performed. Thus, the content of the reproduced image on the monitor device is not changed by the image transferred between the external device and the second memory means.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an imaging apparatus according to the present invention, wherein 1 is an imaging element, 2 is a timing generation circuit, 3 is an oscillator, 4 is a power switch, 5 is a recording trigger switch, and 6 is an AND gate. , 7 are a timing generation circuit, 8 is an oscillator, 9 is an inverter, and 10, 1
1 is a switch, 12 and 13 are semiconductor memories, 14 is a connector, 15 and 16 are switches, 17 is a camera signal processing circuit, 18 is a switch, 19 is an encoder, 20 is an output terminal, 21 is an image data compression processing circuit, 22 Is an image data decompression processing circuit, 23 is a state detector, and 24 is a switch.

In FIG. 1, when a user operates a power switch 4 to close a circuit, a timing generation circuit 2 composed of a microcomputer or a logic circuit detects this, and
A power supply circuit (not shown) is operated to start supplying operation power to each unit, and the first reference frequency signal supplied from the oscillator 3 is subjected to processing such as frequency division as appropriate, so that the imaging device 1 and the camera signal processing circuit 17 are processed. , And generates the operation clock pulses CK1, CK3, and CK2 of the respective encoders 19 and the switch control signals SW1, SW2, and SW3. These switches control signals SW1, SW2, SW3 close the switches 10, 16, 18 in the direction shown. These switches 10, 16, and 18 can be easily configured by a known multiplexer circuit based on a logic circuit technique.

The image sensor 1 having an optical lens (not shown) mounted on the light receiving surface outputs an analog image information signal AIS obtained by photoelectrically converting an optical image. The camera signal processing circuit 17 comprises a circuit known in television cameras such as a correlated double sampling circuit, an automatic gain adjustment circuit, a matrix circuit, a gamma processing circuit, and an A / D (analog / analog) circuit in the signal path of the circuit configuration. A digital) converter is provided for outputting a digitized baseband digital image information signal DIS. This digital image information signal DIS is supplied to an encoder 19 via a switch 18, and a chroma signal modulated to a subcarrier is generated from the baseband digital image information signal DIS, and one of the baseband luminance signal and the clock pulse CK1 is generated. The timing is synchronized with the synchronization signal supplied from the timing generation circuit 2 as a unit, and these are combined and output from the output terminal 20 as a composite video signal or as an independent component signal.

The encoder 19 has a D / A (digital / analog) converter, and outputs an analog image information signal to an output terminal 20. Here, by connecting a known television monitor device to the output terminal 20, a continuous (moving image) image captured by the image sensor 1 can be displayed as a television image.

The above operation is the same as the operation of a known television camera device, and can be realized using, for example, a commercially available television camera circuit of a VM-H39 type VTR integrated camera manufactured by Hitachi, Ltd.

Next, the operation of the electronic camera function of this embodiment will be described. Baseband digital image information signal DIS output from camera signal processing circuit 17
Is supplied to the semiconductor memory 12 via the switch 16. At this time, the clock CL and the address signal Ad generated in synchronization with the camera signal processing clock CK3 and the like by the timing generation circuit 2 are written in the semiconductor memory 12 via the switch 10 to the write clock WC and the write address, respectively. It is supplied as a signal WA.

FIG. 3 is a timing chart showing the operation of the semiconductor memory 12. FIG. 3A shows the operation timing of a television camera circuit including the image pickup device 1 and the camera signal processing circuit 17, and FIG. () Shows the storage timing of the semiconductor memory 12, and (c) shows the operation mode of the semiconductor memory 13. Further, P1, P in FIG.
2, P3,... Represent sequential images (field images or frame images of the television signal) in the image information signal DIS. Images written to the semiconductor memory 12 are also denoted by the same reference numerals.

In FIGS. 1 and 3, when the power switch 4 is closed at time T1, the television camera circuit starts the above-described operation, and the image information signal DIS is generated. The semiconductor memories 12 and 13 generally have a memory capacity capable of recording data for one field image or one frame image.

In general, image data is written into the semiconductor memory 12 in such a manner that previously written image data is replaced with new data by a predetermined data amount (for example, 8 bits) in time sequence. Be executed.
Here, when a natural image is recorded by an electronic camera or the like, the image 1
Since a data amount of at least a kilobit unit per sheet is required, even after writing of one piece of image data is started, until the writing of this one piece of image data is completed, the image written before that is completed. Data will remain in the semiconductor memory. That is, for example, in FIG. 3B, in the time domain indicated by P2, not only the data of the image P2 is stored in the semiconductor memory 12, but also the data of the image P1 written before it and the current time. The data of the image P2 to be written is mixed and stored.

In FIG. 3, a portion indicated by the term "hold" such as "hold P4" is written with new image data (ie, after writing of one image data is completed). , Image data is not rewritten), and the image data is stored as it is.

After time T1, in the semiconductor memory 12, the images P1 to P4 generated by the camera signal processing circuit 17 are sequentially written, and the image data is updated each time. When the recording trigger switch 5 is closed by the user (time T2), at this time, when the writing of the data of the image P4 being written is completed, the next data writing to the semiconductor memory 12 is prohibited, and this image The semiconductor memory 12 is controlled so that the data of P4 is held (frozen). This control is executed by the timing control circuit 2 stopping the generation of the clock CL at the timing of the vertical synchronization signal of the image information signal AIS. Subsequently, the timing control circuit 2 generates an operation control signal MC. This operation control signal MC is supplied to the state detection circuit 2 as described later.
3 is supplied to a timing generation circuit 7 through an AND gate 6 that is controlled to open and close in response to the output signal SD, and starts its operation.

The timing generation circuit 7 processes the reference signal supplied from the oscillator 8 as necessary, such as frequency division, and generates a drive clock CL1 for the semiconductor memory 12, an address signal Ad1, and the like.
The operating clocks CK4 and CK5 of the image data compression processing circuit 21 and the image data decompression processing circuit 22, the driving clock CL2 of the semiconductor memory 13 for storing the compressed image data CID2, the address signal Ad2, and switching between read operation and write operation. This is a circuit for generating a read / write switching signal (R / -W2) for control, and can be constituted by a known logic circuit. The read / write switching signal (R /
-W2) indicates, for example, "read" when "H" (high level) and "write" when "L" (low level).
Shall be indicated.

The timing generation circuit 7 has an operation control signal M
Upon receiving C, the image data compression process and the operation of writing the compressed image data CID into the semiconductor memory 13 are started.

That is, the clock CL1 and the address signal Ad1 output from the timing generation circuit 7
0, a read clock RC and a read address signal R
A is supplied to the semiconductor memory 12. This allows
Data of the image P4 stored and held is sequentially read out from the semiconductor memory 12, and is subjected to compression processing by the compression processing circuit 21 to obtain compressed image data CID. By using a FIFO type semiconductor memory as the semiconductor memory 12, as described with reference to FIG. 2, reading of the data of the image P4 can be started even in the middle of the data writing period of the image P4 of FIG. Can be. Further, the write clock WC and the read clock RC may be asynchronous.

The compressed image data CID output from the compression processing circuit 21 is supplied to a data input / output terminal I of the semiconductor memory 13.
/ O, and a clock CL2 output from the timing generation circuit 7, an address signal Ad2, and a read / write switching signal (R / -W2) indicating "write".
Is supplied to the semiconductor memory 13 via the switch 11 as a clock CL, an address signal Ad, and a read / write switching signal (R / -W), and is indicated by P4 as shown in FIG. The data of the image P4 compressed during the period is written to the semiconductor memory 13.

Here, the semiconductor memory 13 is a memory which is switched between a write mode of image data and a read mode by a read / write switching signal (R / -W), and a read / write switching signal (R / -W). Is in the write mode when is "H". At this time, the data input / output terminal I / O is used for data input, and the clock CL and the address signal Ad are used.
Are used as a write clock and a write address signal, respectively. When the read / write switching signal (R / -W) is "L", the read mode is set. At this time, the data input / output terminal I / O is for data output, and the clock CL and the address signal Ad are used as a read clock and a read address signal. A semiconductor memory circuit that is used by switching between writing and reading in this manner is also known.

In this embodiment, when the size of the device is reduced, a small circuit formed as an LSI is employed for the data compression circuit 21 and the data decompression circuit 22, but from the viewpoint of the processing capability of the circuit elements, Generating one piece of compressed image data requires longer processing time than generating one piece of image data by the camera operation described above. Therefore, the semiconductor memory 12 is used as a buffer memory,
Enables high-speed image capture of camera operation. At this time, the data of the image P4 is held in the semiconductor memory 12 until the compression processing of the data of the image P4 and the writing to the semiconductor memory 13 are completed, thereby preventing the image content from being changed. I have. In order to perform this operation, the timing generation circuit 2 sets the operation control signal M
During the period from when C is output to when the operation end signal ME is supplied from the timing generation circuit 7, the closing information of the recording trigger switch 5 is not taken in.

In FIG. 3C, the timing generation circuit 7 stops the generation of the write clock CL2 at the time when the writing of the data of the compressed image P4 is completed, and thereafter, the semiconductor memory 13 stops the generation of the image P4. The mode is set to the data holding mode, and an operation end signal ME is sent to the timing generation circuit 2. The timing generation circuit 2 outputs the operation end signal ME
Then, the generation of the operation control signal MC is stopped, and the writing operation of the semiconductor memory 12 is started again, and the data of the images P5, P6, and P7 are sequentially written to the semiconductor memory 12, and the next closing of the recording trigger switch 5 is performed. Prepare for operation.

It is conceivable to use a semiconductor memory 13 having a data storage capacity for a plurality of images. At this time, during the data writing operation period indicated by P4, P7 and the like in FIG. 3C, only a partial area assigned to one image among the storage areas of the image data of the semiconductor memory 13 is new. Rewritten with image data. In addition, in the period indicated by “hold” in FIG. 3C, not only the image data written immediately before this but also the image data written before this is held. Further, when the semiconductor memory 13 is, for example, a static random access memory backed up by a battery or a so-called flash nonvolatile memory,
Prior to the writing of the data of the image P4 in FIG. 3C, the image Px recorded at the time of photographing prior to the current photographing started by the closing of the power switch 4 at time T1.
Is held.

FIG. 3 also shows the memory operation when the recording trigger switch 5 is closed again (time T3) during the period of writing the data of the image P7 into the semiconductor memory 12. The operation in this case is also the same as the operation of recording the data of the image P4, and thus the description thereof is omitted.

The operation of the electronic camera function (still image recording function) of this embodiment has been described above with reference to FIG. 3, but this is similar to the operation of the apparatus shown in the above-mentioned known examples 1 and 2.

When the semiconductor memory 13 is a flash memory, image data cannot be rewritten by so-called overwriting due to the structure of the element. For this reason, FIG.
At the timing of the image P4 in FIG.
Before writing the data of the image P4, the operation of temporarily erasing the image data remaining in the memory area allocated as the data writing area of the image P4 is executed. This erasing operation is, specifically, an operation for writing data of a predetermined logic level in the semiconductor memory. For example, a control (not shown) output from the timing generation circuit 7 is output to the output side of the data compression circuit 21 in FIG. A logic gate controlled to output data of a predetermined level by a signal;
Prior to writing the data of the image P4, the data of the predetermined level can be written.

As a flash memory device,
Data input / output terminal I /
It is also known to take in a code signal supplied to O into a memory element and switch an operation mode such as writing and erasing. Further, when erasing or writing, a so-called ready / busy signal generation function is provided for generating data of a predetermined logic level to warn the user to wait for progress to the next operation until the operation inside the memory element is completed. What is possessed is also known. Even when such a memory element is used, a plurality of switching signals of the switch 11 are provided as necessary, and a control code is appropriately supplied to a data input / output terminal I / O terminal by switching between the image data and the semiconductor memory. And can be configured by a known technique in the field of digital circuit technology. Also, switch 1 in FIG.
An interface circuit according to the function of the memory element to be used can be provided between the semiconductor memory 13 and the semiconductor memory 13.

As described above, when recording the image information signal,
When the semiconductor memory 13 is a flash-type memory, the erase operation is performed in conjunction with the semiconductor memory 13 so that the user does not need to be bothered by the erase operation inherent to the flash-type memory. The operation can be performed with the same feeling as that of a memory device that can rewrite data.

The feature of this embodiment is that the connector 14 and the switches 11 and 15 are provided, and the operation of the state detection circuit 23 and the timing generation circuit 7 for detecting the preparation state of the signal transfer operation with the external device is started. Control means such as an AND gate 6 for blocking is provided so that digital image information signals can be transmitted and received between external devices and the semiconductor memories 12 and 13.

Hereinafter, this point will be described with reference to FIGS. FIG. 4 is a block diagram showing a specific example of the state detection circuit 23 in a state where an external device is connected to the connector 14 of FIG. 1, where 23a is a T-FF (T-type flip-flop) and 23b is AND. A gate, 23c is an OR circuit, 25 is an external device, and 25a is a connector.
Are assigned the same reference numerals.

FIG. 5 is a timing chart for explaining the function of transmitting / receiving a signal to / from an external device. The signals corresponding to those in FIG. 4 are denoted by the same reference numerals. FIG.
(A), (b), and (c) show FIGS. 3 (a), (b),
Same as (c).

First, in FIG. 1 and FIG. 5, at time T1 when the power switch 4 is turned on, as described above,
Since the image data already recorded is held in the semiconductor memory 13 and the operation of the timing generation circuit 7 has been stopped, the operation end signal ME becomes "H" to indicate the operation end state. Recording trigger switch 5 at time T2
Is closed, and the writing of the data of the image P4 into the semiconductor memory 13 shown in FIG. 5C is started by the above-described series of operations, the level of the operation end signal ME becomes "L", and the timing Indicates that the generation circuit 7 is operating.

Next, in FIGS. 4 and 5, the AND gate 23b of the state detection circuit 23 has one input
An operation end signal ME is supplied. The other input of the AND gate 23b is connected to the external device 25 by the connector 14.
When the connector 25a is fitted and an external device is connected, a signal (hereinafter, referred to as a preparation status instruction signal) CSSSa indicating a preparation status of a signal transfer operation supplied from the external device 25 via the connectors 25a and 14 is used. is there. The output of the AND gate 23b is used as a trigger clock as TF
It is supplied to the clock terminal T of F23a.

The reset terminal R of the T-FF 23a is supplied with an initial reset signal INS when the power is turned on by the power switch 4 (FIG. 1) via the OR gate 23c. This initial reset signal INS is generated only for a predetermined short time after the power is turned on, and is used to reset each logic circuit to a predetermined initial state. Such a reset method is well known in the logic circuit technical field. This is a method, and a dedicated IC for generating a reset signal at the start of power supply is also commercially available. Therefore, the state detection circuit 23
The reset signal generation IC may be provided as a component of the above, but the output signal of the reset signal generation circuit provided in the timing generation circuit 2 may be used as the initial reset signal INS.

The Q output of the T-FF 23a is used as the state detection signal S
Output as D. The state detection signal SD is reset from an undefined state (an undefined state of “H” or “L”) to an “L” state at a time T1, as shown in FIG. 5, by an initial reset signal INS. When the state detection signal SD is "L", the switches 11 and 15 in FIG. 1 are in the state shown in FIG. The "L" state detection signal SD is inverted by the inverter 9 in FIG. 1 to become "H", and the AND gate 6 is set to a state where the operation control signal MC passes. As a result, as described with reference to FIG.
The data of the image P4 is written into the semiconductor memory 13 in conjunction with the closing of the recording trigger switch 5 in the step (1).

Here, at time T4, the external device 25 instructs the state detection circuit 23 that the external device 25 has completed preparation for signal transmission / reception.
It is assumed that Sa has been supplied. At this time, when the operation end signal ME changes to "H" in accordance with the end of the operation of the timing generation circuit 7 due to the completion of the writing of the data of the image P4 into the semiconductor memory 13, the T-FF 23a is triggered at this timing and the state ends. The detection signal SD is inverted to “H”.

When the state detection signal SD changes to "H", FIG.
The switches 11 and 15 are switched in the direction opposite to that shown in FIG. The switch 11 which is a one-way digital signal switch can be easily constituted by, for example, a multiplexer circuit, and the switch 15 which is a two-way switch can be easily constituted by, for example, a so-called analog switch circuit. Well known in the art.

The state detection signal SD is supplied to the connectors 14 and 25a.
Is supplied to the external device 25 via an external device, and notifies the external device 25 that the image pickup apparatus is in a state capable of performing signal transmission / reception by the fact that the level is “H”.

When the external device 25 receives the state detection signal SD, it receives the clock CL3, the address signal Ad3, and the read / write switching signal (R / -W3) for instructing reading via the switch 11 in FIG. Is supplied to the semiconductor memory 13. Thereby, the semiconductor memory 1
3 reads out, for example, one specific image or all image data from the recording area specified by the address signal Ad3, and reads the image data from the data input / output terminal I / O terminal via the switch 15 and the connector 14 to the outside. Equipment 25 (FIG. 4)
To supply. At this time, the operation of the semiconductor memory 13 is exclusively controlled by the external device 25.

In FIGS. 4 and 5, the external device 25 is
When desired image data is read from the semiconductor memory 13,
The output of the clock CL3 is stopped, and the preparation status indication signal CS
Sa is returned to “L”, and at the same time, a transmission / reception operation end signal CSSb is supplied to the state detection circuit 23. This transfer operation end signal CSSb is supplied to the T-FF through the OR gate 23c.
23a, which resets the state detection signal S
D is returned to “L”.

When the external device 25 is a personal computer, the signal transmission / reception clock CL3 (FIG. 1)
Often, relatively low frequency signals are used as
It is convenient that the frequency can be determined only by the constraint condition of the external device 25 alone. This is generally
When a low-cost external device 25 is used, its data processing capability is low. Therefore, it is preferable to transmit and receive signals using a low-frequency clock. This is because it is desired to complete the transfer operation at a time. Therefore, the external device 25
It is conceivable that the time required for signal transmission and reception differs depending on the type of external device used, even if the amount of signal data transmitted and received is the same.

In this embodiment, the state detection signal SD is also supplied for controlling the AND gate 6 inserted in the transmission path of the operation control signal MC for instructing the start of operation of the timing generation circuit 7, and the state detection signal SD Is at "H", the operation control signal MC is blocked by the AND gate 6, and at least one of the interlocking operations of writing image data to the semiconductor memories 12 and 13 executed by closing the recording trigger switch 5 is performed. The writing of new image data to the semiconductor memory 13 is prohibited, and the image data in the semiconductor memory 13 is altered during the uncertain time required for signal transmission / reception with the external device 25 to change the image content. To prevent.

FIG. 5 explains the operation of the embodiment having the above configuration. For example, the state detection signal SD
Is "H", the timing generation circuit 2 can be configured by a known technique in the logic circuit technical field so that the closed circuit of the recording trigger switch 5 is ignored, and the alteration of the image data in the semiconductor memory 13 can be prevented. However, in this case,
Naturally, all operations by operating the recording trigger switch 5 are prohibited.

In FIG. 5C, when the writing operation of the image P4 in the semiconductor memory 13 is completed and the operation end signal ME is inverted to “H”, as described with reference to FIG. The writing of P5, P6, and P7 resumes (FIG. 5B). When the recording trigger switch 5 is closed at time T3, the image P7 is held in the semiconductor memory 12, but the state detection signal SD is "H". It is blocked and not supplied to the timing generation circuit 7, and the timing generation circuit 7 does not start operation. Therefore, writing of the data of the image P7 is prohibited in the semiconductor memory 13, and the semiconductor memory 13 keeps the previous image data.

As described above, since not only the switching operation of the switches 11 and 15 but also the operation of the timing generation circuit 7 is prohibited, useless operation of the circuit can be omitted and power consumption can be suppressed.

When the reading of the data of the image P4 to the external device 25 is completed and the state detection signal SD output from the state detection circuit 23 becomes "L" by the transmission / reception operation end signal CSSb, the switches 11 and 15 are turned on again. The direction switches to the direction shown in FIG. The AND gate 6 is also in a passable state, the recording trigger switch 5 is closed, and the image P7
When the recording of the image P7 in the semiconductor memory 13 is instructed, the operation control signal MC is supplied to the timing generation circuit 7 upon completion of the recording of the image P7 in the semiconductor memory 12. As a result, the timing generation circuit 7 starts operation, the operation end signal ME becomes "L", and the data of the compressed image P7 is written into the semiconductor memory 13 at the timing shown in FIG. When the writing is completed, the operation end signal ME becomes "H" again, the preparation status instruction signal CSSa becomes "H" again, and it is instructed that the external device 25 is ready for signal transfer. As a result, the state detection signal SD is inverted to “H”, and the external device 25 is notified that the image pickup apparatus is again in a state capable of transmitting and receiving signals.

As described above, according to the operation of this embodiment, during the data reading from the semiconductor memory 13 to the external device 25, the data writing to the semiconductor memory 13 is prohibited or the data to the semiconductor memory 13 is not read. Since data reading to the external device 25 during writing is prohibited, there is no possibility that image data in the semiconductor memory 13 is rewritten during the data reading operation of the semiconductor memory 13 to the external device 25. Therefore, it is possible to prevent the data of a plurality of images from being output in a mixed manner, instead of the data of a single captured image. It can be prevented from being transformed into something different from the one.

In the case where the output of the operation control signal MC is made to be in a standby state, the image data is transferred to the semiconductor memory 12 by the closing operation of the recording trigger switch 5 even while the data is being read out to the external device 25. Ingest,
That is, the photographing can be executed, and the captured image information is automatically transferred to the semiconductor memory 13 and recorded as soon as the data reading to the external device 25 is completed, without requiring a new operation by the user. can do. Further, when the data writing to the semiconductor memory 13 is completed, the state detection signal SD is automatically inverted to “H” in conjunction with this, and
This embodiment can be switched to a state in which signals can be exchanged with the external device 25 and the connected external device 25 can be informed of this state. Can be shortened, and the data can be continuously read out by the external device 25.

Further, the preparation status instruction signal CSSa is
The timing is not limited to the level change timing shown in FIG. 5, but may be maintained once, for example, once inverted to “H”. In this case, FIG.
And the operation end signal M
Each time E is inverted from “L” to “H”, a signal can be automatically exchanged with the external device 25.

Further, the preparation status instruction signal CSSa is transmitted to the
As shown in (2), when it is defined that the signal returns from “H” to “L” every time the signal transfer by the external device 25 is completed, it is not necessary to supply the transfer operation end signal CSSb from the external device 25. No, for example, the preparation status indication signal C
A known logic circuit configuration such as a monostable multivibrator circuit for generating a pulse signal of a predetermined pulse width in synchronization with the edge timing of SSa being inverted from “H” to “L” is used as the state detection circuit 23. And a preparation state instruction signal CSSa is supplied thereto to obtain a pulse signal corresponding to the transmission / reception operation end signal CSSb.

In FIG. 5, the preparation status indication signal C
When the image data holding timing by SSa, that is, when the preparation status instruction signal CSSa is inverted to “H” during the “H” period of the operation end signal ME, the state detection circuit 23 immediately outputs the “H” state detection signal SD. Then, the imaging apparatus of this embodiment enters a signal transmission / reception state with the external device 25. In particular, the imaging apparatus prepares immediately before the operation end signal ME switches from “H” to “L” in conjunction with the closing of the recording trigger switch 5. When the status indication signal CSSa is inverted from “L” to “H”, a noise signal with a small pulse width is generated from the AND gate 23b in FIG.
a may be triggered and the state detection signal SD may be inverted to “H”. Further, when the preparation status instruction signal CSSa is inverted to “H” before the time T1 or at a time near the time T1, T−T by the initial reset signal INS.
Due to the conflict with the reset control of the FF 23a, the T-FF2
The operation of 3a may be uncertain.

FIG. 6 is a circuit diagram showing another embodiment of the state detection circuit 23 in FIG. 1 which is also suitable for such a case. In FIG. 6, reference numeral 23d denotes an inverter, reference numerals 26 to 29 denote resistors, reference numeral 30 denotes transistors, reference numerals 31 and Reference numeral 32 denotes a capacitor, and reference numeral 33 denotes a power supply. Parts corresponding to FIGS. 1 and 4 are denoted by the same reference numerals.

FIG. 7 is a waveform diagram showing signals of various parts in FIG. 6, and signals corresponding to FIG. 6 are denoted by the same reference numerals.

In FIG. 6, a fitting detection switch 24 is provided in the state detecting circuit 23, and when a connector 25a of an external device (not shown) is fitted to the connector 14 (time T1), this fitting is performed. When the detection switch 24 is pressed and closed, the "H" voltage signal SV from the power supply 33 is supplied to the AND gate 23b. This "H" voltage signal SV replaces the preparation status instruction signal CSSa in the specific example shown in FIG. Note that the resistor 28 is connected to the fitting detection switch 2.
4 is to keep one input of the AND gate 23b at the ground ("L") level when the switch 4 is open.

As shown in FIG. 7 (a), when the power supply of the apparatus is turned on by closing the power switch 4 in FIG.
As described above, the preparation status instruction signal CSSa
1 is the same as inverting from “L” to “H”.

In this specific example, the AND gate 23
b, the operation end signal ME is supplied via a resistor 26. A capacitor 31 and a transistor 30 are connected between this input terminal of the AND gate 23b and the ground.
And are connected in parallel. The initial reset signal I is applied to the base of the transistor 30 via the resistor 27.
NS is provided.

Then, as shown in FIG. 7A, when the initial reset signal INS of “H” is generated at the time of turning on the power,
Since the transistor 30 becomes conductive during the signal period,
The input level ADI on the side to which the operation end signal ME of the AND gate 23b is supplied is kept at "L". When the initial reset signal INS becomes “L” after a predetermined time has elapsed, the transistor 30 is turned off.
If the operation end signal ME is "H", the input level ADI becomes "H" after a time delay determined by the time constant of the resistor 26 and the capacitor 31. During this time delay, T
Since the -FF 23a has been reset by the initial reset signal INS, the T-FF 23a is reliably triggered by the "1 level" output ADO of the AND gate 23b obtained when the input level ADI has become "H". , A state detection signal SD can be generated.

FIG. 7B shows the "H" operation output from the operation of the timing generation circuit 2 at time T2 'in conjunction with the closing operation of the recording trigger switch 5 (FIG. 1) at time T2. This is for an operation in a case where the control signal MC and the timing at which the fitting detection switch 24 is closed and the voltage signal SV of “H” is supplied from the power supply 33 to the AND gate 23b conflicts.

At time T2 ', when the timing generation circuit 7 (FIG. 1) starts operating by the "H" operation control signal MC generated from the timing generation circuit 2 (FIG. 1), the operation end signal ME becomes "H". From “L” to “L”. However, in general, due to the operation delay depending on the signal propagation speed of the circuit element or the phase relationship between the operation clock of the timing generation circuit 7 supplied from the oscillation 8 and the operation control signal MC, the time is generally reduced. There is a time difference from T2 'to the point when the operation end signal ME is inverted to "L". When the voltage signal SV from the fitting detection switch 24 is inverted from “L” to “H” during this time difference, a pulse-like “H” output signal ADO is generated from the AND gate 23b for a short period. When the T-FF 23a is triggered by the output signal ADO, the state detection signal SD is inverted to "H". In this state, the switches 11 and 15 (FIG. 1) are operated despite the operation of the timing generation circuit 7. ) Is connected to the access side of the external device, so that image data shot at the time T2 cannot be stored in the semiconductor memory 13 (FIG. 1).

Therefore, the specific example shown in FIG. 6 is provided with the following configuration in order to avoid such a situation in which photographing is invalidated.

That is, in addition to the transmission / reception operation end signal CSSb and the initial reset signal INS as in the specific example shown in FIG. 4, the operation end signal ME is supplied to the OR circuit 23c with its level inverted by the inverter 23d. Thus, when the operation end signal ME is inverted to “L”,
The T-FF 23a is reset, and once "H"
The state detection signal SD, which has been inverted, returns to "L" again. Thus, the image information can be effectively written into the semiconductor memory 13 by the operation of the timing generation circuit 7.

At this time, the condition for generating the state detection signal SD having a pulse-like waveform of “H” as shown in FIG. 7B is such that the voltage signal SV from the fitting detection switch 24 becomes “H”. Circuit operation delay time t from the inversion point to when the AND gate 6 (FIG. 1) is closed by the state detection signal SD.
1 and a delay time t2 defined by the sum of a delay time t2 from when the operation control signal MC is inverted to “H” to when the T-FF 23a is reset by the “L” operation end signal ME. In the area, the voltage signal SV from the fitting detection switch 24 is inverted to “H”. At this time, the times t1 and t2 can be predicted in advance from the speed performance of the circuit element to be used, the adopted circuit configuration, and the like, and the “H” of the state detection signal SD shown in FIG. The period is shorter than the period (t1 + t2).

Therefore, the connector 14 of the state detection signal SD
(B) is supplied to an external device by providing a circuit configuration for preventing the output of a signal having a predetermined pulse width or less from being output to the output unit. Can be prevented. In FIG.
As such blocking means, an integrating circuit including a resistor 29 and a capacitor 32 is used. Of course, other configurations that achieve similar functions are well known in the logic circuit art. It should be noted that, even if such a pulse-like state detection signal SD is supplied to an external device as it is, the external device side may be configured not to respond to a state detection signal SD having a small pulse width assumed in advance. When the state detection circuit 23 side is configured to block such a pulse-like state detection signal SD as described above, there are fewer restrictions on the operation of the external device, and the troublesomeness in setting an operation program in the external device is reduced. Can be reduced.

As still another specific example of the state detection circuit 23, in FIG. 6, a gate is provided on the resistor 28 side of the fitting detection switch 24, and the gate signal G shown in FIG.
C may be used to block the voltage signal. The gate signal GC becomes “H” at a time T2 when the recording trigger switch 5 is closed, that is, a predetermined time before the operation control signal MC, and a predetermined time elapses after the operation end signal ME is inverted to “L”. The gate signal G is generated by the timing generation circuit 2 so as to return to "L" later.
During the “H” period of C, the voltage signal SV from the engagement detection switch 24 is blocked and not supplied to the AND gate 23b, and the voltage from the engagement detection switch 24 in the time domain (t1 + t2) of FIG. The signal SV is prohibited from being inverted to “H”. In this case, the "H" state of the output signal ADO of the AND gate 23b and the state detection signal SD shown after the time T2 'in FIG. 7B does not occur. Therefore, it is not necessary to supply the inverted signal of the operation end signal ME to the OR circuit 23c.

Although the state detection circuit 23 shown in FIGS. 4 and 6 and the AND gate 6 and the inverter 9 shown in FIG. 1 are constituted by hardware logic circuits, for example, a microcomputer is used. The state is detected by the initial reset signal INS, operation end signal ME, voltage signal SV, gate signal GC, and transfer operation end signal CSSb in FIG.
C or the state detection signal SD may be generated.

The above is a description of the imaging operation and the operation of outputting image information to an external device in the embodiment shown in FIG. 1. Next, the image reproduction operation in this embodiment will be described with reference to the operation time chart shown in FIG. This will be described with reference to FIG.

In this operation, in FIG. 1, the power supply switch 4 is closed in a state indicated by a broken line in the opposite direction to that shown in the figure, thereby switching to the reproduction mode.
The recording trigger switch 5 is configured to have a function as a reproduced image update instruction switch that enables the television monitor device connected to the output terminal 20 to sequentially select reproduced images. Such function switching
It can be easily realized using a microcomputer or a logic circuit technology.

In FIGS. 1 and 8, when the user closes the power switch 4 to the reproduction mode shown by the broken line at time T1, the operation power is turned on and the reproduction is started as shown in FIG. The operation starts. At this time, as an initial operation, as shown in FIG. 8B, the data of the first image P1 is read from the semiconductor memory 13 in the image data holding state, and as shown in FIG. Memory 1
2 is written. Such an initial operation is performed as follows.

The timing generation circuit 2 includes a power switch 4
The reproducing operation is started by the closing of the circuit, but at this time, the microcomputer in the timing generating circuit 2 is programmed so as to perform the next initial operation. That is, the timing generation circuit 7 is operated by the operation control signal MC, the clock CL2, the address signal Ad2, and the read / write switching signal (R / −) of “L” instructing the read operation.
W2). Further, it generates an operation clock CK5 of the image data decompression circuit 22 for restoring the compressed image data to non-compressed image data, a clock CL1 for the semiconductor memory 12, and an address signal Ad1. Further, the switches 10, 16, and 18 are closed in the direction opposite to the illustrated direction by the switch control signals SW1, SW2, and SW3. Note that the operation end signal ME is kept “L” at time T1 by the timing generator 7 starting the initial operation.

Here, as shown in FIG. 8, it is assumed that the external device is instructed by the preparation status instruction signal CSSa shown in FIGS. The state detection signal SD is also generated by the operation of the AND gate 23b shown in FIG. 4 or FIG.
Is not inverted to “H”. Therefore, switch 1
1 and 15 maintain the state shown in FIG. 1 and the image data is read from the data input / output terminal I / O of the semiconductor memory 13;
After being processed by the image data decompression circuit 22, the switch 16
Is supplied to the semiconductor memory 12 via the. At this time, the clock CL1 and the address signal Ad1 from the timing generation circuit 7 are supplied to the semiconductor memory 12 as the write clock WC and the write address signal WA, respectively.

The above is the initial operation of the reproduction mode. Next, the operation of reading image data from the semiconductor memory 12 will be described.

In this case, the clock CL and the address signal Ad output from the timing generation circuit 2 are supplied to the semiconductor memory 12 as a read clock RC and a read address signal RA, respectively. This data reading is performed by scanning the data area of the field image or the frame image at the scanning speed of the television signal.

The image data read from the semiconductor memory 12 is supplied to an encoder circuit 19 via a switch 18, converted into an analog video signal, and output from an output terminal 20.

In general, when the power supply is stopped, the supply of the operation power is stopped, and in the semiconductor memory 12 which is not backed up, the false data whose level is undefined at the start of the power supply at the time T1 is stored. become. Therefore, in FIG. 8, during the write operation of the data of the image P1, the false data is sequentially rewritten with the data of the image P1.

Here, 1 is set by the image data decompression circuit 22.
The process of restoring image data of a sheet is also limited by the operation speed for the same processing capability as the image data compression process described above. For this reason, generally, compared to the image data read time of one sheet of the semiconductor memory 12 by the clock CL and the address signal Ad from the timing generation circuit 2,
The time required to restore one image data by the image data decompression circuit 22 is longer. Therefore, at time T1, the data reading of the semiconductor memory 12 is started immediately by the clock CL and the address signal Ad from the timing generating circuit 2, and when the encoder 19 generates a video signal from the read image data, the connection to the output terminal 20 is established. First, on the display device such as a television monitor device, a fake image based on the above fake data, which is generally a mosaic pattern, is reproduced, and then the image decompressed by the image data decompression circuit 22 is displayed. For example, an image based on the data of P1 is displayed such that the image gradually changes from the upper left corner of the displayed image.

Here, the recording area of the semiconductor memory 12 rewritten with the restored data is known from the state of the address signal Ad1 from the timing generation circuit 7, and the image data from the other area is output from the semiconductor memory 12. At this timing, for example, the input level of the encoder 19 is held at a predetermined value, thereby preventing the output of the video signal signal due to the false data at the time of rewriting. For example, a portion of the screen where the rewriting has not been completed can be displayed in gray. It is also possible to adopt a different configuration. Also, without stopping the power supply, at the time of the subsequent update of the reproduced image,
The previously selected image is displayed so as to gradually change to the newly selected image.

As is clear from the above description, the image information output from the output terminal 20 has a period in which a plurality of images are mixed. However, the television monitor connected to the output terminal 20 has a specific configuration. Since it is not a device used to take out one image, there is no problem even if mixed images are transiently output, and it is better for the device to be able to display the process of updating images on the monitor display instead. Since the operation status can be grasped, it is often preferable.

When the writing of the data of the image P1 to the semiconductor memory 12 is completed, the timing generation circuit 7 stops generating the clocks CL1 and CL2, the semiconductor memory 12 enters the data holding mode of the image P1, and 13 is stopped. Further, the timing generation circuit 7 outputs an operation end signal ME of “H”. At this time, as shown in FIG.
Is "H" and indicates a preparation state for signal transmission / reception by an external device, the state detection circuit 23 generates a state detection signal SD of "H". Thereby, the switches 11, 1
5 is switched in the direction opposite to the direction shown in FIG. 1, so that the external device connected to the connector 14 can access the semiconductor memory 13.

Here, a clock CL3, an address signal Ad3, and a read / write switching signal (R / -W3) of "L" designating data writing are supplied from the external device, and data of the image Pext is supplied from the external device. Switch 15
8B, the data of one or more images can be written to the semiconductor memory 13 at the timing indicated by Pext shown in FIG. 8B. Further, an image P1 shown in FIG.
After the completion of writing, the preparation status instruction signal CSSa is
Unlike in the case of (1), when it remains at "L", both the semiconductor memories 12 and 13 are in the data holding state, and in this state, the recording trigger switch 5 is closed at time T2 to instruct the selection of the next image. Immediately, the timing generation circuit 2 outputs the operation control signal MC to execute the operation of writing the image P2 into the semiconductor memory 12.

In this embodiment, the output of the operation control signal MC can be suspended during the period in which the state detection signal SD is "H" even during the reproduction operation, similarly to the above-described imaging operation. 8, when the state detection signal SD becomes “H” before the time T2, the transmission / reception operation end signal CSS indicating the end of the signal transmission / reception operation from the external device
b is supplied until the state detection signal SD returns to “L”, the semiconductor memory 12 is kept in the data holding state, and when the state detection signal SD is inverted to “L”, the image P is automatically displayed.
Writing to the second semiconductor memory 12 can also be executed. If the image P2 is rewritten in the semiconductor memory 13 at the timing of the previous Pext, the rewritten image is written in the semiconductor memory 12.

In the case where signals are not transmitted / received to / from the external device in the connection state of the external device, the preparation status instruction signal CSSa need only be kept at “L”.
For example, when the voltage signal SV from the fitting detection switch 24 is used in place of the preparation state instruction signal CSSa as in the state detection circuit 23 shown in FIG. The state detection signal SD immediately returns to “L” by returning the transmission / reception operation end signal CSSb from the external device every time transmission is performed via the external device, so that the operation by the closed circuit of the recording trigger switch 5 can be started. Thus, selection of a reproduced image by operating the recording trigger switch 5 can be performed without delay.

According to the image reproducing operation of this embodiment as described above, during a period in which the image data is read from the semiconductor memory 13 in order to write the reproduced image data to the semiconductor memory 12, the external device transmits the image data to the semiconductor memory 13. Data writing is prohibited, and during execution of data writing from an external device to the semiconductor memory 13, the semiconductor memory 13
Is prohibited from being read from and written into semiconductor memory 12. With such an operation, there is no possibility that data of a plurality of images are mixed in the image data read from the semiconductor memory 13. Therefore, the image data written in the semiconductor memory 12 and the image data read therefrom and displayed on a television monitor or the like are not generated. The content of the image to be read does not change to a different image from the one image stored in the semiconductor memory 13.

Further, the operation of updating the reproduced image by closing the recording trigger switch 5 or the like is made to wait for a period of signal transmission / reception to / from an external device, and the recording trigger switch 5 is continuously mechanically or electrically operated, for example. A timing generating means is used to detect the open / closed state of the recording trigger switch 5 at a predetermined timing, for example, at each timing when the state detection signal SD is inverted from "H" to "L". By programming the microcomputer of the circuit 2, this embodiment can be operated so that an image written from an external device can be reproduced immediately and automatically. An equivalent feature is
Further, even if the signal transfer operation end signal CSSb is used instead of the closing signal of the recording trigger switch 5,
realizable. At this time, when the semiconductor memory 13 is to record a plurality of images, an image input from an external device is made into one image by one writing operation, and the written image and the image to be read are matched. For this purpose, means for detecting an address signal supplied from an external device and loading the start address into a counter for generating an address signal Ad2 arranged in the timing generation circuit 7 is also used.

Note that the state detection signal SD shown in FIG.
Is "H", regardless of whether the camera is in the imaging mode as described with reference to FIGS. 4 and 5 or in the playback mode as described with reference to FIG. By inverting the level of R / -W3), data writing from the external device to the semiconductor memory 13 or data reading from the semiconductor memory 13 to the external device can be executed. The state detection circuit 23 also outputs a state detection signal from the state detection circuit 23 during a combination operation of the operation mode of this embodiment and the write access or the read access to the semiconductor memory 13 by the external device, which is not described in FIGS. The control operation described with reference to FIGS. 5 and 8 by the signal SD, that is, the data write access to the semiconductor memory 13 (in the imaging mode) or the data read access from the semiconductor memory 13 (in the reproduction mode) by the internal operation of this embodiment. During execution of the process, access to the semiconductor memory 13 by an external device is prohibited, and
During the execution of the access to the semiconductor memory 13, a plurality of image data are stored in the storage area of the semiconductor memory 13 allocated to the data of one image by the control operation for inhibiting the access to the semiconductor memory 13 by the internal operation of this embodiment. Can be prevented.

As described above, in the embodiment shown in FIG. 1, the semiconductor memory 13 is accessed by the operation started in conjunction with the closing of the recording trigger switch 5, ie, the imaging operation or the reproducing operation. At times, access to the semiconductor memory 13 from an external device is completely prohibited.

Incidentally, the access of the semiconductor memory 13 by this internal operation is, as is clear from the description of the above-described embodiment, a memory area for one screen of image data in the semiconductor memory 13 for each closing of the recording trigger switch 5. Only executed by accessing. Therefore, when the semiconductor memory 13 stores a plurality of pieces of image data, the expected effect is obtained even if the above-described access prohibition control is limited to the memory area for the data of one image. can get.

FIG. 9 is a block diagram showing a main part of another embodiment of the image pickup apparatus according to the present invention which can realize such a control operation, wherein 11A and 11B are switches, 13A and 1B.
3B is a semiconductor memory, 15A and 15B are switches, 23
A, 23B and 34 are state detection circuits, 35 is a selection signal generation circuit, 36 and 37 are AND gates, 38 to 42 are OR circuits, 43 to 45 are inverters, and the portions corresponding to those in FIG. I'm wearing it.

In FIG. 9, the left half portion of FIG. 1, that is, the respective portions of the timing generation circuit 2, the semiconductor memory 12, the image sensor 1, the camera signal processing circuit 17, and the encoder 19 are the same, and therefore are omitted. ing. Also, the switch 11, the semiconductor memory 13, the switch 15, and the state detection circuit 23 in FIG. 1 are each two, that is, the switches 11A, 1
1B, semiconductor memories 13A and 13B, switch 15A,
15B, and state detection circuits 23A and 23B are provided. Although not shown in FIG. 9, the timing generation circuit 7 includes a clock CL1 and a clock CL1 as shown in FIG.
An address signal Ad1 is also generated.

This embodiment is characterized in that the semiconductor memory 13
Is independently arranged for each image to be stored, so that access control of image data can be executed independently for each image data. In this embodiment,
The number of images to be stored is two. For this reason, as described above, the semiconductor memory 13 and the switch 1 shown in FIG.
1 and 15 and the state detection circuit 23 are provided in two systems.

Here, each of the semiconductor memories 13A and 13B for storing data of one image is composed of one (or a plurality) of commercially available semiconductor memory ICs. Generally, a chip enable terminal CE is provided, and operates at a logic level of a chip enable signal supplied to this terminal, for example, when it is at "H", by a clock CL, an address signal Ad, and a read / write switching signal (R / -W). When it is "L", it has a function of not accepting any of the above operation control and of setting the input / output impedance of the data input / output terminal I / O to high impedance and disconnecting it from an external circuit. In this embodiment, the semiconductor memory 13A, 13B is selected by using such a function.

For this purpose, in this embodiment, the operation control signal MC supplied to the timing generation circuit 7 via the AND gate 6 is also supplied to the selection signal generation circuit 35 composed of a counter or a shift register. You. The selection signal generating circuit 35 is provided with the semiconductor memories 13A, 13B
Select signals S1 and S2 for selecting.

In this embodiment, the access to the semiconductor memories 13A and 13B is performed in units of one image, as in the embodiment described above.
S2 does not simultaneously reach a logic level for selecting the semiconductor memories 13A and 13B (here, the selection level is set to “H”). Also, the semiconductor memory 1
Preparation status indication signal C which becomes "H" when selecting 3A
SSa1 and a preparation status instruction signal CSSa2 which becomes “H” when the semiconductor memory 13B is selected are supplied through the connector 14.

Here, the timing generation circuit 7 accesses the semiconductor memory 13 in response to the operation control signal MC supplied from the timing generation circuit 2 in conjunction with the closing of the recording trigger switch 5 shown in FIG. At this time, in the selection signal generation circuit 35, the 1
Times, the selection signal S1 becomes “H” and the selection signal S
2 becomes “L”, and the next closing of the recording trigger switch 5 causes the selection signal S1 to go to “L” and the selection signal S2 to become “H”. S1 and S2 return to the initial levels, and thereafter, changes in the levels of the selection signals S1 and S2 are:
The above operation is repeated every time the recording trigger switch 5 is closed.

The selection signals S1 and S2 are supplied to AND gates 36 and 37, respectively, and become "L" when the operation of the timing generation circuit 7 starts.
In order to maintain the levels of the D gates 36 and 37, the operation end signal ME is inverted by an inverter 43 and supplied to the AND gates 36 and 37. The output signals of the AND gates 36 and 37 are passed through OR circuits 38 and 39, respectively, and output as chip enable signals to the semiconductor memory 1.
It is supplied to the chip enable terminals CE of 3A and 13B.
Thus, each time the timing generation circuit 7 performs an operation by closing the recording trigger switch 5, the semiconductor memories 13A and 13B are alternately selected.

The selection signals S1 and S2 are inverted in level by inverters 44 and 45, respectively, and
It is supplied to the state detection circuits 23A and 23B via 42. Also, the operation end signal ME is output from these OR circuits 41,
It is supplied to the state detection circuits 23A and 23B via 42. As a result, the output signal of the OR circuit 41 becomes “L” only while the semiconductor memory 13A is being accessed by the timing generation circuit 7, and becomes “H” during other periods. Similarly, the output signal of the OR circuit 42 is also
Is "L" only during the period when it is being accessed by the timing generation circuit 7, and "H" during the other periods. The output signals of these OR circuits 41 and 42 are supplied to the state detection circuits 23A and 23A.
B is an alternative to the operation end signal ME in the state detection circuit 23 in FIG.

The state detection circuit 23A is supplied with a preparation state instruction signal CSSa1 from an external device, and the state detection circuit 23B is supplied with a preparation state instruction signal CSSa2. These preparation state instruction signals CSSa1 and CSSa2 are provided in FIG. Preparation state indication signal CSS supplied to the state detection circuit 23 of FIG.
It is the same as a. Further, the transfer operation end signal CSSb from the external device is supplied to both the state detection circuits 23A and 23B.

Here, the external device is the semiconductor memory 13A.
Is accessed, the preparation status indication signal CSSa1
When the semiconductor memory 13B is accessed, the preparation status instruction signals CSSa2 are set to "H", but these are not set to "H" at the same time. In addition, even when the external device accesses one of the semiconductor memories 13A and 13B, the external device generates a pulse-like transfer operation end signal CSSb as shown in FIG. 5 every time the access operation of the selected semiconductor memory ends. .

With the above configuration, state detection circuit 23A performs the same operation as state detection circuit 23 shown in FIG. 4, and when semiconductor memory 13A is being accessed by timing generation circuit 7, the state of preparation state instruction signal CSSa1 is Regardless of this, the state detection signal SDa is held at “L”,
When this access is not made, the state detection signal SDa can be switched to "H" by setting the preparation status instruction signal CSSa1 to "H".

When the state detection signal SDa is "H", the switches 11A and 15A are switched to switch the semiconductor memory 13A.
Of the semiconductor memory 13A via the OR circuit 38 to make it operable. Further, the semiconductor memory 1 is connected to an external device via the OR circuit 40.
3 is in an accessible state. The semiconductor memory 13B also operates by the operation of the state detection circuit 23B.
Similarly, access is switched.

The state detection signals SDa and SDb further include:
It is also supplied to the state detection circuit 34. In the embodiment shown in FIG. 1, the state detection signal SD output from the state detection circuit 23 is supplied to the AND gate 6 via the inverter 9, and the state detection circuit 23 controls the operation of the timing generation circuit 2. Although it is used for the control to wait for the output of the signal MC, in this embodiment shown in FIG.
This operation is performed using the state detection circuit 34.

That is, the state detection circuit 34 outputs the selection signal S
The semiconductor memory to be selected by the selection signal generating circuit 35 in the next operation based on the levels of S1 and S2 is the semiconductor memory 13A.
Or the semiconductor memory 13B can be detected, and the semiconductor memory 13A, 13B by an external device is determined by the logic level of the state detection signal SDa or SDb.
Semiconductor memory 13 that knows the selection status of
If A or 13B is not being accessed by an external device, the operation starts immediately, and if it is being accessed, the operation waits or the semiconductor memory 13A, 13B
The operation is started by selecting the non-accessed one of B.

FIG. 10 is a block diagram showing a specific example of the state detection circuit shown in FIG.
The D gate 34c is a NOR circuit, and portions corresponding to those in FIG.

In the figure, if the selection signal S1 is now "H", the selection signal generation circuit 35 sets the selection signal S2 to "H" and the selection signal S1 to "L" when the next operation control signal MC is input. When the selection signal S2 is "H", the selection signal S1 is switched to "H" and the selection signal S2 is switched to "L" when the next operation control signal MC is input.

Therefore, in the state detection circuit 34, the selection signal S2 and the state detection signal SDa are connected to the AND gate 34a.
And the selection signal S1 and the signal SDb are connected to the AND gate 34b.
When the semiconductor memory 13A or 13B currently accessed by the external device matches the semiconductor memory 13A or 13B to be accessed by the next operation of the timing generation circuit 7. , "H" from one of AND gates 34a, 34b
Is output. At this time, since the output signal of the NOR circuit 34c becomes "L", the passage of the operation control signal MC is blocked by the AND gate 6, and the above described state detection signal SDa or SDb becomes "L". The standby operation state is set until the coincidence state is released.

In the embodiment shown in FIG. 9, a total of two images are stored, one for each, in the two systems of semiconductor memories 13A and 13B. 11, 15 and the state detection circuit 2
3. By adding a circuit configuration including the OR circuit 38 and the like, two or more images can be stored. At this time, the state detection circuit 34 may be one,
FIG. 11 shows a specific example of the state detection circuit 34 when the N-system semiconductor memory 13 is used. However, in the figure,
341, 342, 343, 344,..., 34N are shown in FIG.
This is an AND gate corresponding to the AND gates 34a and 34b at 0, and the portions corresponding to those in FIG.

In FIG. 11, N semiconductor memories 13
The selection signal generation circuit 35 in which the number of stages of the counter or the shift register is set corresponding to the N selection signals S
1, S2, S3, S4,..., SN, which are AND gates 341 and 342 of the state detection circuit 34, respectively.
, 343, 344,..., 34N. Although not shown, N circuits corresponding to the state detection circuits 23A, 23A of FIG. 9 are provided, and the state detection signals SD1, SD2, SD3, SD4,... , 342, 343, 344, ...
.., 34N. With this configuration, when the system of any of the semiconductor memories 13 to be accessed is being accessed by the external device by the next operation of the timing generation circuit 7, the operation of the timing generation circuit 7 is put on standby. be able to.

In FIGS. 10 and 11, the selection signal generating circuit 35 has an initial reset signal INS at power-on.
Is supplied, and the above-mentioned counter and the like are reset to set a selection signal in an initial state (generally, the first selection signal S1 is set to “H”).

Further, the counter of the selection signal generation circuit 35 in FIG. 10 or 11 is added with a digital addition circuit for adding 1 to the current count number and a function of loading the addition result into this counter. When the output signal of the circuit 34c is “L” and the operation control signal MC is inverted from “L” to “H”, the above-mentioned loading is executed, so that the AND gate 6
When the operation control signal MC blocks, the selection signal generation circuit 35 automatically counts up and the NOR circuit 34c
Is released, and the selection signal generating circuit 35 is counted up again by the operation control signal MC passing through the AND gate 6 by this release, whereby the semiconductor device not accessed by the external device is released. It becomes possible to select a memory system and execute writing.

As described above, even if the semiconductor memory 13 is divided into a plurality of memory blocks which can be accessed independently, the same effects as those of the embodiment shown in FIG. 1 can be obtained. When one of the memory blocks is being accessed by an external device,
It is also possible to automatically select the memory block that has not been accessed and execute access to the semiconductor memory 13 by an imaging operation or a reproduction operation. Therefore,
In the case where the semiconductor memory 13 having a recording area for a plurality of images is employed, even when the external device accesses the semiconductor memory 13, the recording area other than the recording area currently being accessed by the external device is stored in the recording area. A plurality of images can be taken and recorded.

In the embodiments shown in FIGS. 1 and 9, the recording trigger switch 5 for starting the operation is arranged in the apparatus. However, the present invention is not limited to this. The operation can be started by a remote controller that uses an external device, or an operation start can be commanded from an external device connected to the connector 14.

In the embodiment shown in FIGS. 1 and 9, instead of the semiconductor memory 13, a memory means such as a magnetic disk may be employed.
It can be configured to execute the switching control of these memory accesses.

Further, in the embodiment shown in FIGS. 1 and 9, the image data is compressed or decompressed.
Such a function is not essential in the present invention. Although the semiconductor memory 12 is used as the buffer memory, the semiconductor memory 12 is not essential in the embodiment having no image data compression / decompression function, and the captured image information is recorded in the semiconductor memory 13 in real time. May be configured.

Further, the semiconductor memory 13, 13A, 13B shown in FIGS.
When using flash memory devices that generate busy signals, the ready / busy signals they generate
A signal obtained by performing an OR operation with the state detection signals SD, SDa, and SDb may be transmitted to an external device via the connector 14.

Further, referring to FIG.
A switch corresponding to the switch 11 is further provided between the semiconductor memory 12 and the data input terminal I and the data output terminal O of the semiconductor memory 12 to switch between the connection relationship shown in FIG. A switch that can be selectively connected to the connection relationship with an external device through the switch is provided, and this switch is used to replace the signal indicating the operation state of the timing generation circuit 2 with the operation end signal ME or the operation end signal ME. In addition, by being configured to switch according to the output signal of the state detection circuit 23 used,
Writing uncompressed image data from an external device to the semiconductor memory 12, compressing the compressed image data by the image data compression processing circuit 21, and writing the compressed data to the semiconductor memory 13,
The compressed image data from the external device is written into the semiconductor memory 13 and is written into the image data decompression circuit 12.
5 and temporarily stored in the semiconductor memory 12, and thereafter, the image information restored from the semiconductor memory 12 can be read out to an external device. Also,
At this time, the access of the semiconductor memory 12 which is started by the user operating the recording trigger switch 5 at an arbitrary timing and the access of the individual semiconductor memory 12 by the external device also overlap with each other. Therefore, data of a plurality of images are not mixed in one image data.

FIG. 12 is a diagram showing an external view and an example of use of an embodiment of an image pickup apparatus according to the present invention. Here, 46 is an imaging device according to the present invention, 47 is a light receiving lens for imaging, 48 is a finder similar to a conventional film camera, and 49 is a lens hood.

FIG. 12A shows the appearance of an image pickup apparatus, which is provided with a light receiving lens 47 for image pickup, a finder 48, and a lens hood 49 similar to those of a conventional film camera. Also, similarly to the conventional film camera, a recording trigger switch 5 is provided on the upper left side in the figure, and a connector 14 is mounted on the right side in the figure. Here, when the semiconductor memory 13 which is irremovably built in the device is used, the thickness D shown in the figure can be made extremely thin.

FIGS. 12B to 12E show an example in which an external device is a personal computer PC, and an image pickup device 46 is mounted on the personal computer PC for use. FIG. 14 is a personal computer PC
Shows the case of connecting directly to the internal socket.

FIG. 12C shows the connector 1 of the image pickup device 46.
4 shows an example in which the personal computer 4 is connected to a personal computer PC via a socket 50 and a cable 51.

FIG. 12D shows a state in which the imaging device 46 is mounted on an adapter 52 having a built-in power supply circuit such as a known AC / DC converter for generating a DC voltage from an AC power supply, and this adapter 52 is connected to a personal computer PC. Things. In this case, for example, operating power is supplied to the imaging device 46 from an operating power input terminal provided on the connector 14, and input / output signals of the connector 14 are supplied to an electric circuit installed inside the adapter 52, for example, electric wiring or a signal buffer. It is connected to a personal computer PC via a circuit or the like. Note that the adapter 52 may include a known DC power supply such as a dry battery, and in this case, the adapter 5
2 is provided exclusively for supplying the operating power,
It can also be used together when used outdoors.

FIG. 12E shows an example in which a personal computer PC is connected to an adapter 53 having a mechanism similar to that of a known desk lamp.
In this case, for example, the image pickup device 46 is installed inside the circle drawn by the fluorescent tubes of the circular fluorescent lamps 54a and 54b, so that the subject illuminated by the fluorescent lamps 54a and 54b is imaged, and the image information is obtained by a personal computer. It can be configured to transmit to a PC.

Here, the connector 14 shown in FIG.
12 (b) to (e) in the operation shown in FIGS. 12 (b) to 12 (e) by defining the terminal position of the device based on the device exterior surface on the side opposite to the direction of the incident light of the imaging light receiving lens 47. When the reference surface is mounted facing the adapter or the like, the direction of the incident light is opened without being blocked, so that the image can be taken with the personal computer PC or the adapter mounted.

[0143]

As described above, according to the present invention,
The image reproduction read from the second memory means and reproduced by the monitor device can be updated by operating the reproduced image update instruction means, and the connection between the external device and the second memory means via the connector. When the image signal is transmitted and received between the devices, the reproduced image cannot be updated even if the reproduced image update instructing means is operated. There is no change due to the image transferred between the two memory means, and the usability is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an imaging device according to the present invention.

FIG. 2 is a schematic diagram showing a FIFO type memory used in a conventional imaging device.

FIG. 3 is a timing chart showing an operation of the semiconductor memory in FIG. 1;

FIG. 4 is a block diagram illustrating a specific example of a state detection circuit in FIG. 1;

FIG. 5 is a timing chart showing a signal transfer function with the external device of the embodiment shown in FIG. 1 and an operation of the state detection circuit shown in FIG. 4;

FIG. 6 is a block diagram showing another specific example of the state detection circuit in FIG. 1;

FIG. 7 is a timing chart showing an operation of the state detection circuit shown in FIG. 6;

FIG. 8 is a timing chart showing an image reproducing operation of the embodiment shown in FIG. 1;

FIG. 9 is a block diagram showing a main part of another embodiment of the imaging apparatus according to the present invention.

FIG. 10 is a block diagram illustrating a specific example of a state detection circuit in FIG. 9;

FIG. 11 is a block diagram showing another specific example of the state detection circuit in FIG. 9;

FIG. 12 is a diagram showing an appearance of an embodiment of an imaging apparatus according to the present invention and an example of its use.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image sensor 2 Timing generation circuit 4 Power switch 5 Recording trigger switch 7 Timing generation circuit 10, 11, 11A, 11B Switch 12, 13, 13A, 13B Semiconductor memory 14 Connector 15, 15A, 15B, 16 switch 17 Camera signal processing circuit Reference Signs List 18 switch 19 encoder 20 output terminal 21 image data compression processing circuit 22 image data decompression processing circuit 23, 23A, 23B state detection circuit 24 fitting detection switch 25 external device 34 state detection circuit 35 selection signal generation circuit

Claims (4)

[Claims] 1. An imaging device to which an external device can be connected, comprising: imaging means for generating an image signal from an optical image; first memory means for storing the image signal generated by the imaging means; Compression means for compressing the image signal stored in the first memory means to generate a compressed image signal; second memory means for storing the compressed image signal; and compression means stored in the second memory means. Decompressing means for decompressing an image signal; reproduced image update instructing means for instructing an update of a reproduced image of a monitor device for displaying the decompressed image signal; a connector enabling connection of the external device; While writing the compressed image signal from the external device connected to the second memory means to the second memory means, even if the reproduced image update instructing means is operated, the compressed image data stored in the second memory means is signal Imaging apparatus characterized by comprising a control means for controlling to read is not performed. 2. An imaging apparatus to which an external device can be connected, comprising: imaging means for generating an image signal from an optical image; first memory means for storing the image signal generated by the imaging means; Compression means for compressing the image signal stored in the first memory means to generate a compressed image signal; second memory means for storing the compressed image signal; and compression means stored in the second memory means. Decompressing means for decompressing an image signal; reproduced image update instructing means for instructing an update of a reproduced image of a monitor device for displaying the decompressed image signal; While writing the compressed image signal from the external device connected to the second memory means to the second memory means, even if the reproduced image update instructing means is operated, the compressed image data stored in the second memory means is signal Control is performed so that reading is not performed, and further, no compressed image signal is exchanged between the second memory means and the external device while the external device is connected via the connector. An imaging apparatus comprising: control means for controlling the updating of a reproduced image on the monitor device when the reproduced image update instruction means is operated. 3. An image pickup apparatus to which an external device can be connected, wherein: an image pickup means for generating an image signal from an optical image; a memory means for storing the image signal generated by the image pickup means; Reproduced image update instructing means for instructing an update of a reproduced image of a monitor device for displaying a stored image signal; a connector enabling connection of the external device; and an image from the external device connected via the connector Control means for controlling not to read out the image signal stored in the memory means even if the reproduced image update instruction means is operated while the signal is being written to the memory means. An imaging device characterized by the above-mentioned. 4. An image pickup apparatus to which an external device can be connected, wherein: an image pickup means for generating an image signal from an optical image; a memory means for storing the image signal generated by the image pickup means; Reproduced image update instructing means for instructing an update of a reproduced image of a monitor device for displaying a stored image signal; a connector enabling connection of the external device; and an image from the external device connected via the connector While the signal is being written to the memory means, even if the reproduced image update instructing means is operated, control is performed so that the image signal stored in the memory means is not read out. When no image signal is exchanged between the memory unit and the external device while the external device is connected, the reproduced image update instruction unit is operated. When the imaging apparatus characterized by updating the reproduced image in the monitoring device and control means for controlling to occur.