JP2004129294A - Image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate memory access from an external device, and to prevent image information from being modified. <P>SOLUTION: When a record trigger switch 5 is operated, one image outputted from a camera signal processing circuit 17 at that time is written into a semiconductor memory 12, and further, the written image is subjected to data compression by a data compression circuit 21 and stored in a semiconductor memory 13. In this case, if an external device (not shown) is connected to a connector 14, even if the external device instructs to fetch an image of the memory 13 while the memory 13 is writing the image, a state detection circuit 23 detects it and inhibits the external device from fetching the image. Also, while an image of the memory 13 is fetched into the external device even if the circuit 23 detects it and operates the switch 5, an AND gate 6 is turned off and image writing into the memory 13 is inhibited. <P>COPYRIGHT: (C)2004,JPO

Description

The present invention relates to an imaging device that electronically records an optical image of a subject as an image information signal, and particularly to an operability in a case where the image information signal is exchanged between devices by connecting to peripheral devices. To an imaging device.

As a conventional device of this type, there is a so-called electronic camera, and as one example, there is a digital still camera (for example, see Non-Patent Document 1).

As another example, there is a DS-100 type camera (for example, see Non-Patent Document 2).

In the electronic cameras described in Non-Patent Documents 1 and 2, for example, as shown in FIG. 1 of Non-Patent Document 1, an image information signal obtained by an image pickup device is digitized (quantized), and a semiconductor memory is used. It is recorded on a mounted card (hereinafter referred to as a memory card).

As described above, in Non-Patent Documents 1 and 2, the image information signal is handled as a digital signal, so connection with peripheral devices such as a personal computer that handles digital signals exclusively (without passing through an analog / digital converter or the like). It is shown that the connection with other systems is good, for example, it is easy (because a digital signal can be directly transmitted and received) and there is no image quality deterioration due to the transmission path.

Although Non-Patent Document 1 does not describe a specific example regarding connection with peripheral devices, it is understood that a memory card is used as an intermediary medium. Non-Patent Document 2 discloses an example of using such a memory card. That is, the memory card is first mounted on the electronic camera to record image information signals, and then the memory card is removed from the electronic camera, mounted on a peripheral device separate from the electronic camera, and recorded on the memory card. The peripheral device reads the image information signal. Also in this case, as a method of transmitting the image information recorded in the memory by the electronic camera as a digital signal to a peripheral device (without passing through a digital / analog converter or an analog / digital converter, etc.), the above-described memory card is used. No method other than the medium method is disclosed.

{Circle over (2)} As a known device that is connected to a personal computer or the like to electrically transmit and receive image information signals, there is an FSA2001 type still image compression / expansion substrate (for example, see Non-Patent Document 3).

The device described in Non-Patent Document 3 has a built-in semiconductor memory for storing a digital image information signal, and is connected between the device and a personal computer connected via a connector, a cable or the like to the semiconductor memory. The digital image information signal is to be stored, or an already stored digital image information signal is transmitted and received as a digital signal.

In the case of Non-Patent Documents 1 and 2, it is a camera device, which has an image pickup means for generating an electrical image information signal from an optical image, whereas in the case of Non-Patent Document 3, it has such a means. Instead, the creation of the image information signal is performed by a personal computer. The image information signal generated by the personal computer is transmitted to the device described in Non-Patent Document 3 and temporarily stored in the first memory. Next, the image information signal read from the first memory is subjected to image data compression processing by DCT (Discrete Cosine Transform), and is sent back to the personal computer. Such an operation is similar to the operation of the device block shown in FIG.

Here, since the writing or reading operation of the image information signal in the device described in Non-Patent Document 3 is performed under the time management of the connected personal computer, the writing of the information data in the first memory is performed. The inconvenience such that the contents are switched to the data of another image while the data of one image is being read due to the overlap between the reading and the reading, etc., and as a result, the image information is transformed It can be avoided beforehand.

In the device described in Non-Patent Document 3, when the above-described image data is compressed and the compressed image information signal is output, data output from the device to a personal computer is synchronized with a clock output from the personal computer. The compression processing of image data is performed by an independent clock inside the apparatus, that is, a clock asynchronous with the clock output from the personal computer. Therefore, a so-called FIFO (Fast In / Fast Out) type buffer memory is used. It has.

Here, the operation of the FIFO type memory will be described with reference to FIG.

In the figure, the FIFO type memory 21 has a data storage area of memory addresses 0, 1, 2,..., N, n + 1,. When the memory 21 starts operating, data is written in the order of addresses 0, 1, 2,.... The update of the write address is performed at each repetition timing of the clock in the device. When data is written to address n, data reading is started from address 0 at this timing, and data is read in the order of 1, 2,. The update of the read address is performed at each repetition timing of the external clock supplied from the personal computer to the above device. Thereafter, the read address is also updated so as to follow the sequentially updated write address. In both writing and reading, when the address reaches address m, control is performed so that the address returns to address 0 again at the next clock timing.

When the FIFO type memory is operated as described above, the initial address offset amount between writing and reading is Aos (= n), and the writing and reading addresses when the writing address is the last m address of the buffer memory. Assuming that the offset amount is A'os (= m−n) and the repetition period of the external read clock is T, the timing of the write clock relative to the generation timing of the read clock is Aos × T at the maximum in the delay direction and the advance direction. Therefore, even if the values are shifted from each other by a maximum of A'os × T, data can be correctly read out in the order written in the memory. In other words, data transfer can be performed correctly between systems operating with asynchronous clocks by interposing a FIFO buffer memory.

However, when the FIFO type memory is used, a write clock (in the compressed data output operation mode of the device described in Non-Patent Document 3 and a clock inside the device) and a read clock (in the same mode, a personal computer transmits the data to the device). The supplied clock cannot be set without any correlation. For example, the difference in the repetition frequency between clocks is a limiting factor due to the amount of address offset regulated by the capacity of the buffer memory used, and the start timing of the read operation is time-managed with respect to the timing of the write operation. It must be.

The device described in Non-Patent Document 3 further receives a compressed image information signal from a personal computer, restores the original uncompressed image information signal by an internal data decompression circuit, and stores it in the first semiconductor memory. It also has a function of storing and then sending back the restored image information signal to the personal computer. Even in such an operation, the operation timing of this apparatus is executed under the control of the connected personal computer, so that the image information signal supplied from the computer and not subjected to the compression processing to the first semiconductor memory is written. And writing of the restored image information signal into the memory can be avoided beforehand.

In such an operation, the FIFO memory operates using a clock supplied from a personal computer as a write clock and using a clock inside the device as a read clock. The relationship between the two clocks is as follows. This is the same as the case of the output operation of the compressed image information signal described above.

In the device described in Non-Patent Document 3, the FIFO memory is connected so that an operation mode in which writing by the clock inside the device and writing by the clock from the personal computer do not overlap in time occurs. A personal computer program to be used is configured.
"A Journal of the Television Society," Vol. 46, No. 3 (1992), pp. 300-307, a paper by Sasaki et al. Catalog "FUJIX DIGITAL STILL CAMERA SYSTEM" published by Fuji Photo Film Co., Ltd. (September 1991) "FSA2001 Overview Information Material" issued by Fujifilm Micro Devices, Inc. (June 24, 1991)

By the way, the electronic circuits for imaging devices such as electronic cameras shown in Non-Patent Documents 1 and 2 can be realized with extremely small circuit blocks by using recent high-integration LSI technology and high-density substrate mounting technology. For this reason, particularly when a small camera using a single focus optical lens or the like is to be manufactured, the method using a memory card disclosed in the above-mentioned non-patent document uses a space for accommodating the memory card and a memory card loading device. The space for mounting the connector for the camera or the space for the mechanism for removing the memory card is a major factor that hinders miniaturization.

In addition, it is conceivable to reduce the size of the device and the memory card, but it is troublesome to remove a smaller memory card from the miniaturized device, and the device is accidentally dropped during removal. For example, the device may be destroyed.

The above-described inconvenience due to the insertion / removal of the memory card can be solved by providing a connector for inputting / outputting image information signals in the image pickup apparatus and directly transmitting / receiving signals to / from an external device via the connector. . However, the image pickup apparatus is provided with a recording switch corresponding to a shutter button of a conventional film camera, and by closing the recording switch, an arbitrary operation desired by an operator and an external device connected to the connector are performed. There is a case where an operation of capturing an optical image into the apparatus at a timing that is not restricted by the operation state of the device and recording it as an electric signal in the semiconductor memory is executed or desired to be executed. For example, when an external device is attached to the connector after the recording switch is closed and the recording operation in the apparatus is not yet completed, or when an image is recorded without missing a photo opportunity at a certain moment. is there. Therefore, when the connector as described above is provided in the image pickup apparatus, it is necessary to prevent the change of the image content due to the overlapping of the writing and reading of the information in the semiconductor memory, or to write the information by operating the recording switch. In order to avoid the inconvenience of competing the writing of information input from an external device with the writing of information input from an external device in the same semiconductor memory and changing the image content, all the device operations are centrally managed by a computer. A new operation management different from the device described in Non-Patent Document 3 is required.

Further, a personal computer can be considered as an external device for exchanging image information with the imaging device. In this case, an information transmission clock that is completely uncorrelated with a system operation clock inside the imaging device is input from the personal computer to the imaging device. If information can be transmitted and received by the user, it is extremely effective in terms of versatility and operability.

目的 An object of the present invention is to provide a small-sized imaging device which prevents malfunctions and has excellent versatility and operability in consideration of the above points.

In order to achieve the above object, the present invention provides a semiconductor memory, a device operation start instructing means such as a recording switch, and an image information signal obtained by imaging in cooperation with an operation start instruction by the device operation start instructing device. For outputting an image information signal stored in the semiconductor memory to the outside of the device or for inputting a signal to be stored in the semiconductor memory to the inside of the device. And detecting that the first connector has been fitted to a second connector of the external device or the like, or detecting a signal supplied from the external device via the first connector. By detecting the state, the first state in the state of preparation for image information exchange with the external device or the state of execution of image exchange is detected, and State detecting means for detecting a second state in a writing operation state of the image information signal to the semiconductor memory in conjunction with the operation of the recording switch, when the state detecting means detects the first state, Writing of a new image information signal to the semiconductor memory in conjunction with closing or the like is prohibited, and when the state detecting means detects the second state, the state changes to an execution state of image information exchange with an external device. To prohibit migration.

The state detecting means includes, for example, a switch that is pressed and closed when the first connector and the second connector are fitted, and this switch outputs an electric signal while these connectors are in the fitted state. I do. Alternatively, for example, after the above-described connectors are fitted, a signal input from at least an external device via the connectors and before execution of image signal exchange with the external device is detected, and an electric signal is output. However, during the period when the semiconductor memory is in the image information signal writing operation mode in conjunction with the closing of the recording switch or the like, the imaging device is prohibited from outputting the electric signal.

The present invention is directed to a semiconductor memory to be accessed for transmitting and receiving an image information signal to and from an external device when an output electric signal of the state detection means is present. Is controlled to prohibit writing.

According to the above operation, in the present invention, when image information is exchanged with an external device, even if a user accidentally operates the recording switch, the image information is exchanged. The content of the existing image does not change. Further, for example, by providing a buffer memory for temporary storage in a preceding stage of the semiconductor memory, it is possible to capture an image even during a signal transfer operation with an external device.

When the output of the electric signal from the state detection means is prohibited, the access state of the semiconductor memory selected to write the image information signal in conjunction with the closing of the recording switch or the like is maintained, and the access from the external device is performed. The transition to a possible state is prohibited.

According to the above operation, in the present invention, even when a series of operations for recording a captured image is continued, a connection operation with an external device or the like can be performed without changing the content of the image.

Further, in the present invention, writing of an image information signal in conjunction with a recording switch, which is an internal operation of the apparatus, and reading / writing of an image information signal, which is an exchange operation with an external device of the apparatus, are performed independently in a time-division manner. Since there is no time constraint in the operation timing between the executed and divided operations, a clock uncorrelated with the system operation clock inside the device can be supplied from outside the device to exchange image information with the device. .

According to the present invention, the memory incorporated in the imaging device for storing the captured image information is provided with a signal switching unit and a signal transmission connector for accessing the memory from outside the device. When information stored in the memory is exchanged with an external device, the device does not need to be detached, so that the device can be downsized.

At the same time, there is provided a means for detecting a preparation state and an execution state of the access operation of the memory from outside of the device, and when such a state is detected, the apparatus is configured to wait for execution of writing of a captured image to the memory. And a means for detecting that writing of the captured image to the memory is in a preparation state or in an execution state. When such a state is detected, an access operation of the memory from an external device is performed. By configuring to wait for execution, an instruction at an arbitrary timing of a writing operation of a captured image by a user's operation can be executed without changing image information, and communication with an external device can be performed. Even if the instruction is given at the time of execution of the signal transfer, the content of the image information being transferred does not change. In addition, when the operation of writing the captured image to the memory is performed, the content of the captured image being written does not change even if the captured image is connected to an external device via the connector.

Further, when the memory has a recording area for a plurality of images, even during a period in which a signal is exchanged with an external device, a write operation of a captured image by a user operation is performed at an arbitrary timing. With this instruction, it is possible to shoot an image at this timing, and to shoot without missing a chance.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of an imaging apparatus according to the present invention, wherein 1 is an imaging device, 2 is a timing generation circuit, 3 is an oscillator, 4 is a power switch, 5 is a recording trigger switch, and 6 is an AND gate. , 7 are a timing generation circuit, 8 is an oscillator, 9 is an inverter, 10 and 11 are switches, 12 and 13 are semiconductor memories, 14 is a connector, 15 and 16 are switches, 17 is a camera signal processing circuit, 18 is a switch, 19 Is an encoder, 20 is an output terminal, 21 is an image data compression processing circuit, 22 is an image data decompression processing circuit, 23 is a state detector, and 24 is a switch.

In FIG. 1, when a user operates a power switch 4 to close a circuit, a timing generation circuit 2 composed of a microcomputer or a logic circuit detects this and operates a power circuit (not shown) to start supplying operation power to each unit. At the same time, the first reference frequency signal supplied from the oscillator 3 is subjected to processing such as frequency division as appropriate, and the operating clock pulses CK1, CK3, CK2 of the imaging device 1, the camera signal processing circuit 17, the encoder 19, It generates switch control signals SW1, SW2, and SW3. By these switch control signals SW1, SW2, SW3, the switches 10, 16, 18 close in the direction shown. These switches 10, 16, and 18 can be easily configured by a known multiplexer circuit based on a logic circuit technique.

(4) An analog image information signal AIS resulting from the photoelectric conversion of an optical image is output from the image sensor 1 in which an optical lens (not shown) is mounted on the light receiving surface. The camera signal processing circuit 17 is composed of circuits known in television cameras, such as a correlated double sampling circuit, an automatic gain adjustment circuit, a matrix circuit, and a gamma processing circuit, and has an A / D (analog / analog) circuit in the signal path of the circuit configuration. A digital) converter is provided for outputting a digitized baseband digital image information signal DIS. This digital image information signal DIS is supplied to an encoder 19 via a switch 18, and a chroma signal modulated into a subcarrier is generated from the baseband digital image information signal DIS, and one of the baseband luminance signal and the clock pulse CK1 is generated. The timing is synchronized with the synchronization signal supplied from the timing generation circuit 2 as a unit, and these are combined and output from the output terminal 20 as a composite video signal or as an independent component signal.

The encoder 19 has a D / A (digital / analog) converter, and outputs an analogized image information signal to an output terminal 20. Here, by connecting a known television monitor device to the output terminal 20, a continuous (moving image) image picked up by the image pickup device 1 can be displayed as a television image.

The above operation is similar to the operation of a known television camera device, and can be realized by using, for example, a commercially available television camera circuit of a VM-H39 type VTR integrated camera manufactured by Hitachi, Ltd.

Next, the operation of the electronic camera function of this embodiment will be described.

The baseband digital image information signal DIS output from the camera signal processing circuit 17 is supplied to the semiconductor memory 12 via the switch 16. At this time, the clock CL and the address signal Ad generated in synchronization with the camera signal processing clock CK3 and the like by the timing generation circuit 2 are supplied to the semiconductor memory 12 via the switch 10, respectively. It is supplied as a signal WA.

3A and 3B are timing charts showing the operation of the semiconductor memory 12. FIG. 3A shows the operation timing of a television camera circuit including the image sensor 1 and the camera signal processing circuit 17, and FIG. FIG. 4C shows the storage timing of the memory 12 and the operation mode of the semiconductor memory 13. Also, P1, P2, P3,... In FIG. 3B represent sequential images (field image or frame image of a television signal) in the image information signal DIS. Images written to the semiconductor memory 12 are also denoted by the same reference numerals.

1 and 3, when the power switch 4 is closed at time T1, the television camera circuit starts the above-described operation, and the image information signal DIS is generated. The semiconductor memories 12 and 13 generally have a memory capacity capable of recording data for one field image or one frame image.

Generally, writing of image data to the semiconductor memory 12 is executed in such a manner that previously written image data is replaced with new data by a predetermined data amount (for example, 8 bits) in time sequence. . Here, when a natural image is recorded by an electronic camera or the like, a data amount of at least a kilobit unit or more is required for each image. Therefore, even after writing of one image data is started, this one image Until the data writing is completed, the previously written image data remains in the semiconductor memory. That is, for example, in FIG. 3B, in the time domain indicated by P2, not only the data of the image P2 is stored in the semiconductor memory 12, but also the data of the image P1 written before it and the current time. The data of the image P2 to be written is mixed and stored.

In FIG. 3, a portion indicated by adding a term “hold” such as “hold P4” indicates that after writing of one image data is completed, writing of new image data (that is, , The image data is stored as it is.

以降 After time T1, in the semiconductor memory 12, the images P1 to P4 generated by the camera signal processing circuit 17 are sequentially written, and the image data is updated each time. Then, when the recording trigger switch 5 is closed by the user (time T2), at this time, when the writing of the data of the image P4 being written is completed, the next data writing to the semiconductor memory 12 is prohibited, and this image is written. The semiconductor memory 12 is controlled so that the data of P4 is held (frozen). This control is executed by the timing control circuit 2 stopping the generation of the clock CL at the timing of the vertical synchronization signal of the image information signal AIS. Subsequently, the timing control circuit 2 generates an operation control signal MC. The operation control signal MC is supplied to the timing generation circuit 7 via the AND gate 6 that is controlled to open and close in accordance with the output signal SD of the state detection circuit 23, as described later, to start the operation.

The timing generation circuit 7 processes the reference signal supplied from the oscillator 8 as appropriate, such as frequency division, to drive the clock CL1 for the semiconductor memory 12, the address signal Ad1, the image data compression processing circuit 21 and the image data decompression processing circuit 22. Operating clocks CK4 and CK5, a driving clock CL2 of the semiconductor memory 13 for storing the compressed image data CID2, an address signal Ad2, and a read / write switching signal (R /-) for controlling switching between a read operation and a write operation. W2), and can be constituted by a known logic circuit. The read / write switching signal (R / -W2) indicates, for example, "read" when "H" (high level) and "write" when "L" (low level). .

(4) Upon receiving the operation control signal MC, the timing generation circuit 7 starts the compression processing of the image data and the operation of writing the compressed image data CID into the semiconductor memory 13.

That is, the clock CL1 and the address signal Ad1 output from the timing generation circuit 7 are supplied to the semiconductor memory 12 via the switch 10 as the read clock RC and the read address signal RA. As a result, the data of the image P4 stored and held is sequentially read from the semiconductor memory 12, and is compressed by the compression processing circuit 21 to obtain compressed image data CID. By using a FIFO type semiconductor memory as the semiconductor memory 12, as described with reference to FIG. 2, reading of the image P4 data can be started even during the data writing period of the image P4 in FIG. Can be. Further, the write clock WC and the read clock RC may be asynchronous.

The compressed image data CID output from the compression processing circuit 21 is supplied to the data input / output terminal I / O of the semiconductor memory 13, and also indicates the clock CL2 output from the timing generation circuit 7, the address signal Ad2, and "write". The read / write switching signal (R / -W2) to be supplied is supplied to the semiconductor memory 13 via the switch 11 as the clock CL, the address signal Ad, and the read / write switching signal (R / -W). As shown in ()), the data of the compressed image P4 is written into the semiconductor memory 13 during the period indicated by P4.

Here, the semiconductor memory 13 is a memory which is switched between a write mode of image data and a read mode by a read / write switching signal (R / -W), and the read / write switching signal (R / -W) is "H". "" Means the write mode. At this time, the data input / output terminal I / O is used for data input, and the clock CL and the address signal Ad are used as a write clock and a write address signal, respectively. When the read / write switching signal (R / -W) is "L", the read mode is set. At this time, the data input / output terminal I / O is used for data output, and the clock CL and the address signal Ad are used as a read clock and a read address signal. A semiconductor memory circuit that is used by switching between writing and reading in this manner is also known.

By the way, in this embodiment, when the apparatus is downsized, a small circuit formed as an LSI is adopted for the data compression circuit 21 and the data decompression circuit 22. However, from the viewpoint of the processing capability of the circuit elements, the camera described above is used. Generating one piece of compressed image data requires a longer processing time than generating one piece of image data in an operation. For this reason, the semiconductor memory 12 is used as a buffer memory, and it is possible to capture images at a high speed of the camera operation. At this time, the data of the image P4 is held in the semiconductor memory 12 until the compression processing of the data of the image P4 and the writing to the semiconductor memory 13 are completed, thereby preventing the image content from being changed. I have. In order to perform this operation, the closing information of the recording trigger switch 5 is captured during a period from when the timing generation circuit 2 outputs the operation control signal MC to when the operation end signal ME is supplied from the timing generation circuit 7. Not to be.

In FIG. 3C, the timing generation circuit 7 stops generating the write clock CL2 when the writing of the data of the compressed image P4 is completed, and thereafter the semiconductor memory 13 holds the data of the image P4. Mode, and sends an operation end signal ME to the timing generation circuit 2. When receiving the operation end signal ME, the timing generation circuit 2 stops the generation of the operation control signal MC, starts the writing operation of the semiconductor memory 12 again, and sequentially transfers the data of the images P5, P6, and P7 to the semiconductor memory 12. Write to prepare for the next closing operation of the recording trigger switch 5.

It is conceivable to use a semiconductor memory 13 having a data storage capacity for a plurality of images. At this time, during the data write operation period indicated by P4, P7 and the like in FIG. 3C, only a part of the storage area of the image data held by the semiconductor memory 13 allocated to one image is new. Rewritten with image data. In addition, in the period indicated by "hold" in FIG. 3C, not only the image data written immediately before this but also the image data written before this is held. Further, in the case where the semiconductor memory 13 is, for example, a static random access memory backed up by a battery or a so-called flash nonvolatile memory, the time before writing the data of the image P4 in FIG. The data of the image Px recorded at the time of shooting before the current shooting started by closing the power switch 4 at T1 is held.

FIG. 3 also shows a memory operation when the recording trigger switch 5 is closed again (time T3) during a period of writing data of the image P7 into the semiconductor memory 12. The operation in this case is also the same as the recording operation of the data of the image P4, and thus the description thereof is omitted.

Although the operation of the electronic camera function (still image recording function) of this embodiment has been described above with reference to FIG. 3, this operation is similar to the operation of the apparatus described in Non-Patent Documents 1 and 2.

In the case where the semiconductor memory 13 is a flash memory, rewriting of image data by so-called overwriting cannot be performed due to the element configuration. Therefore, at the timing of the image P4 in FIG. 3C, before the data of the image P4 is written, the image data remaining in the memory area allocated as the data writing area of the image P4 is temporarily erased. Is executed. This erasing operation is, specifically, an operation of writing data of a predetermined logic level in the semiconductor memory. For example, a control (not shown) output from the timing generation circuit 7 is output to the output side of the data compression circuit 21 in FIG. A logic gate controlled to output data of a predetermined level by a signal is provided, and the data of the predetermined level can be written before writing the data of the image P4.

Further, as a flash memory device, there is also known a flash memory device in which a code signal supplied to a data input / output terminal I / O is fetched into a memory device by using several kinds of control signals and an operation mode such as writing and erasing is switched. is there. In addition, a so-called ready / busy signal generation function for generating data of a predetermined logic level to warn the user to wait for progress to the next operation during erasing or writing until the operation inside the memory element is completed is provided. What is possessed is also known. Even when such a memory element is used, a plurality of switching signals of the switch 11 are provided as necessary, and a control code is appropriately supplied to the data input / output terminal I / O terminal by switching between the image data and the semiconductor memory. And can be configured by a known technique in the field of digital circuit technology. An interface circuit corresponding to the function of the memory element to be used can be provided between the switches 11 and 15 and the semiconductor memory 13 in FIG.

As described above, when the image information signal is recorded, when the semiconductor memory 13 is a flash memory, the erasing operation is performed in conjunction with the operation, so that the user does not have to perform the erasing operation inherent to the flash memory. Operation can be performed with the same feeling as a conventional memory device capable of automatic rewriting by overwriting.

This embodiment is characterized in that the connector 14, the switches 11 and 15, the state detection circuit 23 for detecting the ready state of the signal transfer operation with the external device, and the start of the operation of the timing generation circuit 7 are prevented. Is provided so that digital image information signals can be transmitted and received between external devices and the semiconductor memories 12 and 13.

Hereinafter, this point will be described with reference to FIGS. However, FIG. 4 is a block diagram showing a specific example of the state detection circuit 23 in a state where an external device is connected to the connector 14 in FIG. 1, where 23a is a T-FF (T-type flip-flop) and 23b is AND. A gate, 23c is an OR circuit, 25 is an external device, 25a is a connector, and portions corresponding to those in FIG.

FIG. 5 is a timing chart for explaining a function of transmitting and receiving signals to and from an external device, and signals corresponding to those in FIG. 4 are denoted by the same reference numerals. FIGS. 5A, 5B, and 5C are the same as FIGS. 3A, 3B, and 3C, respectively.

First, in FIGS. 1 and 5, at time T1 when the power switch 4 is turned on, the image data already recorded is held in the semiconductor memory 13 as described above, and the timing generation circuit 7 operates. Is stopped, the operation end signal ME becomes “H” to indicate the operation end state. At time T2, the recording trigger switch 5 is closed, and when the writing of the data of the image P4 into the semiconductor memory 13 shown in FIG. 5C is started by the above-described series of operations, the level of the operation end signal ME becomes " L "to indicate that the timing generation circuit 7 is operating.

(4) Next, in FIG. 4 and FIG. 5, the operation end signal ME is supplied as one input to the AND gate 23b of the state detection circuit 23. The other input of the AND gate 23b is used to transmit and receive signals supplied from the external device 25 via the connectors 25a and 14 when the connector 25a of the external device 25 is fitted to the connector 14 and the external device is connected. This signal is a signal SaSa indicating a preparation state for operation (hereinafter, referred to as a preparation state instruction signal). The output of the AND gate 23b is supplied to the clock terminal T of the T-FF 23a as a trigger clock.

{Circle around (2)} The reset terminal R of the T-FF 23a is supplied with an initial reset signal INS when the power is turned on by the power switch 4 (FIG. 1) via the OR gate 23c. This initial reset signal INS is generated only for a predetermined short time after the power is turned on, and is used to reset each logic circuit to a predetermined initial state. Such a reset method is well known in the logic circuit technical field. This is a method, and a dedicated IC for generating a reset signal at the start of power supply is also commercially available. Therefore, the reset signal generation IC may be provided as a component of the state detection circuit 23, but the output signal of the reset signal generation circuit provided in the timing generation circuit 2 may be used as the initial reset signal INS.

Ｑ The Q output of the T-FF 23a is output as the state detection signal SD. As shown in FIG. 5, the state detection signal SD is reset from an undefined state (an undefined state of “H” or “L”) to an “L” state at time T1, as shown in FIG. When the state detection signal SD is "L", the switches 11 and 15 in FIG. 1 are in the state shown in FIG. The "L" state detection signal SD is inverted by the inverter 9 in FIG. 1 to become "H", and the AND gate 6 is set to a state of passing the operation control signal MC. Thus, as described with reference to FIG. 3, the data of the image P4 is written to the semiconductor memory 13 in conjunction with the closing of the recording trigger switch 5 at the time T2.

Here, suppose that at time T4, the external device 25 supplies the state detection circuit 23 with the "H" preparation status instruction signal CSSa indicating that preparation for signal transmission and reception has been completed by the external device 25. At this time, when the operation end signal ME changes to “H” with the end of the operation of the timing generation circuit 7 due to the completion of the writing of the data of the image P4 to the semiconductor memory 13, the T-FF 23a is triggered at this timing and the state is changed. The detection signal SD is inverted to “H”.

(1) When the state detection signal SD becomes “H”, the switches 11 and 15 in FIG. 1 are switched in the direction opposite to the direction shown in FIG. The switch 11 which is a one-way digital signal switch can be easily constituted by, for example, a multiplexer circuit, and the switch 15 which is a two-way switch can be easily constituted by, for example, a so-called analog switch circuit. Well known in the art.

(4) The state detection signal SD is supplied to the external device 25 via the connectors 14 and 25a, and notifies the external device 25 that the imaging device is in a state capable of signal transmission / reception by the fact that its level is "H".

When the external device 25 receives the state detection signal SD, the external device 25 receives the clock CL3, the address signal Ad3, and the read / write switching signal (R / -W3) for instructing the read through the switch 11 in FIG. 13. As a result, the semiconductor memory 13 reads, for example, one specific image or all image data from the recording area specified by the address signal Ad3, and switches the data input / output terminal I / O terminal to the switch 15 and the connector. 14 to an external device 25 (FIG. 4). At this time, the operation of the semiconductor memory 13 is exclusively controlled by the external device 25.

4 and 5, when the desired image data is read from the semiconductor memory 13, the external device 25 stops outputting the clock CL3, returns the preparation status instruction signal CSSa to "L", and at the same time, performs the transfer operation. The end signal CSSb is supplied to the state detection circuit 23. The transmission / reception operation end signal CSSb is supplied to the T-FF 23a via the OR gate 23c, and the T-FF 23a is reset to return the state detection signal SD to "L".

When the external device 25 is a personal computer, a signal of a relatively low frequency is often used as the signal transmission / reception clock CL3 (FIG. 1), but the frequency is determined only by the constraints of the external device 25 alone. It is convenient to be able to do it. In general, when a low-cost external device 25 is used, its data processing capability is low, so it is preferable to transmit and receive signals using a low-frequency clock. This is because it is desired that the transfer operation be completed in a short time with a high-speed clock. For this reason, it is conceivable that the time required for signal transmission / reception with the external device 25 differs depending on the model of the external device used even if the amount of signal data transmitted / received is the same.

In this embodiment, the state detection signal SD is also supplied for controlling the AND gate 6 inserted in the transmission path of the operation control signal MC for instructing the start of operation of the timing generation circuit 7, and the state detection signal SD is set to "H". , The operation control signal MC is blocked by the AND gate 6, and at least the semiconductor memory 13 in the interlocking operation of writing image data to the semiconductor memories 12 and 13 executed by closing the recording trigger switch 5. The writing of new image data to the external device 25 is inhibited, and the image data in the semiconductor memory 13 is prevented from being altered and the image content is changed during the uncertain time required for the signal exchange with the external device 25.

FIG. 5 illustrates the operation of the embodiment having the above configuration. For example, when the state detection signal SD is “H”, the timing generation circuit 2 is configured to ignore the closing of the recording trigger switch 5. Can be configured by a known technique in the field of logic circuit technology, and the above-described modification of image data in the semiconductor memory 13 can be prevented. However, in this case, naturally, all operations by operating the recording trigger switch 5 are prohibited.

In FIG. 5C, when the writing operation of the image P4 in the semiconductor memory 13 is completed and the operation end signal ME is inverted to “H”, as described with reference to FIG. , P7 are restarted (FIG. 5B). Then, when the recording trigger switch 5 is closed at time T3, the image P7 is held in the semiconductor memory 12, but the state control signal SD is "H". It is blocked and not supplied to the timing generation circuit 7, and the timing generation circuit 7 does not start operation. Therefore, the writing of the data of the image P7 is prohibited in the semiconductor memory 13, and the semiconductor memory 13 keeps the previous image data.

As described above, not only the switching operation of the switches 11 and 15 but also the operation of the timing generation circuit 7 are prohibited, so that useless operation of the circuit can be omitted and power consumption can be suppressed.

When the reading of the data of the image P4 to the external device 25 is completed and the state detection signal SD output from the state detection circuit 23 becomes “L” by the transmission / reception operation end signal CSSb, the switches 11 and 15 are again shown in FIG. It switches to the direction you do. The AND gate 6 is also enabled to pass, and the operation control signal MC is supplied to the timing generation circuit 7. As a result, the timing generation circuit 7 starts operation, the operation end signal ME becomes "L", and the data of the compressed image P7 is written into the semiconductor memory 13 at the timing shown in FIG. When this writing is completed, the operation end signal ME becomes "H" again, the preparation status instruction signal CSSa becomes "H" again, and it is instructed that the external device 25 is ready for signal transfer. As a result, the state detection signal SD is inverted to “H”, and the external device 25 is notified that the imaging device is in a state capable of exchanging signals again.

As described above, according to the operation of the present embodiment, during the data reading from the semiconductor memory 13 to the external device 25, the data writing to the semiconductor memory 13 is prohibited, or during the data writing to the semiconductor memory 13, Is prohibited from being read out to the external device 25 during the execution of the data read operation of the semiconductor memory 13 to the external device 25, there is no possibility that the image data in the semiconductor memory 13 is rewritten. Therefore, it is possible to prevent data of a plurality of images from being output in a mixed manner, instead of data of a single captured image, so that an image reproduced using the output data is a single image captured. It can be prevented from being transformed into a different one.

Further, when the output of the operation control signal MC is configured to be on standby, the image data is taken into the semiconductor memory 12 by the closing operation of the recording trigger switch 5 even when the data reading to the external device 25 is being executed, that is, Shooting can be performed, and the captured image information is automatically transferred to the semiconductor memory 13 and recorded as soon as the data readout to the external device 25 is completed, without requiring a new operation by the user. be able to. Further, when the data writing to the semiconductor memory 13 is completed, the state detection signal SD is automatically inverted to “H” in conjunction with the completion of the data writing, and the embodiment is switched to a state in which the signal exchange with the external device 25 is possible. Since the connected external device 25 can be notified of this state, the image data recorded in the semiconductor memory 13 can be read continuously by the external device 25 by shortening the waiting time. Become.

Further, the preparation status instruction signal CSSa is not limited to the level change timing as shown in FIG. 5, but may be maintained at this level after being once inverted to “H”, for example. Every time the writing of new image information in 5 (c) is completed and the operation end signal ME is inverted from “L” to “H”, a state in which signals can be automatically exchanged with the external device 25 becomes possible. .

When the preparation status instruction signal CSSa is defined to return from “H” to “L” each time the external device 25 ends signal transmission and reception, as shown in FIG. 5, the transmission / reception operation end signal CSSb is not necessarily required. It is not necessary to supply the signal from the external device 25. For example, a pulse signal having a predetermined pulse width is generated in synchronization with the edge timing of the preparation status instruction signal CSSa being inverted from “H” to “L”. For example, a known logic circuit configuration such as a monostable multivibrator circuit may be incorporated in the state detection circuit 23, and a preparation state instruction signal CSSa may be supplied to the state detection circuit 23 to obtain a pulse signal corresponding to the transmission / reception operation end signal CSSb. it can.

In FIG. 5, when the image data holding timing by the preparation state instruction signal CSSa, that is, when the preparation state instruction signal CSSa is inverted to “H” during the “H” period of the operation end signal ME, the state detection circuit 23 immediately The imaging apparatus according to the present embodiment outputs a state detection signal SD of “H”, and enters the signal transmission / reception state with the external device 25. In particular, the operation end signal ME is set to “H” in conjunction with the closing of the recording trigger switch 5. When the preparation status instruction signal CSSa is inverted from “L” to “H” immediately before switching from “L” to “L”, a noise signal with a small pulse width is generated from the AND gate 23b in FIG. Is triggered, the state detection signal SD may be inverted to “H”. Further, when the preparation status instruction signal CSSa is inverted to “H” before or near the time T1, the operation of the T-FF 23a is uncertain due to competition with the reset control of the T-FF 23a by the initial reset signal INS. Might be.

FIG. 6 is a circuit diagram showing another embodiment of the state detection circuit 23 in FIG. 1 which is also suitable for such a case, where 23d is an inverter, 26 to 29 are resistors, 30 is a transistor, and 31 and 32 are capacitors. , 33 are power supplies, and portions corresponding to those in FIGS. 1 and 4 are denoted by the same reference numerals.

FIG. 7 is a waveform diagram showing signals at various parts in FIG. 6, and signals corresponding to FIG. 6 are denoted by the same reference numerals.

In FIG. 6, the state detection circuit 23 is provided with a fitting detection switch 24. When a connector 25a of an external device (not shown) is fitted to the connector 14 (time T1), the fitting detection switch 24 is provided. Is pressed to close the circuit, and the "H" voltage signal SV from the power supply 33 is supplied to the AND gate 23b. This “H” voltage signal SV replaces the preparation status instruction signal CSSa in the specific example shown in FIG. The resistor 28 is for keeping one input of the AND gate 23b at the ground ("L") level when the fitting detection switch 24 is opened.

As a result, as shown in FIG. 7A, when the power of the apparatus is turned on by closing the power switch 4 in FIG. 1 in the state in which the connectors 25a and 14 are fitted, as shown in FIG. This is the same as the instruction signal CSSa being inverted from “L” to “H” at time T1.

In this specific example, the operation end signal ME is supplied as the other input of the AND gate 23b via the resistor 26. The capacitor 31 and the transistor 30 are connected between the input terminal of the AND gate 23b and the ground. Are connected in parallel. Then, an initial reset signal INS is supplied to the base of the transistor 30 via the resistor 27.

Therefore, as shown in FIG. 7A, when an initial reset signal INS of "H" is generated at the time of turning on the power, the transistor 30 is turned on during the signal period, so that the operation end signal ME of the AND gate 23b is supplied. The input level ADI on the other side is kept at "L". When the initial reset signal INS becomes “L” after a predetermined time has elapsed, the transistor 30 is turned off. At this time, if the operation end signal ME is “H”, the transistor 30 is turned off by the resistor 26 and the capacitor 31. After a time delay determined by the time constant, the input level ADI becomes "H". Since the T-FF 23a is reset by the initial reset signal INS during this time delay, the T-FF 23a is reset by the "1 level" output ADO of the AND gate 23b obtained when the input level ADI becomes "H". -The FF 23a can be reliably triggered to generate the state detection signal SD.

FIG. 7B shows the operation control signal MC of “H” output at time T2 ′ from the operation of the timing generation circuit 2 in conjunction with the closing operation of the recording trigger switch 5 (FIG. 1) at time T2. And the timing at which the fitting detection switch 24 is closed and the "H" voltage signal SV is supplied from the power supply 33 to the AND gate 23b.

At time T2 ', when the timing generation circuit 7 (FIG. 1) starts operating in response to the "H" operation control signal MC generated from the timing generation circuit 2 (FIG. 1), the operation end signal ME changes from "H" to "L". However, in general, from the time T2 ′, the operation delay depends on the signal propagation speed of the circuit element or the phase relationship between the operation clock of the timing generation circuit 7 supplied from the oscillation 8 and the operation control signal MC. There is a time difference before the operation end signal ME is inverted to “L”. When the voltage signal SV from the fitting detection switch 24 is inverted from “L” to “H” during the time difference, a pulse-like “H” output signal ADO is generated from the AND gate 23b for a short period. When the T-FF 23a is triggered by the output signal ADO, the state detection signal SD is inverted to "H". In this state, the switches 11 and 15 (FIG. 1) are operated in spite of the operation of the timing generation circuit 7. ) Is connected to the access side of the external device, so that image data captured at the time T2 cannot be stored in the semiconductor memory 13 (FIG. 1).

Therefore, the specific example shown in FIG. 6 is provided with the following configuration in order to avoid such a situation in which photographing is invalidated.

That is, in addition to the transmission / reception operation end signal CSSb and the initial reset signal INS, the operation end signal ME is supplied to the OR circuit 23c with its level inverted by the inverter 23d, as in the specific example shown in FIG. When the operation end signal ME is inverted to "L", the T-FF 23a is reset, and the state detection signal SD, which has been inverted to "H", returns to "L" again. . Thus, the image information can be effectively written into the semiconductor memory 13 by the operation of the timing generation circuit 7.

Further, at this time, the condition for generating the state detection signal SD having a pulse-like waveform of “H” as shown in FIG. 7B is determined from the time when the voltage signal SV from the fitting detection switch 24 is inverted to “H”. The circuit operation delay time t1 until the AND gate 6 (FIG. 1) is closed by the state detection signal SD, and the T-FF 23a by the "L" operation end signal ME from the time when the operation control signal MC is inverted to "H". The voltage signal SV from the fitting detection switch 24 is inverted to “H” in a time region around the time T2 ′ defined by the sum of the delay time t2 and the reset time t2. At this time, the times t1 and t2 can be predicted in advance based on the speed performance of the circuit element to be used, the adopted circuit configuration, and the like. Further, the state detection signal SD of “H” shown in FIG. The period is shorter than the period (t1 + t2).

Therefore, by providing a circuit for preventing the output of a signal having a predetermined pulse width or less from being provided at the output section of the state detection signal SD to the connector 14, a pulse-like state detection signal of "H" shown in FIG. SD can be prevented from being supplied to an external device. In FIG. 6, an integrating circuit including a resistor 29 and a capacitor 32 is used as the blocking means. Of course, other configurations for implementing similar functions are well known in the logic circuit art. It should be noted that even if such a pulse-like state detection signal SD is supplied to an external device as it is, the external device side may be configured not to respond to a state detection signal SD having a small pulse width assumed in advance. When the state detection circuit 23 side is configured to block such a pulse-like state detection signal SD as described above, there are fewer restrictions on the operation of the external device, and the troublesomeness in setting an operation program in the external device is reduced. Can be reduced.

As another specific example of the state detection circuit 23, in FIG. 6, a gate is provided on the resistor 28 side of the fitting detection switch 24, and this is controlled by a gate signal GC shown in FIG. You may make it. The gate signal GC becomes "H" at a time T2 when the recording trigger switch 5 is closed, that is, a predetermined time before the operation control signal MC, and a predetermined time elapses after the operation end signal ME is inverted to "L". It is generated by the timing generation circuit 2 so as to return to "L" later. During the "H" period of the gate signal GC, the voltage signal SV from the fitting detection switch 24 is blocked and the AND gate 23b , And the inversion of the voltage signal SV from the fitting detection switch 24 to “H” in the time domain (t1 + t2) in FIG. 7B is prohibited. In this case, the "H" state of the output signal ADO and the state detection signal SD of the AND gate 23b shown after the time T2 'in FIG. 7B does not occur. Therefore, it is not necessary to supply the inverted signal of the operation end signal ME to the OR circuit 23c.

Although the state detection circuit 23 shown in FIGS. 4 and 6 and the AND gate 6 and the inverter 9 in FIG. 1 are constituted by hardware logic circuits, for example, a microcomputer is used and this is used in FIG. The state may be detected by the initial reset signal INS, the operation end signal ME, the voltage signal SV, the gate signal GC, and the transfer operation end signal CSSb, and the operation control signal MC and the state detection signal SD may be generated based on the result.

The above is the description of the image capturing operation and the image information output operation to the external device of the embodiment shown in FIG. 1. Next, the image reproducing operation of this embodiment will be described with reference to the operation time chart shown in FIG. explain.

In this operation, in FIG. 1, the power supply switch 4 is closed in a state of a broken line in the opposite direction to that shown in the drawing, thereby switching to the reproduction mode. In this case, the recording trigger switch 5 is operated by the forward selection switch of the reproduction image. It is configured to have a function as Such function switching can be easily realized by using a microcomputer or a logic circuit technology.

1 and 8, when the user closes the power switch 4 to the reproduction mode side shown by a broken line at time T1, the operation power is turned on and the reproduction operation starts as shown in FIG. Is done. At this time, as an initial operation, as shown in FIG. 8B, the data of the first image P1 is read from the semiconductor memory 13 in the image data holding state, and as shown in FIG. The data is written to the memory 12. Such an initial operation is performed as follows.

(4) The timing generation circuit 2 starts the reproduction operation by closing the power switch 4, but at this time, the microcomputer in the timing generation circuit 2 is programmed so as to perform the next initial operation. That is, the timing generation circuit 7 is operated by the operation control signal MC to generate the clock CL2, the address signal Ad2, and the read / write switching signal (R / -W2) of "L" instructing the read operation. Further, it generates an operation clock CK5 of the image data expansion circuit 22 for restoring the compressed image data to non-compressed image data, a clock CL1 for the semiconductor memory 12, and an address signal Ad1. Further, the switches 10, 16, and 18 are closed in the directions opposite to those illustrated by the switch control signals SW1, SW2, and SW3. The operation end signal ME is kept at "L" at time T1 by the timing generator 7 starting the initial operation.

Here, as shown in FIG. 8, even if the external device is instructed by the preparation status instruction signal CSSa shown in FIGS. 4 and 5 to be in an access preparation state to the semiconductor memory 13 as shown in FIG. 4 or the operation of the AND gate 23b shown in FIG. 6 prevents the state detection signal SD from being inverted to "H". Therefore, the switches 11 and 15 maintain the state shown in FIG. 1, and the image data is read from the data input / output terminal I / O of the semiconductor memory 13 and processed by the image data expansion circuit 22. The data is supplied to the semiconductor memory 12. At this time, the clock CL1 and the address signal Ad1 from the timing generation circuit 7 are supplied to the semiconductor memory 12 as the write clock WC and the write address signal WA, respectively.

The above is the initial operation of the reproduction mode. Next, the operation of reading image data from the semiconductor memory 12 will be described.

In this case, the clock CL and the address signal Ad output from the timing generation circuit 2 are supplied to the semiconductor memory 12 as the read clock RC and the read address signal RA, respectively. This data reading is performed by scanning the data area of the field image or the frame image at the scanning speed of the television signal.

The image data read from the semiconductor memory 12 is supplied to the encoder circuit 19 via the switch 18, converted into an analog video signal, and output from the output terminal 20.

By the way, generally, the supply of the operation power is stopped together with the stop of the supply of the power, and in the semiconductor memory 12 which is not backed up, the false data whose level is undefined is stored at the start of the power supply at the time T1. Therefore, in FIG. 8, during the write operation of the data of the image P1, the false data is sequentially rewritten with the data of the image P1.

Here, the restoration processing of one image data by the image data decompression circuit 22 is also restricted by the operation speed due to the same processing capability as the above-described image data compression processing operation. Therefore, in general, the time required to restore one image data by the image data decompression circuit 22 is shorter than the time required to read one image data of the semiconductor memory 12 by the clock CL and the address signal Ad from the timing generation circuit 2. It is longer. Then, at time T1, the data reading from the semiconductor memory 12 is started immediately by the clock CL and the address signal Ad from the timing generating circuit 2, and when the encoder 19 generates a video signal from the read image data, the connection to the output terminal 20 is established. First, on the display device such as a television monitor device, a fake image based on the above fake data, which is generally a mosaic pattern, is reproduced, and then the image decompressed by the image data decompression circuit 22. For example, an image is displayed on the image based on the data of P1 such that the image gradually changes from the upper left corner of the displayed image.

Here, the recording area of the semiconductor memory 12 rewritten with the restored data is known from the state of the address signal Ad1 from the timing generation circuit 7, and the timing at which image data from other areas is output from the semiconductor memory 12 Thus, for example, by holding the input level of the encoder 19 at a predetermined value, the output of the video signal signal due to the false data at the time of rewriting is prevented, and for example, a portion on the screen where the rewriting has not been completed can be displayed in gray. It is also possible. Further, at the time of successively updating the reproduced image without stopping the power supply, the previously selected image is displayed so as to gradually change to the newly selected image.

As is clear from the above description, the image information output from the output terminal 20 has a period in which a plurality of images are mixed. Since it is not a device used to retrieve images, there is no problem even if mixed images are transiently output, and it is better to be able to display the process of updating images on the monitor display rather than the operation status of the device. In many cases, it is suitable because it can be grasped.

When the writing of the data of the image P1 to the semiconductor memory 12 is completed, the timing generation circuit 7 stops generating the clocks CL1 and CL2, the semiconductor memory 12 enters the data holding mode of the image P1, and the semiconductor memory 13 is read. Operation stops. Further, the timing generation circuit 7 outputs an “H” operation end signal ME. At this time, as shown in FIG. 8, when the preparation state instruction signal CSSa is “H” and indicates the preparation state of signal transmission / reception by the external device, the state detection circuit 23 outputs the “H” state detection signal SD. To occur. As a result, the switches 11 and 15 are switched in the direction opposite to the direction shown in FIG. 1, so that the external device connected to the connector 14 can access the semiconductor memory 13.

Here, a clock CL3, an address signal Ad3, and a read / write switching signal (R / -W3) of "L" instructing data writing are supplied from the external device, and the data of the image Pext is transmitted from the external device to the switch 15. By supplying the image data to the semiconductor memory 13 via the memory, one or a plurality of image data can be written to the semiconductor memory 13 at the timing indicated by Pext shown in FIG. Further, after the writing of the image P1 shown in FIG. 8C is completed, when the preparation status instruction signal CSSa remains "L" unlike the case of FIG. 8, both the semiconductor memories 12 and 13 are in the data holding state. In this state, as soon as the recording trigger switch 5 is closed at time T2 and the selection of the next image is instructed, the timing generation circuit 2 immediately outputs the operation control signal MC to transfer the image P2 to the semiconductor memory 12. Execute the write operation.

In this embodiment, the output of the operation control signal MC can be suspended during the period in which the state detection signal SD is at “H” during the reproduction operation, similarly to the above-described imaging operation. When the state detection signal SD becomes “H” before the time T2, a transmission / reception operation end signal CSSb indicating the end of the signal transmission / reception operation is supplied from the external device until the state detection signal SD returns to “L”. During the period, the semiconductor memory 12 is kept in the data holding state, and when the state detection signal SD is inverted to “L”, the image P2 can be automatically written into the semiconductor memory 12. When the image P2 is rewritten in the semiconductor memory 13 at the timing of the previous Pext, the rewritten image is written in the semiconductor memory 12.

In addition, in the case where signals are not exchanged with the external device in the connection state of the external device, it is natural that the preparation status instruction signal CSSa should be kept at “L”. For example, as shown in FIG. When the voltage signal SV from the fitting detection switch 24 is used in place of the preparation state instruction signal CSSa as in the state detection circuit 23, the state detection signal SD of “H” is transmitted through the connector 14 every time. Then, by sending back the sending / receiving operation end signal CSSb from the external device, the state detection signal SD immediately returns to "L" and the operation by the closing of the recording trigger switch 5 can be started. Selection of the reproduced image by the operation 5 can be performed without delay.

According to the image reproducing operation of this embodiment as described above, during a period in which image data is read from the semiconductor memory 13 in order to write reproduced image data to the semiconductor memory 12, data writing from the external device to the semiconductor memory 13 is not performed. Also, while data writing from an external device to the semiconductor memory 13 is being executed, data reading from the semiconductor memory 13 and writing to the semiconductor memory 12 are prohibited. With such an operation, there is no possibility that data of a plurality of images are mixed in the image data read from the semiconductor memory 13. Therefore, the image data written in the semiconductor memory 12 and the image data read therefrom and displayed on a television monitor or the like are not generated. The content of the image to be read does not change to a different image from the one image stored in the semiconductor memory 13.

Further, the operation of updating the reproduced image by closing the recording trigger switch 5 or the like is made to wait for a period of signal transmission / reception with an external device, and the recording trigger switch 5 is closed mechanically or electrically continuously, for example. The timing generation circuit 2 detects the open / closed state of the recording trigger switch 5 at every predetermined timing, for example, at each time when the state detection signal SD is inverted from “H” to “L”. By programming the microcomputer, this embodiment can be operated so that the image written from the external device is immediately and automatically reproduced. The same function can also be realized by using the signal transfer operation end signal CSSb instead of the closing signal of the recording trigger switch 5. At this time, when the semiconductor memory 13 records a plurality of images, the image input from the external device is made into one image by one writing operation, and the written image and the image to be read are matched. For this purpose, means for detecting an address signal supplied from an external device and loading the start address into a counter for generating an address signal Ad2 arranged in the timing generation circuit 7 is also used.

Note that when the state detection signal SD is “H” in FIG. 5 or FIG. 8, regardless of whether the camera is in the imaging mode as described in FIG. 4 or FIG. 5 or in the reproduction mode as described in FIG. By inverting the level of the read / write switching signal (R / -W3) supplied from the external device, data writing from the external device to the semiconductor memory 13 or data reading from the semiconductor memory 13 to the external device can be executed. In addition, the state detection circuit 23 also outputs a state detection signal output from the state detection circuit 23 during a combination operation of the operation mode of the present embodiment and the write access or the read access to the semiconductor memory 13 by the external device, which is not described in FIGS. 5 and 8 by the signal SD, that is, data write access to the semiconductor memory 13 (in the imaging mode) or data read access from the semiconductor memory 13 (in the reproduction mode) by the internal operation of this embodiment. During execution of the control, prohibits access to the semiconductor memory 13 by an external device, and prohibits access to the semiconductor memory 13 by the internal operation of the present embodiment during access to the semiconductor memory 13 by the external device. By the operation, the data is stored in the storage area of the semiconductor memory 13 allocated to the data of one image. Image data can be prevented from being stored.

As described above, in the embodiment shown in FIG. 1, when the semiconductor memory 13 is accessed by the operation started in conjunction with the closing of the recording trigger switch 5, that is, the imaging operation or the reproducing operation, This is to prohibit any access to the semiconductor memory 13 from the device.

By the way, the access of the semiconductor memory 13 by this internal operation accesses only the memory area of one screen of image data in the semiconductor memory 13 for each closing of the recording trigger switch 5 as is clear from the description of the above embodiment. It is executed by doing. Therefore, when the semiconductor memory 13 stores a plurality of pieces of image data, the desired effect can be obtained even if the above-described access prohibition control is limited to the memory area for the data of one image. can get.

FIG. 9 is a block diagram showing a main part of another embodiment of the imaging apparatus according to the present invention capable of realizing such a control operation, wherein 11A and 11B are switches, 13A and 13B are semiconductor memories, and 15A and 15B are switches. , 23A, 23B, and 34 are state detection circuits, 35 is a selection signal generation circuit, 36 and 37 are AND gates, 38 to 42 are OR circuits, and 43 to 45 are inverters, and the same reference numerals are used for parts corresponding to FIG. Is attached.

9, the left half of FIG. 1, that is, the timing generation circuit 2, the semiconductor memory 12, the image sensor 1, the camera signal processing circuit 17, and the encoder 19 are the same, and thus are omitted. Further, the switch 11, the semiconductor memory 13, the switch 15, and the state detection circuit 23 in FIG. 1 are each two, that is, the switches 11A and 11B, the semiconductor memories 13A and 13B, the switches 15A and 15B, and the state detection circuits 23A and 23B. Is provided. Although not shown in FIG. 9, the timing generation circuit 7 also generates a clock CL1 and an address signal Ad1, as in the case of FIG.

The feature of this embodiment is that the semiconductor memory 13 is arranged independently for each image to be stored, and the access control of the image data can be executed independently for each image data. is there. In this embodiment, the number of images to be stored is two. For this purpose, as described above, each of the semiconductor memory 13, the switches 11, 15 and the state detection circuit 23 in FIG. .

Here, each of the semiconductor memories 13A and 13B for storing data of one image is composed of one (or a plurality) of commercially available semiconductor memory ICs. An enable terminal CE is provided, and operates at a logic level of a chip enable signal supplied to this terminal, for example, when it is at "H", by a clock CL, an address signal Ad, and a read / write switching signal (R / -W). At the time of L ", it has a function of not accepting the above operation control at all, and having a function of setting the input / output impedance of the data input / output terminal I / O to high impedance and disconnecting it from an external circuit. In this embodiment, the semiconductor memory 13A, 13B is selected by using such a function.

For this reason, in this embodiment, the operation control signal MC supplied to the timing generation circuit 7 via the AND gate 6 is also supplied to the selection signal generation circuit 35 including a counter or a shift register. The selection signal generation circuit 35 generates selection signals S1 and S2 for selecting the semiconductor memories 13A and 13B.

In this embodiment, similarly to the above-described embodiment, since the access to the semiconductor memories 13A and 13B is performed in units of one image, the selection signals S1 and S2 simultaneously select the semiconductor memories 13A and 13B. The level (here, the selection level is set to “H”) does not occur. In addition, from the external device, a preparation status instruction signal CSSa1 which becomes “H” when the semiconductor memory 13A is selected and a preparation status instruction signal CSSa2 that becomes “H” when the semiconductor memory 13B is selected are transmitted from the connector 14 Is supplied via

Here, when the timing generation circuit 7 executes the access to the semiconductor memory 13 in response to the operation control signal MC supplied from the timing generation circuit 2 in conjunction with the closing of the recording trigger switch 5 shown in FIG. In the signal generation circuit 35, the selection signal S1 becomes “H” and the selection signal S2 becomes “L” by one closing of the recording trigger switch 5, and the selection signal S1 becomes “L” by the next closing of the recording trigger switch 5. Becomes "L", the selection signal S2 becomes "H", and when the recording trigger switch 5 is further closed, the selection signals S1 and S2 return to the initial level. The level change is repeated as described above for each closing of the recording trigger switch 5.

The selection signals S1 and S2 are supplied to the AND gates 36 and 37, respectively, and become "L" at the start of the operation of the timing generation circuit 7. During the operation, the levels of the AND gates 36 and 37 are maintained. The operation termination signal ME is inverted by an inverter 43 and supplied to AND gates 36 and 37. Output signals of the AND gates 36 and 37 are supplied to chip enable terminals CE of the semiconductor memories 13A and 13B as chip enable signals via OR circuits 38 and 39, respectively. Thus, each time the timing generation circuit 7 performs an operation by closing the recording trigger switch 5, the semiconductor memories 13A and 13B are alternately selected.

The selection signals S1 and S2 are supplied to the state detection circuits 23A and 23B via the OR circuits 41 and 42 after the level is inverted by the inverters 44 and 45, respectively. The operation end signal ME is also supplied to the state detection circuits 23A and 23B via the OR circuits 41 and 42. As a result, the output signal of the OR circuit 41 becomes “L” only while the semiconductor memory 13A is being accessed by the timing generation circuit 7, and becomes “H” during other periods. Similarly, the output signal of the OR circuit 42 is “L” only while the semiconductor memory 13B is being accessed by the timing generation circuit 7, and is “H” during other periods. The output signals of these OR circuits 41 and 42 replace the operation end signal ME in the state detection circuit 23 in FIG. 1 in the state detection circuits 23A and 23B.

The state detection circuit 23A is supplied with a preparation state instruction signal CSSa1 from an external device, and the state detection circuit 23B is supplied with a preparation state instruction signal CSSa2. These preparation state instruction signals CSSa1 and CSSa2 are used for state detection in FIG. This is the same as the preparation status instruction signal CSSa supplied to the circuit 23. Further, a transfer operation end signal CSSb from an external device is supplied to both the state detection circuits 23A and 23B.

Here, when accessing the semiconductor memory 13A, the external device sets the preparation status instruction signal CSSa1 to "H" when accessing the semiconductor memory 13B, and simultaneously sets the preparation status instruction signal CSSa2 to "H". H ”. In addition, even when the external device accesses one of the semiconductor memories 13A and 13B, the external device generates a pulse-like transfer operation end signal CSSb as shown in FIG. 5 every time the access operation of the selected semiconductor memory ends. .

With the above configuration, the state detection circuit 23A performs the same operation as the state detection circuit 23 shown in FIG. 4, and when the semiconductor memory 13A is being accessed by the timing generation circuit 7, regardless of the state of the preparation state instruction signal CSSa1. When the state detection signal SDa is held at "L" and this access is not made, the state detection signal SDa can be switched to "H" by setting the preparation status instruction signal CSSa1 to "H".

When the state detection signal SDa is “H”, the switches 11A and 15A are switched to enable connection of each terminal of the semiconductor memory 13A to an external device, and to the chip enable terminal CE of the semiconductor memory 13A via the OR circuit 38. Supplied to make it operable. Further, it notifies the external device via the OR circuit 40 that the semiconductor memory 13 can be accessed. Similarly, the access of the semiconductor memory 13B is switched by the operation of the state detection circuit 23B.

(4) The state detection signals SDa and SDb are further supplied to the state detection circuit 34. In the embodiment shown in FIG. 1, the state detection signal SD output from the state detection circuit 23 is supplied to the AND gate 6 via the inverter 9, and the state detection circuit 23 controls the operation of the timing generation circuit 2. Although this is used for the control to wait for the output of the signal MC, in this embodiment shown in FIG. 9, such an operation is performed by using the state detection circuit 34.

That is, the state detection circuit 34 can detect whether the semiconductor memory to be selected by the selection signal generation circuit 35 in the next operation is the semiconductor memory 13A or the semiconductor memory 13B from the levels of the selection signals S1 and S2. The state of selection of the semiconductor memories 13A and 13B by the external device is known from the logic level of the state detection signal SDa or SDb. If the semiconductor memory 13A or 13B to be selected is not accessed by the external device, the operation is immediately started. When the access is being made, the operation waits or the non-accessed one of the semiconductor memories 13A and 13B is selected to start the operation.

FIG. 10 is a block diagram showing a specific example of the state detection circuit 34 in FIG. 9, wherein 34a and 34b are AND gates, 34c is a NOR circuit, and portions corresponding to FIG. .

In the figure, when the selection signal S1 is set to "H", the selection signal generation circuit 35 switches the selection signal S2 to "H" and the selection signal S1 to "L" when the next operation control signal MC is input. When the selection signal S2 is "H", the selection signal S1 is switched to "H" and the selection signal S2 is switched to "L" when the next operation control signal MC is input.

Therefore, in the state detection circuit 34, the selection signal S2 and the state detection signal SDa are supplied to the AND gate 34a, and the selection signal S1 and the signal SDb are supplied to the AND gate 34b, respectively. When the semiconductor memory 13A or 13B matches the semiconductor memory 13A or 13B that is to be accessed by the operation of the next timing generation circuit 7, an "H" signal is output from one of the AND gates 34a and 34b. Is output. At this time, since the output signal of the NOR circuit 34c becomes "L", the passage of the operation control signal MC is prevented by the AND gate 6, and the above described state detection signal SDa or SDb becomes "L". The standby operation state is maintained until the coincidence state is released.

In the embodiment shown in FIG. 9, a total of two images are stored in the two systems of semiconductor memories 13A and 13B, one image each. However, the semiconductor memory 13 is added, and accordingly, the switches 11 and 15 are added. Alternatively, by adding a circuit configuration including the state detection circuit 23 and the OR circuit 38, two or more images can be stored. At this time, only one state detection circuit 34 may be used. FIG. 11 shows a specific example of the state detection circuit 34 in the case where the N-system semiconductor memory 13 is used. However, in the figure, 341, 342, 343, 344,..., 34 N are AND gates corresponding to the AND gates 34 a, 34 b in FIG. 10, and the parts corresponding to FIG. .

11, a selection signal generation circuit 35 in which the number of stages of a counter or a shift register is set corresponding to N semiconductor memories 13 generates N selection signals S1, S2, S3, S4,..., SN. These are supplied to AND gates 341, 342, 343, 344,..., 34N of the state detection circuit 34, respectively. Although not shown, N circuits corresponding to the state detection circuits 23A, 23A of FIG. 9 are provided, and the state detection signals SD1, SD2, SD3, SD4,... , 342, 343, 344,..., 34N. With this configuration, when the system of any of the semiconductor memories 13 to be accessed is being accessed by an external device by the next operation of the timing generation circuit 7, the operation of the timing generation circuit 7 is put on standby. be able to.

In FIGS. 10 and 11, an initial reset signal INS at power-on is supplied to the selection signal generation circuit 35. By resetting the counter and the like, the selection signal in the initial state is set (generally, The first selection signal S1 is set to "H").

Further, a digital addition circuit for adding 1 to the current count number of the counter of the selection signal generation circuit 35 in FIG. 10 or 11 and a function of loading the addition result into the counter are added. The above-mentioned loading is executed at the timing when the output signal is “L” and the operation control signal MC is inverted from “L” to “H”, so that the AND gate 6 blocks the operation control signal MC. Then, the selection signal generation circuit 35 automatically counts up and cancels the condition that the output signal of the NOR circuit 34c becomes "L", and the operation control signal MC passing through the AND gate 6 releases the selection signal. By counting up the generating circuit 35 again, a semiconductor memory system not accessed by an external device is selected to execute writing. It is possible to become so as to.

As described above, even if the semiconductor memory 13 is divided into a plurality of memory blocks that can be independently accessed, the same effect as that of the embodiment shown in FIG. 1 can be obtained. When any of the blocks is being accessed by an external device, it is possible to automatically select the memory block that has not been accessed and execute access to the semiconductor memory 13 by an imaging operation or a reproduction operation. Therefore, when the semiconductor memory 13 having a recording area for a plurality of images is employed, even when the external device is accessing the semiconductor memory 13, the recording except for the recording area currently accessed by the external device is performed. A plurality of images can be taken and recorded in the area.

In the embodiments shown in FIGS. 1 and 9, the recording trigger switch 5 for starting the operation is arranged in the apparatus. However, the present invention is not limited to this. The operation can be started by a remote controller, or an operation start can be instructed from an external device connected to the connector 14.

In the embodiment shown in FIGS. 1 and 9, a memory means such as a magnetic disk may be used instead of the semiconductor memory 13, and the switching control of these memory accesses is performed in the same manner as described above. Configurable to perform.

In the embodiments shown in FIGS. 1 and 9, the image data is compressed or decompressed, but such a function is not essential in the present invention. Although the semiconductor memory 12 is used as the buffer memory, the semiconductor memory 12 is not indispensable in an embodiment having no image data compression / decompression function, and the captured image information is recorded in the semiconductor memory 13 in real time. May be configured.

Further, in the case where flash memory elements for generating the above-mentioned ready / busy signals are used as the semiconductor memories 13, 13A and 13B in FIGS. 1 and 9, the ready / busy signals generated by them and the state detection signal A signal obtained by performing a logical sum with each of SD, SDa, and SDb may be transmitted to an external device via the connector 14.

1, a switch corresponding to the switch 11 is further provided between the switch 10 and the semiconductor memory 12, and the data input terminal I and the data output terminal O of the semiconductor memory 12 are switched to each other. A switch that can be selectively connected to the connection relationship shown and the connection relationship with an external device via the connector 14 is provided, and this switch is used as a signal indicating the operation state of the timing generation circuit 2 as an operation end signal ME. Instead, or by switching in accordance with the output signal of the state detection circuit 23 used in addition to the operation end signal ME, image data that has not been subjected to compression processing from an external device is written into the semiconductor memory 12 and the image data is written into the semiconductor memory 12. The data may be compressed by the data compression processing circuit 21 and written into the semiconductor memory 13 or may be compressed by an external device. Image data is written to the semiconductor memory 13, restored by the image data decompression processing circuit 125, temporarily taken into the semiconductor memory 12, and then external devices can read the restored image information from the semiconductor memory 12. realizable. Also, at this time, the access of the semiconductor memory 12 started by the user operating the recording trigger switch 5 at an arbitrary timing and the access of the individual semiconductor memory 12 by the external device overlap with each other. Automatically avoids data of a plurality of images in one image data.

FIG. 12 is a diagram showing an external view and an example of use of an embodiment of the imaging apparatus according to the present invention. Here, 46 is an imaging device according to the present invention, 47 is a light receiving lens for imaging, 48 is a finder similar to a conventional film camera, and 49 is a lens hood.

FIG. 12A shows the appearance of an image pickup apparatus, which is provided with a light receiving lens 47 for image pickup, a finder 48, and a lens hood 49 similar to those of a conventional film camera. Further, similarly to the conventional film camera, a recording trigger switch 5 is provided on the upper left side in the figure, and a connector 14 is mounted on the right side surface in the figure. Here, when the semiconductor memory 13 irremovably built in the device is used, the thickness D shown in the figure can be made extremely thin.

12B to 12E show an example in which the external device is a personal computer PC and the image pickup device 46 is mounted on the personal computer PC for use. FIG. This shows a case where the connection is directly made to a socket inside the computer PC.

FIG. 12C shows an example in which the connector 14 of the imaging device 46 is connected to a personal computer PC via a socket 50 and a cable 51.

FIG. 12D shows a configuration in which the imaging device 46 is mounted on an adapter 52 having a built-in power supply circuit such as a known AC / DC converter that generates a DC voltage from an AC power supply, and the adapter 52 is connected to a personal computer PC. . In this case, for example, operating power is supplied to the imaging device 46 from an operating power input terminal provided in the connector 14 and input / output signals of the connector 14 are transmitted to an electric circuit, for example, electric wiring or a signal buffer installed inside the adapter 52. It is connected to a personal computer PC via a circuit or the like. Note that the adapter 52 may include a known DC power supply such as a dry battery, and in this case, the adapter 52 is configured to exclusively supply an operation power supply, and is used together when the imaging device 46 is used outdoors. You can do anything.

FIG. 12 (e) shows an example in which a personal computer PC is connected to an adapter 53 having the same mechanism as that of a known desk lamp stand. In this case, for example, the imaging device 46 is installed inside the circle drawn by the fluorescent tubes of the round fluorescent lamps 54a and 54b, thereby capturing an image of the subject illuminated by the fluorescent lamps 54a and 54b, and using the image information of the personal computer. It can be configured to transmit to a PC.

Here, the terminal position of the connector 14 shown in FIG. 12A is defined with reference to the device exterior surface on the side opposite to the direction of the incident light of the light receiving lens 47 for imaging, so that the configuration shown in FIG. In the operations (b) to (e), when the reference surface is mounted facing the adapter or the like, the incident light direction is opened without being shielded, so the mounting is performed on the personal computer PC or the adapter. Images can be taken in the state.

FIG. 1 is a block diagram illustrating an embodiment of an imaging device according to the present invention. FIG. 11 is a schematic diagram illustrating a FIFO memory used in a conventional imaging device. FIG. 2 is a timing chart showing an operation of the semiconductor memory in FIG. 1. FIG. 2 is a block diagram illustrating a specific example of a state detection circuit in FIG. 1. FIG. 5 is a timing chart illustrating a signal transmission / reception function with the external device of the embodiment illustrated in FIG. 1 and an operation of the state detection circuit illustrated in FIG. 4. FIG. 3 is a block diagram illustrating another specific example of the state detection circuit in FIG. 1. FIG. 7 is a timing chart illustrating an operation of the state detection circuit illustrated in FIG. 6. FIG. 2 is a timing chart showing an image reproducing operation of the embodiment shown in FIG. 1. FIG. 10 is a block diagram illustrating a main part of another embodiment of an imaging device according to the present invention. FIG. 10 is a block diagram illustrating a specific example of a state detection circuit in FIG. 9. FIG. 10 is a block diagram illustrating another specific example of the state detection circuit in FIG. 9. FIG. 1 is a diagram illustrating an appearance of an embodiment of an imaging device according to the present invention and an example of its use.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 1 Image sensor 2 Timing generation circuit 4 Power switch 5 Recording trigger switch 7 Timing generation circuit 10, 11, 11A, 11B Switch 12, 13, 13A, 13B Semiconductor memory 14 Connector 15, 15A, 15B, 16 switch 17 Camera signal processing circuit Reference Signs List 18 switch 19 encoder 20 output terminal 21 image data compression processing circuit 22 image data decompression processing circuit 23, 23A, 23B state detection circuit 24 fitting detection switch 25 external device 34 state detection circuit 35 selection signal generation circuit

Claims (1)

Imaging means for photoelectrically converting an optical image to generate an electric two-dimensional image information signal; memory for storing the two-dimensional image information signal; operation start instruction means for operation start instruction; and operation start instruction Control means for storing one two-dimensional image information signal generated by the imaging means by the first access of the memory in response to an operation start instruction of the means in the memory;
A connector that can be connected to an external device;
Switching means for switching between the second access for accessing the memory and the first access by an external device via the connector;
State detecting means for detecting a first state in which the second access is in a preparation state or an execution state, and when the state detecting means detects the first state, the first state is set by the switching means. An imaging apparatus characterized in that switching to access is prohibited.

Images