JP3685198B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus that electronically records an optical image of a subject as an image information signal, and in particular, improves operability when connecting to a peripheral device and exchanging the image information signal between apparatuses. The present invention relates to an imaging apparatus.

  As a conventional device of this type, there is a so-called electronic camera, and a digital still camera is one example (see, for example, Non-Patent Document 1).

  Another example is a DS-100 type camera (see, for example, Non-Patent Document 2).

  In the electronic cameras described in Non-Patent Documents 1 and 2, for example, as shown in FIG. 1 of Non-Patent Document 1, an image information signal obtained by an image sensor is digitized (quantized) to obtain a semiconductor memory. It is recorded on an installed card (hereinafter referred to as a memory card).

  As described above, in Non-Patent Documents 1 and 2, since the image information signal is handled as a digital signal, connection with a peripheral device such as a personal computer that handles the digital signal exclusively (without an analog / digital converter or the like) It is easy (as a signal can be directly exchanged with a digital signal), and there is no deterioration in image quality due to the transmission path, and it is shown that the connectivity with other systems is good.

  Non-Patent Document 1 does not describe a specific example related to connection with a peripheral device, but it is understood that a memory card is used as an intermediary medium. Non-Patent Document 2 discloses a usage example of such a memory card. That is, the memory card is first attached to the electronic camera to record image information signals, and then the memory card is detached from the electronic camera and attached to a peripheral device separate from the electronic camera, and recorded on the memory card. This peripheral information is read by the peripheral device. In this case as well, the above-mentioned memory card is used as a method for transmitting the image information recorded in the memory by the electronic camera to the peripheral device as a digital signal (without going through a digital / analog converter or an analog / digital converter). A method other than the method of using the medium is not disclosed.

  By the way, there is an FSA2001 type still image compression / expansion substrate as a known device that is connected to a personal computer or the like to electrically exchange image information signals (for example, see Non-Patent Document 3).

  The device described in Non-Patent Document 3 has a built-in semiconductor memory for storing digital image information signals. Between the device and a personal computer connected via a connector, a cable, etc. The digital image information signal which is to be stored or already stored is transferred as a digital signal.

  In the case of Non-Patent Documents 1 and 2, it is a camera device, and has an imaging means for generating an electrical image information signal from an optical image, whereas in Non-Patent Document 3, it has such means. The image information signal is generated by a personal computer. The image information signal generated by the personal computer is transmitted to the device described in Non-Patent Document 3 and temporarily stored in the first memory. Next, the image information signal read from the first memory is subjected to image data compression processing by a DCT (Discrete Cosine Transform) method, and sent back to the personal computer. Such an operation is similar to the operation of the device block shown in FIG.

  Here, since the writing or reading operation of the image information signal in the apparatus described in Non-Patent Document 3 is executed under the time management of the connected personal computer, the writing of the information data in the first memory is performed. When the data of one image is being read out, the content is switched to the data of another image, and as a result, the image information is transformed. It can be avoided in advance.

  In the apparatus described in Non-Patent Document 3, the data output from the apparatus to the personal computer is synchronized with the clock output from the personal computer when the image data is compressed and the compressed image information signal is output. However, since the compression processing of the image data is performed by an independent clock inside the apparatus, that is, a clock asynchronous with the clock output from the personal computer, a so-called FIFO (Fast In / Fast Out) type buffer memory is used. It has.

  Here, the operation of the FIFO memory will be described with reference to FIG.

  In the figure, the FIFO memory 21 has data storage areas at memory addresses 0, 1, 2,..., N, n + 1,. When the memory 21 starts operating, data is first written in the order of address 0, 1, 2,. The update of the write address is performed every time the clock inside the apparatus is repeated. When data is written to address n, data reading is started from address 0 at this timing, and data is read in the order of 1, 2,... The read address is updated at every repetition timing of the external clock supplied from the personal computer to the device. Thereafter, the read address is also updated so as to follow the sequentially updated write address. Both writing and reading are controlled to return to address 0 again at the next clock timing when the address reaches address m.

  When the FIFO-type memory is operated as described above, the address offset amount in the initial state of writing and reading is Aos (= n), and the address of writing and reading when the write address becomes the final address m of the buffer memory When the offset amount is A'os (= mn) and the repetition cycle of the external read clock is T, the timing of the write clock with respect to the read clock generation timing is maximum Aos × T in the delay direction, the advance direction Thus, even if the maximum deviation is A′os × T, the data can be read correctly in the order written in the memory. In other words, data transfer can be performed correctly between systems operating with asynchronous clocks by interposing a FIFO buffer memory.

  However, when a FIFO type memory is used, a write clock (in the compressed data output operation mode of the device described in Non-Patent Document 3 is a clock inside the device) and a read clock (in the same mode, from the personal computer to the device). It is not possible to set them without any interrelation. For example, regarding the difference in repetition frequency between clocks, the amount of address offset regulated by the capacity of the buffer memory to be used becomes a limiting factor, and the start timing of the read operation is time-controlled with respect to the timing of the write operation. It must be.

  The apparatus described in Non-Patent Document 3 further receives a compressed image information signal from a personal computer, restores it to the original uncompressed image information signal by an internal data decompression circuit, and stores it in the first semiconductor memory. It also has a function of storing and then returning this restored image information signal to the personal computer. Even in such an operation, since the operation timing of this apparatus is executed under the control of the connected personal computer, the writing of the image information signal not subjected to the compression process supplied from the computer to the first semiconductor memory is performed. In addition, it is possible to avoid a situation in which the restoration image information signal writing to the memory overlaps in time.

  In this operation, the FIFO type memory operates using a clock supplied from a personal computer as a write clock and using a clock inside the apparatus as a read clock. The relationship between the two clocks is as follows. This is the same as the output operation of the compressed image information signal described above.

In the device described in Non-Patent Document 3, the FIFO type memory is connected so that an operation mode in which writing by the clock inside the device and writing by the clock from the personal computer overlap in time does not occur. A personal computer program to be used is configured.
“The Image Coding System for Digital Still Cameras” by Sasaki et al., “Journal of the Television Society,” Vol. 46, No. 3 (1992) pp. 300-307. Catalog “FUJIX DIGITAL STILL CAMERA SYSTEM” published by Fuji Photo Film Co., Ltd. (September 1991) "FSA2001 Overview Document" published by FUJIFILM Microdevices Co., Ltd. (June 24, 1991)

  By the way, the electronic circuit for an imaging device such as an electronic camera disclosed in Non-Patent Documents 1 and 2 can be realized with an extremely small circuit block by using the recent highly integrated LSI technology and high-density substrate mounting technology. For this reason, especially when trying to make a small camera using a single focus optical lens or the like, in the method using the memory card shown in the non-patent document, the space for storing the memory card, the memory card loading The mounting space for the connector for the device or the space for the mechanism for removing the memory card is a major factor that hinders downsizing.

  In addition, it is conceivable to reduce the size of the device and the size of the memory card. However, removing a smaller memory card from the downsized device is cumbersome and causes the device to fall accidentally when it is removed. For example, the device may be destroyed.

  The inconvenience caused by the insertion / removal of the memory card as described above can be solved by providing a connector for inputting / outputting image information signals in the image pickup apparatus so that signals can be directly exchanged with external devices via this connector. . However, the image pickup apparatus is provided with a recording switch corresponding to a shutter button of a conventional film camera, and by an operation of closing the recording switch, an arbitrary external device connected to the connector is desired by the operator. There is a case where an operation of capturing an optical image in the apparatus at a timing that is not restricted by the operation state of the apparatus and recording it in the semiconductor memory as an electric signal is executed or desired to be executed. For example, when the recording switch is closed and the recording operation in the apparatus has not yet been completed, an external device is attached to the connector, or an image is recorded without missing a photo opportunity at a certain moment. is there. Therefore, when the imaging apparatus is provided with the connector as described above, the information writing in the semiconductor memory is prevented from being changed due to overlapping information writing and reading, or the information writing by operating the recording switch is performed. And the writing of information input from an external device compete with each other in the same semiconductor memory, and all device operations are centrally managed by a computer in order to avoid inconveniences such as transformation of image contents. New operation management different from the apparatus described in Non-Patent Document 3 is required.

  Furthermore, a personal computer can be considered as an external device that exchanges image information with the imaging device. In this case, an information transmission clock that is completely uncorrelated with the system operation clock inside the imaging device is input from the personal computer to the imaging device. If information can be exchanged, it is extremely effective from the viewpoint of versatility and operability.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a small-sized imaging device that takes the above points into consideration, prevents malfunctions, and has excellent versatility and operability.

  To achieve the above object, the present invention provides a semiconductor memory, a device operation start instruction means such as a recording switch, and an image information signal obtained by imaging in conjunction with an operation start instruction by the device operation start instruction means. In order to output an image information signal stored in the semiconductor memory to the outside of the apparatus or to input a signal to be stored in the semiconductor memory into the apparatus And detecting that the first connector is fitted to the second connector of the external device or the like, or a signal supplied from the external device via the first connector. By detecting this, a first state in which the image information is prepared to be exchanged with an external device or in the exchange execution state is detected, and the recording switch is closed. State detecting means for detecting the second state in the state of writing the image information signal to the semiconductor memory linked to the semiconductor memory, and when the state detecting means detects the first state, the recording switch is closed. When writing of a new image information signal to the semiconductor memory linked to the generation or the like is prohibited and the state detecting means detects the second state, the state of the image information exchange with the external device is changed to the execution state. Prohibit migration.

  The state detection means includes a switch that is pressed and closed when, for example, the first connector and the second connector are engaged, and the switch outputs an electrical signal while the connectors are in the engaged state. To do. Alternatively, for example, after the above-described connectors are fitted, a signal input from an external device through the connectors before the execution of image signal exchange with the external device is detected, and an electrical signal is output. However, in the period in which the semiconductor memory is in the image information signal writing operation mode in conjunction with the closing of the recording switch or the like, the imaging apparatus is prohibited from outputting the electrical signal.

  The present invention relates to an image information signal linked to closing of a recording switch in a semiconductor memory to be accessed for transmission / reception of an image information signal to / from an external device when there is an output electric signal of the state detection means. Is controlled to be prohibited from being written.

  With the above operation, in the present invention, when image information is exchanged with an external device, even if a situation occurs in which the user accidentally operates the recording switch, the image information is exchanged. The content of the image is not changed. Also, for example, by providing a buffer memory for temporary storage in the previous stage of the semiconductor memory, it is possible to take an image even during a signal exchange operation period with an external device.

  When the output of the electrical signal from the state detection means is prohibited, the access state of the semiconductor memory selected to write the image information signal in conjunction with the closing of the recording switch or the like is maintained, and the access from the external device Transitioning to a possible state is prohibited.

  With this operation, in the present invention, even when a series of operations for recording a photographed image is continued, a connection operation with an external device or the like can be executed without changing the contents of the image.

  In the present invention, the writing of the image information signal linked to the recording switch, which is an internal operation of the apparatus, and the reading / writing of the image information signal, which is an exchange operation with an external device of the apparatus, are independently performed in a time division manner. Since there is no time constraint on the operation timing between the divided and divided operations, a system operation clock and a non-correlated clock can be supplied from the outside of the device to exchange image information with the device. .

  According to the present invention, the memory built in the imaging apparatus for storing the captured image information includes the signal switching means and the signal transmission connector for accessing the memory from outside the apparatus. Even when information stored in the memory is exchanged with an external device, it is not necessary to remove it, and the apparatus can be reduced in size, and it is not necessary to attach or detach the memory, improving usability.

  Along with this, there is provided means for detecting the preparation state and execution state of the access operation from the outside of the device of the memory, and when such state is detected, it is configured to wait for execution of writing of the captured image to the memory. In addition, a means for detecting whether the captured image is written to the memory is in a ready state or in an executing state, and when such a state is detected, an access operation of the memory from an external device is performed. Since it is configured to wait for execution, it is possible to execute an instruction at an arbitrary timing of writing operation of a captured image by a user's operation without changing the image information. Even if the above instruction is given at the time of signal exchange, the contents of the image information being exchanged will not change. In addition, when the captured image is written to the memory, even if the captured image is connected to an external device via the connector, the content of the captured image being written does not change.

  Further, when the memory has a recording area for a plurality of images, the captured image writing operation by the user's operation can be performed at an arbitrary timing even during the period of signal exchange with the external device. With this instruction, it is possible to take an image at this timing, and it is possible to shoot without missing a chance.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an embodiment of an imaging apparatus according to the present invention, in which 1 is an imaging device, 2 is a timing generation circuit, 3 is an oscillator, 4 is a power switch, 5 is a recording trigger switch, and 6 is an AND gate. , 7 is a timing generation circuit, 8 is an oscillator, 9 is an inverter, 10 and 11 are switches, 12 and 13 are semiconductor memories, 14 is a connector, 15 and 16 are switches, 17 is a camera signal processing circuit, 18 is a switch, 19 Is an output terminal, 21 is an image data compression processing circuit, 22 is an image data decompression processing circuit, 23 is a state detector, and 24 is a switch.

  In this figure, when the user closes the power switch 4, the timing generation circuit 2 constituted by a microcomputer or a logic circuit detects this, and operates a power circuit (not shown) to start supplying operating power to each part. At the same time, the first reference frequency signal supplied from the oscillator 3 is appropriately subjected to a process such as frequency division, and the operation clock pulses CK1, CK3, CK2 of the image pickup device 1, the camera signal processing circuit 17, and the encoder 19, respectively. Switch control signals SW1, SW2, and SW3 are generated. These switch control signals SW1, SW2, and SW3 close the switches 10, 16, and 18 in the illustrated direction. These switches 10, 16, and 18 can be easily configured by a known multiplexer circuit based on logic circuit technology.

  An analog image information signal AIS obtained by photoelectrically converting an optical image is output from the image sensor 1 in which an optical lens (not shown) is mounted on the light receiving surface. The camera signal processing circuit 17 is a circuit known in television cameras such as a correlated double sampling circuit, an automatic gain adjustment circuit, a matrix circuit, and a gamma processing circuit, and A / D (analog / analog) is provided in the middle of the signal path of the circuit configuration. A digital) converter is arranged to output a digitized baseband digital image information signal DIS. The digital image information signal DIS is supplied to the encoder 19 via the switch 18, and a chroma signal modulated to a subcarrier is generated from the baseband digital image information signal DIS, and one of the baseband luminance signal and the clock pulse CK1 is generated. As a unit, the timing is synchronized with the synchronization signal supplied from the timing generation circuit 2, and these are combined and output from the output terminal 20 as a composite video signal or as an independent component signal.

  The encoder 19 has a D / A (digital / analog) converter and outputs an analog image information signal to the output terminal 20. Here, by connecting a known television monitor device to the output terminal 20, a continuous (moving image) image captured by the image sensor 1 can be displayed as a television image.

  The above operation is the same as that of a known television camera device, and can be realized by using, for example, a commercially available television camera circuit of a VM-H39 type VTR integrated camera manufactured by Hitachi, Ltd.

  Next, the operation of the electronic camera function of this embodiment will be described.

  The baseband digital image information signal DIS output from the camera signal processing circuit 17 is supplied to the semiconductor memory 12 via the switch 16. At this time, in the semiconductor memory 12, the clock CL and the address signal Ad generated in synchronization with the camera signal processing clock CK3 and the like by the timing generation circuit 2 via the switch 10 respectively. Supplied as signal WA.

  FIG. 3 is a timing chart showing the operation of the semiconductor memory 12. FIG. 3A shows the operation timing of the television camera circuit composed of the image sensor 1 and the camera signal processing circuit 17, and FIG. FIG. 4C shows the storage timing of the memory 12 and the operation mode of the semiconductor memory 13, respectively. In FIG. 3B, P1, P2, P3,... Represent sequential images (television signal field images or frame images) in the image information signal DIS. Images written to the semiconductor memory 12 are also represented by the same reference numerals.

  1 and 3, when the power switch 4 is closed at time T1, the television camera circuit starts the operation described above, and the image information signal DIS is generated. The semiconductor memories 12 and 13 generally have a memory capacity capable of recording data for one field image or one frame image.

  In general, the writing of image data to the semiconductor memory 12 is executed by rewriting the previously written image data to new data by a predetermined amount of data (for example, 8 bits) in time sequence. . Here, when recording a natural image with an electronic camera or the like, a data amount of at least a kilobit unit per image is required, so even after starting to write one image data, this one image Until the data writing is completed, the previously written image data remains in the semiconductor memory. That is, for example, in FIG. 3B, in the time domain indicated by P2, not only the data of the image P2 is stored in the semiconductor memory 12, but the data of the image P1 written before that and the current data The data of the image P2 to be written is mixed and stored.

  Also, in FIG. 3, the portion indicated by the term “hold” such as “P4 hold” is written with new image data (that is, image data after writing of one image data is completed). It is shown that the image data is stored as it is without rewriting.

  After time T1, in the semiconductor memory 12, the images P1 to P4 generated by the camera signal processing circuit 17 are sequentially written, and the image data is updated each time. When the recording trigger switch 5 is closed by the user (time T2), when the writing of the data of the image P4 being written at this time is completed, the next data writing to the semiconductor memory 12 is prohibited, and this image The semiconductor memory 12 is controlled so that the data of P4 is held (frozen). This control is executed by the timing control circuit 2 stopping the generation of the clock CL at the timing of the vertical synchronization signal of the image information signal AIS. Subsequently, the timing control circuit 2 generates an operation control signal MC. As will be described later, the operation control signal MC is supplied to the timing generation circuit 7 via the AND gate 6 that is controlled to open and close in accordance with the output signal SD of the state detection circuit 23, and starts its operation.

  The timing generation circuit 7 appropriately divides the reference signal supplied from the oscillator 8, and the driving clock CL 1 and address signal Ad 1 of the semiconductor memory 12, the image data compression processing circuit 21, and the image data expansion processing circuit 22. Operating clocks CK4 and CK5, a driving clock CL2 of the semiconductor memory 13 for storing the compressed image data CID, an address signal Ad2, and a read / write switching signal (R /-) for switching and controlling the read operation and the write operation. A circuit for generating W2), which can be constituted by a known logic circuit. The read / write switching signal (R / -W2) indicates, for example, “read” when “H” (high level) and “write” when “L” (low level). .

  When receiving the operation control signal MC, the timing generation circuit 7 starts the compression process of the image data and the writing operation of the compressed image data CID into the semiconductor memory 13.

  That is, the clock CL1 and the address signal Ad1 output from the timing generation circuit 7 are supplied to the semiconductor memory 12 through the switch 10 as the read clock RC and the read address signal RA. As a result, the data of the stored image P4 is sequentially read from the semiconductor memory 12, and compressed by the compression processing circuit 21 to obtain compressed image data CID. By using a FIFO type semiconductor memory as the semiconductor memory 12, as described with reference to FIG. 2, reading of the data of the image P4 is started even during the data writing period of the image P4 of FIG. 3B. Can do. Further, the write clock WC and the read clock RC may be asynchronous.

  The compressed image data CID output from the compression processing circuit 21 is supplied to the data input / output terminal I / O of the semiconductor memory 13, and also indicates the clock CL2, the address signal Ad2 output from the timing generation circuit 7 and "write". The read / write switching signal (R / −W2) to be supplied is supplied to the semiconductor memory 13 via the switch 11 as the clock CL, the address signal Ad, and the read / write switching signal (R / −W). ), The data of the image P4 compressed in the period indicated by P4 is written into the semiconductor memory 13.

  Here, the semiconductor memory 13 is a memory that is switched between a writing mode and a reading mode of image data by a reading / writing switching signal (R / -W), and the reading / writing switching signal (R / -W) is "H". When "", write mode is selected. At this time, the data input / output terminal I / O is used for data input, and the clock CL and the address signal Ad are used as a write clock and a write address signal, respectively. When the read / write switching signal (R / −W) is “L”, the read mode is set. At this time, the data input / output terminal I / O is for data output, and the clock CL and the address signal Ad are used as a read clock and a read address signal. A semiconductor memory circuit that is used by switching between writing and reading is also known.

  By the way, in this embodiment, when the device is downsized, the data compression circuit 21 and the data decompression circuit 22 employ a small circuit formed as an LSI. It takes a longer processing time to generate one piece of compressed image data than to generate one piece of image data in operation. For this reason, the semiconductor memory 12 is used as a buffer memory, and it is possible to capture an image at a high speed of the camera operation. At this time, the image P4 data is held in the semiconductor memory 12 until the compression processing of the data of the image P4 and the writing to the semiconductor memory 13 is completed, thereby preventing the change of the image contents. Yes. In order to perform this operation, the closing information of the recording trigger switch 5 is captured during a period from when the timing generation circuit 2 outputs the operation control signal MC to when the operation end signal ME is supplied from the timing generation circuit 7. Do not.

  In FIG. 3C, the timing generation circuit 7 stops the generation of the write clock CL2 when the writing of the data of the compressed image P4 is completed, and thereafter the semiconductor memory 13 holds the data of the image P4. The operation end signal ME is sent to the timing generation circuit 2. Upon receiving the operation end signal ME, the timing generation circuit 2 stops the generation of the operation control signal MC and starts the write operation of the semiconductor memory 12 again, and sequentially stores the data of the images P5, P6, and P7 to the semiconductor memory 12. Write and prepare for the next closing operation of the recording trigger switch 5.

  It is conceivable to use a semiconductor memory 13 having a data storage capacity for a plurality of images. At this time, in the data write operation period indicated by P4, P7, etc. in FIG. 3C, only a partial area allocated to one image is newly stored in the image data storage area of the semiconductor memory 13. Rewritten to image data. In addition, in the period indicated by “Hold” in FIG. 3C, not only the image data written immediately before this but also the image data written before this is held. Further, when the semiconductor memory 13 is, for example, a static random access memory backed up by a battery or a so-called flash type nonvolatile memory, the time before the data writing time of the image P4 in FIG. Data of the image Px recorded at the time of photographing before the current photographing started by closing the power switch 4 at T1 is held.

  FIG. 3 further shows a memory operation when the recording trigger switch 5 is closed again (time T3) during the period in which the data of the image P7 is written to the semiconductor memory 12. Since the operation in this case is the same as the data recording operation of the image P4, the description thereof is omitted.

  The operation of the electronic camera function (still image recording function) of this embodiment has been described above with reference to FIG. 3, and this is similar to the operation of the apparatus shown in Non-Patent Documents 1 and 2 above.

  When the semiconductor memory 13 is a flash memory, the image data cannot be rewritten by so-called overwriting because of the element configuration. Therefore, at the timing of the image P4 in FIG. 3C, before the data of the image P4 is written, the image data remaining in the memory area allocated as the data writing area of the image P4 is temporarily erased. Is executed. Specifically, this erasing operation is an operation of writing data of a predetermined logic level in the semiconductor memory. For example, a control (not shown) output from the timing generation circuit 7 on the output side of the data compression circuit 21 in FIG. A logic gate controlled to output a predetermined level of data according to a signal may be provided so that the predetermined level of data is written prior to writing of the data of the image P4.

  Also known as flash type memory devices are those in which a code signal supplied to the data input / output terminal I / O is fetched into the memory device using several kinds of control signals and the operation mode such as writing and erasing is switched. is there. Furthermore, when erasing or writing, a so-called ready / busy signal generation function is provided that warns to generate data of a predetermined logic level and wait for progress to the next operation until the internal operation of the memory element is completed. What it has is also known. Even when such a memory element is used, a semiconductor memory is provided so that a plurality of switching signals for the switch 11 are provided as necessary, and a control code is appropriately switched to image data and supplied to the data input / output terminal I / O terminal. It can be configured by a known technique in the field of digital circuit technology using. Further, an interface circuit can be provided between the switches 11 and 15 of FIG. 1 and the semiconductor memory 13 in accordance with the function of the memory element to be used.

  As described above, when the image information signal is recorded, when the semiconductor memory 13 is a flash memory, the erasing operation is executed in conjunction with the user so that the user is bothered by the erasing operation unique to the flash memory. Therefore, it can be operated with the same feeling as a conventional memory device capable of automatic rewriting by overwriting.

  The feature of this embodiment is to prevent the operation of the timing generation circuit 7 and the state detection circuit 23 that detects the preparation state of the signal exchange operation with the connector 14, the switches 11 and 15, and the external device. The AND gate 6 is provided so that digital image information signals can be exchanged between the external device and the semiconductor memories 12 and 13.

  Hereinafter, this point will be described with reference to FIGS. 4 and 5. However, FIG. 4 is a block diagram showing a specific example of the state detection circuit 23 in a state where an external device is connected to the connector 14 of FIG. 1, wherein 23a is a T-FF (T-type flip-flop), and 23b is an AND. A gate, 23c is an OR circuit, 25 is an external device, 25a is a connector, and the same reference numerals are given to portions corresponding to FIG.

  FIG. 5 is a timing chart for explaining the function of exchanging signals with an external device. Signals corresponding to those in FIG. 5A, 5B, and 5C are the same as FIGS. 3A, 3B, and 3C, respectively.

  First, in FIG. 1 and FIG. 5, at time T1 when the power switch 4 is turned on, as described above, already recorded image data is held in the semiconductor memory 13, and the timing generation circuit 7 operates. Therefore, the operation end signal ME becomes “H” to indicate the operation end state. When the recording trigger switch 5 is closed at time T2 and writing of the data of the image P4 to the semiconductor memory 13 shown in FIG. 5C is started by the series of operations described above, the level of the operation end signal ME is “ L "indicates that the timing generation circuit 7 is operating.

  Next, in FIG. 4 and FIG. 5, the operation end signal ME is supplied to the AND gate 23b of the state detection circuit 23 as one input. The other input of the AND gate 23b is a signal exchange supplied from the external device 25 via the connectors 25a and 14 when the connector 25a of the external device 25 is fitted to the connector 14 and the external device is connected. It is a signal CSSa (hereinafter referred to as a preparation status instruction signal) indicating an operation preparation status. The output of the AND gate 23b is supplied to the clock terminal T of the T-FF 23a as a trigger clock.

  The reset terminal R of the T-FF 23a is supplied with an initial reset signal INS when the operation power is turned on by the power switch 4 (FIG. 1) via the OR gate 23c. The initial reset signal INS is generated for a predetermined minute time after power-on, and is used to reset each logic circuit to a predetermined initial state. Such a reset technique is well known in the logic circuit technical field. A dedicated IC for generating a reset signal at the start of power supply is also commercially available. Therefore, the reset signal generation IC may be provided as a component of the state detection circuit 23, but the output signal of the reset signal generation circuit provided in the timing generation circuit 2 may be used as the initial reset signal INS.

  The Q output of the T-FF 23a is output as the state detection signal SD. As shown in FIG. 5, the state detection signal SD is reset from the undefined state (an undefined state of “H” or “L”) to the “L” state at time T1, as shown in FIG. When the state detection signal SD is “L”, the switches 11 and 15 in FIG. 1 are in the state shown in FIG. Further, the “L” state detection signal SD is inverted to “H” by the inverter 9 of FIG. 1, and the AND gate 6 is made to pass the operation control signal MC. As a result, as described with reference to FIG. 3, the image P4 data is written to the semiconductor memory 13 in conjunction with the closing of the recording trigger switch 5 at time T2.

  Here, it is assumed that the preparation status instruction signal CSSa of “H” is supplied from the external device 25 to the state detection circuit 23 at time T4, which indicates that the preparation for signal transmission / reception is completed by the external device 25. At this time, when the operation end signal ME changes to “H” with the completion of the operation of the timing generation circuit 7 due to the completion of the writing of the data of the image P4 to the semiconductor memory 13, the T-FF 23a is triggered at this timing and the state is reached. The detection signal SD is inverted to “H”.

  When the state detection signal SD becomes “H”, the switches 11 and 15 in FIG. 1 are switched in the direction opposite to that shown in FIG. The switch 11 that is a unidirectional digital signal switch can be easily configured by, for example, a multiplexer circuit, and the switch 15 that is a bidirectional switch can be easily configured by, for example, a so-called analog switch circuit. It is well known in the field.

  The state detection signal SD is supplied to the external device 25 via the connectors 14 and 25a, and notifies the external device 25 that the image pickup apparatus is in a state capable of performing a signal transmission / reception by its level being “H”.

  Therefore, when the external device 25 receives this state detection signal SD, in FIG. 1, via the switch 11, the external device 25 sends a clock CL3, an address signal Ad3, and a read / write switching signal (R / −W3) instructing reading to the semiconductor memory. 13 is supplied. As a result, the semiconductor memory 13 reads, for example, one specific image or all of the image data from the recording area designated by the address signal Ad3, and switches 15 and connectors from the data input / output terminal I / O terminal. 14 to the external device 25 (FIG. 4). At this time, the operation of the semiconductor memory 13 is exclusively controlled by the external device 25.

  4 and 5, when the external device 25 reads the desired image data from the semiconductor memory 13, the external device 25 stops outputting the clock CL3 and returns the preparation status instruction signal CSSa to "L". An end signal CSSb is supplied to the state detection circuit 23. The transfer operation end signal CSSb is supplied to the T-FF 23a via the OR gate 23c, and resets the state detection signal SD to "L".

  When the external device 25 is a personal computer, a signal having a relatively low frequency is often used as the signal transmission / reception clock CL3 (FIG. 1), but the frequency is determined only by the constraints of the external device 25 alone. It is convenient to be able to do it. In general, when a low-cost external device 25 is used, its data processing capability is low, so it is preferable to send and receive signals using a low-frequency clock, and any external device with high processing capability. This is because it is desired to complete the transfer operation in a short time with a high-speed clock. For this reason, it is conceivable that the time required for signal exchange with the external device 25 varies depending on the model of the external device to be used even if the amount of signal data to be exchanged is the same.

  In this embodiment, the state detection signal SD is supplied also for controlling the AND gate 6 inserted in the transmission path of the operation control signal MC instructing the operation start of the timing generation circuit 7, and the state detection signal SD is “H”. ”, The operation control signal MC is blocked by the AND gate 6, and at least the semiconductor memory 13 among the image data writing linked operations to the semiconductor memories 12 and 13 executed by closing the recording trigger switch 5. The writing of new image data to the memory device is prohibited, and the image data in the semiconductor memory 13 is prevented from being altered and the image content being transformed during an indefinite time required for signal exchange with the external device 25.

  FIG. 5 illustrates the operation of the embodiment having the above-described configuration. However, for example, when the state detection signal SD is “H”, the timing generation circuit 2 is arranged so as to ignore the closing of the recording trigger switch 5. Can be configured by a known technique in the logic circuit technical field, and alteration of the image data in the semiconductor memory 13 can be prevented. In this case, however, all operations by operating the recording trigger switch 5 are naturally prohibited.

  In FIG. 5C, when the writing operation of the image P4 in the semiconductor memory 13 is completed and the operation end signal ME is inverted to “H”, the images P5 and P6 to the semiconductor memory 12 as described in FIG. , P7 is resumed (FIG. 5B). When the recording trigger switch 5 is closed at time T3, the image P7 is held in the semiconductor memory 12, but since the state detection signal SD is “H”, the operation control signal MC is generated by the AND gate 6. Blocked and not supplied to the timing generation circuit 7, the timing generation circuit 7 does not start operation. For this reason, the semiconductor memory 13 is prohibited from writing data of the image P7 and retains the previous image data.

  In this way, not only the switching operation of the switches 11 and 15 but also the operation of the timing generation circuit 7 is prohibited, so that unnecessary circuit operation can be omitted and power consumption can be suppressed.

  When the reading of the data of the image P4 to the external device 25 is completed and the state detection signal SD output from the state detection circuit 23 by the transfer operation end signal CSSb becomes “L”, the switches 11 and 15 are again illustrated in FIG. The direction is switched. The AND gate 6 is also allowed to pass, and the operation control signal MC is supplied to the timing generation circuit 7. As a result, the timing generation circuit 7 starts operating, the operation end signal ME becomes “L”, and the compressed image P7 data is written into the semiconductor memory 13 at the timing shown in FIG. When this writing is completed, the operation end signal ME becomes “H” again, and the preparation status instruction signal CSSa becomes “H” again, indicating that the external device 25 is ready for signal transmission / reception. As a result, the state detection signal SD is inverted to “H” to notify the external device 25 that the imaging apparatus is in a state where it can exchange signals again.

  As described above, according to the operation of this embodiment, during data reading from the semiconductor memory 13 to the external device 25, data writing to the semiconductor memory 13 is prohibited, or data writing to the semiconductor memory 13 is in progress. Since the data reading to the external device 25 is prohibited, the image data in the semiconductor memory 13 is not rewritten during the data reading operation of the semiconductor memory 13 to the external device 25. Accordingly, it is possible to prevent a plurality of image data from being mixed and output instead of one captured image data. Therefore, one image obtained by capturing an image reproduced using this output data. It is possible to avoid changing to something different.

  Further, in the case where the output of the operation control signal MC is made to wait, the image data is taken into the semiconductor memory 12 by the closing operation of the recording trigger switch 5 during the data reading to the external device 25, that is, Shooting can be performed, and the image information captured here is automatically transferred to the semiconductor memory 13 and recorded as soon as the data reading to the external device 25 is completed, without requiring a new operation by the user. be able to. Further, when the data writing to the semiconductor memory 13 is completed, the state detection signal SD is automatically inverted to “H” in conjunction with this, and this embodiment is switched to a state in which signals can be exchanged with the external device 25. Since the connected external device 25 can be notified of this state, the image data recorded in the semiconductor memory 13 can be continuously read by the external device 25 with a shorter waiting time. Become.

  Further, the preparation status instruction signal CSSa is not limited to the level change timing as shown in FIG. 5, but may be maintained, for example, after it is once inverted to “H”. Each time the writing of new image information in 5 (c) is completed and the operation end signal ME is inverted from “L” to “H”, a signal can be automatically exchanged with the external device 25. .

  In addition, when the preparation status instruction signal CSSa is defined so as to return from “H” to “L” at the end of signal exchange by the external device 25 as shown in FIG. It is not necessary to supply from the external device 25. For example, a pulse signal having a predetermined pulse width is generated in synchronization with the edge timing of the preparation status instruction signal CSSa that is inverted from “H” to “L”. For example, a known logic circuit configuration such as a monostable multivibrator circuit is incorporated in the state detection circuit 23, and a preparation state instruction signal CSSa is supplied to the state detection circuit 23 to obtain a pulse signal corresponding to the transfer operation end signal CSSb. it can.

  In FIG. 5, when the image data holding timing by the preparation status instruction signal CSSa, that is, when the preparation status instruction signal CSSa is inverted to “H” within the “H” period of the operation end signal ME, the state detection circuit 23 immediately The “H” state detection signal SD is output, and the image pickup apparatus of this embodiment enters a signal exchange state with the external device 25. In particular, the operation end signal ME is linked to the closing of the recording trigger switch 5 to “H”. When the preparation status instruction signal CSSa is inverted from “L” to “H” immediately before switching from “L” to “L”, a noise signal having a minute pulse width is generated from the AND gate 23b in FIG. May trigger the state detection signal SD to be inverted to “H”. Further, when the preparation status instruction signal CSSa is inverted to “H” before the time T1 or in the vicinity of the time T1, the operation of the T-FF 23a is uncertain due to a conflict with the reset control of the T-FF 23a by the initial reset signal INS. There is a risk of becoming.

  FIG. 6 is a circuit diagram showing another embodiment of the state detection circuit 23 in FIG. 1 which is also suitable in such a case. 23d is an inverter, 26-29 are resistors, 30 is a transistor, 31 and 32 are capacitors. , 33 are power supplies, and parts corresponding to those in FIGS. 1 and 4 are given the same reference numerals.

  FIG. 7 is a waveform diagram showing signals at various parts in FIG. 6, and the signals corresponding to those in FIG.

  In FIG. 6, the state detection circuit 23 is provided with a fitting detection switch 24, and when a connector 25a of an external device (not shown) is fitted to the connector 14 (time T1), the fitting detection switch 24 is provided. Is pressed to close the circuit, and the “H” voltage signal SV from the power supply 33 is supplied to the AND gate 23b. This “H” voltage signal SV replaces the preparation status instruction signal CSSa in the specific example shown in FIG. The resistor 28 is for keeping one input of the AND gate 23b at the ground ("L") level when the fitting detection switch 24 is opened.

  Accordingly, as shown in FIG. 7A, when the apparatus power is turned on by closing the power switch 4 in FIG. 1 in the fitted state of the connectors 25a and 14, as shown in FIG. The instruction signal CSSa is the same as the inversion from “L” to “H” at time T1.

  In this specific example, the operation end signal ME is supplied as the other input of the AND gate 23b via the resistor 26. The capacitor 31 and the transistor 30 are connected between the input terminal of the AND gate 23b and the ground. Are connected in parallel. The initial reset signal INS is supplied to the base of the transistor 30 via the resistor 27.

  Therefore, as shown in FIG. 7A, when the initial reset signal INS of “H” is generated when the power is turned on, the signal period transistor 30 becomes conductive, so that the operation end signal ME of the AND gate 23b is supplied. The input level ADI on the other side is kept at “L”. When the initial reset signal INS becomes “L” after a lapse of a predetermined time, the transistor 30 is turned off. At this time, if the operation end signal ME is “H”, the resistance 26 and the capacitor 31 After a time delay determined by the time constant, the input level ADI becomes “H”. During this time delay, since the T-FF 23a is reset by the initial reset signal INS, the output ADO of "1 level" of the AND gate 23b obtained by the input level ADI becoming "H" causes T -FF 23a can be reliably triggered to generate a state detection signal SD.

  FIG. 7B shows an “H” operation control signal MC output at time T2 ′ from the operation of the timing generation circuit 2 in conjunction with the closing operation of the recording trigger switch 5 (FIG. 1) at time T2. And the operation when the fitting detection switch 24 is closed and the timing at which the voltage signal SV of “H” is supplied from the power source 33 to the AND gate 23b competes.

  When the timing generation circuit 7 (FIG. 1) starts operation by the “H” operation control signal MC generated from the timing generation circuit 2 (FIG. 1) at time T2 ′, the operation end signal ME changes from “H” to “L”. In general, from the time T2 ′, due to the operation delay depending on the signal propagation speed of the circuit element or the phase relationship between the operation clock of the timing generation circuit 7 supplied from the oscillation 8 and the operation control signal MC, etc. There is a time difference until the operation end signal ME is inverted to “L”. When the voltage signal SV from the fitting detection switch 24 is inverted from “L” to “H” during this time difference period, a pulsed “H” output signal ADO is generated from the AND gate 23b only for a short period. When the T-FF 23a is triggered by the output signal ADO, the state detection signal SD is inverted to “H”, and the switches 11 and 15 (FIG. 1) are kept in spite of the operation of the timing generation circuit 7 as it is. ) Is connected to the access side of the external device, the image data photographed at time T2 cannot be stored in the semiconductor memory 13 (FIG. 1).

  Therefore, in the specific example shown in FIG. 6, the following configuration is provided in order to avoid such a situation that photographing is invalidated.

  That is, the OR circuit 23c is supplied with the operation end signal ME whose level is inverted by the inverter 23d in addition to the transfer operation end signal CSSb and the initial reset signal INS as shown in the specific example shown in FIG. When the operation end signal ME is inverted to “L”, the T-FF 23a is reset thereby, and the state detection signal SD once inverted to “H” is returned to “L” again. . Thereby, it is possible to effectively write the image information to the semiconductor memory 13 by the operation of the timing generation circuit 7.

  At this time, the condition for generating the state detection signal SD having a pulsed waveform of “H” as shown in FIG. 7B is that the voltage signal SV from the fitting detection switch 24 is inverted to “H”. The circuit operation delay time t1 until the AND gate 6 (FIG. 1) is closed by the state detection signal SD, and the operation end signal ME of “L” from the time when the operation control signal MC is inverted to “H”. That is, the voltage signal SV from the fitting detection switch 24 is inverted to “H” in a time region around the time T2 ′ defined by the sum of the delay time t2 until the “t” is reset. At this time, the times t1 and t2 can be predicted in advance from the speed performance of the circuit elements to be used, the circuit configuration to be used, and the like, and the state detection signal SD of “H” shown in FIG. The period is shorter than the period (t1 + t2).

  Therefore, by providing a circuit configuration for preventing the output of the signal having a predetermined pulse width or less at the output portion of the state detection signal SD to the connector 14, the “H” pulse-like state detection signal shown in FIG. It is possible to prevent the SD from being supplied to an external device. In FIG. 6, an integrating circuit comprising a resistor 29 and a capacitor 32 is used as such blocking means. Of course, other configurations that implement similar functions are also known in the logic circuit art. Note that even if such a pulse-like state detection signal SD is supplied to an external device as it is, it can be configured not to respond to the state detection signal SD with a minute pulse width assumed in advance on the external device side. As described above, the configuration in which the state detection circuit SD on the side of the state detection circuit 23 is configured to block the pulse-like state detection signal SD has fewer restrictions on the operation of the external device, and is troublesome when setting the operation program in the external device. Can be reduced.

  As another specific example of the state detection circuit 23, in FIG. 6, a gate is provided on the resistor 28 side of the fitting detection switch 24, and this is controlled by the gate signal GC shown in FIG. You may make it do. This gate signal GC becomes “H” at a time T2 when the recording trigger switch 5 is closed, that is, a predetermined time before the operation control signal MC, and the operation end signal ME is inverted to “L” and a predetermined time elapses. It is generated by the timing generation circuit 2 so as to return to “L” later, and during the “H” period of the gate signal GC, the voltage signal SV from the fitting detection switch 24 is blocked and the AND gate 23b. The voltage signal SV from the fitting detection switch 24 is prohibited from being inverted to “H” in the time domain (t1 + t2) of FIG. In this case, the output signal ADO of the AND gate 23b and the “H” state of the state detection signal SD shown after the time T2 ′ in FIG. Therefore, it is not necessary to supply the inverted signal of the operation end signal ME to the OR circuit 23c.

  The state detection circuit 23 shown in FIGS. 4 and 6 and the AND gate 6 and the inverter 9 in FIG. 1 are configured by hardware logic circuits. For example, a microcomputer is used, which is shown in FIG. The state may be detected by the initial reset signal INS, the operation end signal ME, the voltage signal SV, the gate signal GC, and the transfer operation end signal CSSb, and the operation control signal MC and the state detection signal SD may be generated based on the result.

  The above is the description of the image pickup operation and the image information output operation to the external device shown in FIG. 1. Next, the image reproduction operation of this embodiment will be described with reference to the operation time chart shown in FIG. explain.

  In this operation, in FIG. 1, the power switch 4 is closed to the state of the broken line in the direction opposite to that shown in the figure, thereby switching to the reproduction mode. In this case, the recording trigger switch 5 is a reproduction image forward selection switch. It is comprised so that it may have a function as. Such function switching can be easily realized by using a microcomputer or a logic circuit technique.

  1 and 8, when the user closes the power switch 4 to the regeneration mode side indicated by the broken line at time T1, the operation power supply is started and the regeneration operation is started as shown in FIG. 8A. Is done. At this time, as an initial operation, as shown in FIG. 8B, the data of the first image P1 is read from the semiconductor memory 13 in the image data holding state, and as shown in FIG. It is written in the memory 12. Such initial operation is executed as follows.

  The timing generation circuit 2 starts the reproduction operation by closing the power switch 4. At this time, the microcomputer in the timing generation circuit 2 is programmed so as to perform the next initial operation. That is, the timing generation circuit 7 is operated by the operation control signal MC to generate the clock CL2, the address signal Ad2, and the “L” read / write switching signal (R / −W2) instructing the read operation. In addition, an operation clock CK5 of the image data decompression circuit 22 that restores the compressed image data to uncompressed image data, and a clock CL1 for the semiconductor memory 12 and an address signal Ad1 are generated. Further, the switches 10, 16, and 18 are closed in the direction opposite to that illustrated by the switch control signals SW1, SW2, and SW3. Note that when the timing generation circuit 7 starts the initial operation, the operation end signal ME maintains “L” at time T1.

  Here, even if the preparation state instruction signal CSSa shown in FIGS. 4 and 5 indicates that the device is in a state of preparation for access from the external device to the semiconductor memory 13, as shown in FIG. 4 or the operation of the AND gate 23b shown in FIG. 6 does not invert the state detection signal SD to “H”. Accordingly, the switches 11 and 15 maintain the state shown in FIG. 1, and image data is read from the data input / output terminal I / O of the semiconductor memory 13 and processed by the image data decompression circuit 22. It is supplied to the semiconductor memory 12. At this time, the clock CL1 and the address signal Ad1 from the timing generation circuit 7 are supplied to the semiconductor memory 12 as the write clock WC and the write address signal WA, respectively.

  The above is the initial operation of the reproduction mode. Next, the operation of reading image data from the semiconductor memory 12 will be described.

  In this case, the clock CL and the address signal Ad output from the timing generation circuit 2 are supplied to the semiconductor memory 12 as the read clock RC and the read address signal RA, respectively. This data reading is performed by scanning the data area of the field image or frame image at the scanning speed of the television signal.

  The image data read from the semiconductor memory 12 is supplied to the encoder circuit 19 through the switch 18, converted into an analog video signal, and output from the output terminal 20.

  Now, in general, the supply of operating power is stopped at the same time as the supply of power is stopped, and in the semiconductor memory 12 that is not backed up by power, fake data with an indefinite level is stored at the time of the start of power supply at time T1. Therefore, in FIG. 8, at the time of the data writing operation of the image P1, the fake data is sequentially rewritten to the data of the image P1.

  Here, the restoration processing of one piece of image data by the image data decompression circuit 22 is also limited by the operation speed due to the same processing capability as the above-described image data compression processing operation. Therefore, in general, the time required for the image data decompression circuit 22 to restore one image data is longer than the image data read time for one image of the semiconductor memory 12 by the clock CL and the address signal Ad from the timing generation circuit 2. Will be longer. Thus, at time T1, data reading from the semiconductor memory 12 is started immediately with the clock CL and the address signal Ad from the timing generation circuit 2, and when the video signal is generated by the encoder 19 from the read image data, it is connected to the output terminal 20. On a display device such as a television monitor device, first, a fake image, generally in a mosaic pattern, is reproduced by the fake data, and then the image is decompressed by the image data decompression circuit 22. For example, an image display that gradually changes from the upper left corner of the displayed image is performed on the image based on the data of P1.

  Here, the recording area of the semiconductor memory 12 rewritten to the restored data is known from the status of the address signal Ad1 from the timing generation circuit 7, and the timing at which image data from other areas is output from the semiconductor memory 12 Thus, for example, by holding the input level of the encoder 19 at a predetermined value or the like, the output of the video signal signal due to false data at the time of rewriting is blocked, and for example, the portion of the screen that has not been rewritten can be displayed in gray. It is also possible to do. In addition, when the reproduction image is subsequently updated without stopping the power supply, the previously selected image is displayed so as to gradually change to the newly selected image.

  As is clear from the above description, there is a period in which a plurality of images are mixed in the image information output from the output terminal 20, but the television monitor device connected to the output terminal 20 is a specific one sheet. Since it is not a device used to extract images, there is no problem even if a mixed image is output transiently. On the contrary, it is better to be able to display the background of the image update on the monitor display. It is often preferable because it can be grasped.

  When the writing of the image P1 data to the semiconductor memory 12 is completed, the timing generation circuit 7 stops generating the clock CL1 and the clock CL2, and the semiconductor memory 12 enters the image P1 data holding mode, and the reading of the semiconductor memory 13 is completed. Operation stops. Further, the timing generation circuit 7 outputs an “H” operation end signal ME. At this time, as shown in FIG. 8, when the preparation status instruction signal CSSa is “H” and indicates a preparation state of signal transmission / reception by an external device, the state detection circuit 23 detects the state detection signal SD of “H”. Is generated. As a result, the switches 11 and 15 are switched in the direction opposite to that shown in FIG. 1, and the semiconductor memory 13 can be accessed by the external device connected to the connector 14.

  Here, the clock CL3, the address signal Ad3, and the “L” read / write switching signal (R / −W3) instructing data writing are supplied from the external device, and the image Pext data from the external device passes through the switch 15. By being supplied to the semiconductor memory 13, data of one image or a plurality of images can be written in the semiconductor memory 13 at the timing given Pext shown in FIG. Further, after the writing of the image P1 shown in FIG. 8C, when the preparation status instruction signal CSSa remains “L” unlike the case of FIG. 8, both the semiconductor memories 12 and 13 are in the data holding state. In this state, when the recording trigger switch 5 is closed at time T2 and selection of the next image is instructed, the timing generation circuit 2 immediately outputs the operation control signal MC, and the image P2 to the semiconductor memory 12 is output. Perform a write operation.

  In this embodiment, since the output of the operation control signal MC can be suspended during the period when the state detection signal SD is “H” even during the reproduction operation, as in the imaging operation described above, in FIG. When the state detection signal SD becomes “H” before the time T2, the transfer operation end signal CSSb indicating the end of the signal transfer operation is supplied from the external device until the state detection signal SD returns to “L”. During the period, the semiconductor memory 12 is kept in the data holding state, and when the state detection signal SD is inverted to “L”, the image P2 can be automatically written to the semiconductor memory 12. When the image P2 is rewritten in the semiconductor memory 13 at the timing of Pext in advance, the rewritten image is written in the semiconductor memory 12.

  In addition, when the signal transmission / reception with the external device is not performed in the connection state of the external device, it is natural that the preparation status instruction signal CSSa is kept at “L”. For example, as shown in FIG. When the voltage signal SV from the fitting detection switch 24 is used instead of the preparation status instruction signal CSSa as in the state detection circuit 23, every time the “H” state detection signal SD is transmitted through the connector 14. In addition, by sending back the transmission / reception operation end signal CSSb from the external device, the state detection signal SD immediately returns to “L” so that the operation by the closing of the recording trigger switch 5 can be started. The selection of the reproduced image by the operation 5 can be performed without delay.

  According to the image reproducing operation of this embodiment as described above, data writing from the external device to the semiconductor memory 13 is performed during a period in which the image data is read from the semiconductor memory 13 in order to write the reproduced image data to the semiconductor memory 12. In addition, while data writing from the external device to the semiconductor memory 13 is being executed, data reading from the semiconductor memory 13 and writing to the semiconductor memory 12 are prohibited. By such an operation, there is no possibility that a plurality of image data is mixed in the image data read from the semiconductor memory 13, and accordingly, the image data written in the semiconductor memory 12 or read from the image data and displayed on a television monitor or the like. The content of the generated image is not changed to a different image from the one image stored in the semiconductor memory 13.

  Further, the reproduction image update operation by closing the recording trigger switch 5 or the like is made to wait for a period of signal exchange with an external device, and the recording trigger switch 5 is continuously closed mechanically or electrically, for example. For example, the timing generation circuit 2 detects the open / close state of the recording trigger switch 5 at a predetermined timing such as every time the state detection signal SD is inverted from “H” to “L”. By programming the microcomputer, this embodiment can be operated so that an image written from an external device is immediately and automatically reproduced. A function equivalent to this can also be realized by using the signal transmission / reception operation end signal CSSb in place of the closing signal of the recording trigger switch 5. At this time, when the semiconductor memory 13 records a plurality of images, the image input from the external device is a single image by one writing operation, and the written image is matched with the read image. Therefore, a means for detecting an address signal supplied from an external device and loading the start address into a counter for generating an address signal Ad2 arranged in the timing generation circuit 7 is also used.

  When the state detection signal SD is “H” in FIG. 5 or FIG. 8, regardless of whether it is in the imaging mode as described in FIG. 4 or 5 or in the playback mode as described in FIG. By reversing the level of the read / write switching signal (R / -W3) supplied from the external device, data can be written from the external device to the semiconductor memory 13 or read from the semiconductor memory 13 to the external device. Further, the state detection output from the state detection circuit 23 is also possible in the combined operation of the operation mode of this embodiment and the write access or read access of the semiconductor memory 13 by an external device, which is not described in FIGS. 5 and 8 by the signal SD, that is, data write access to the semiconductor memory 13 (in the imaging mode) or data read access from the semiconductor memory 13 (in the reproduction mode) by the internal operation of this embodiment. Is controlled to prohibit access to the semiconductor memory 13 by an external device, and to prohibit access to the semiconductor memory 13 by the internal operation of this embodiment during execution of access to the semiconductor memory 13 by the external device. As a result of the operation, the memory area allocated to the data of one image in the semiconductor memory 13 is duplicated. Image data can be prevented from being stored.

  As described above, in the embodiment shown in FIG. 1, when the semiconductor memory 13 is accessed by an operation started in conjunction with the closing of the recording trigger switch 5, that is, by an imaging operation or a reproduction operation, Access to the semiconductor memory 13 from the device is completely prohibited.

  By the way, the access to the semiconductor memory 13 by this internal operation accesses only the memory area of the image data for one screen in the semiconductor memory 13 per closing of the recording trigger switch 5 as is apparent from the description of the above embodiment. To be executed. Therefore, when the semiconductor memory 13 stores a plurality of pieces of image data, the desired effect can be obtained even if the access prohibition control as described above is limited to the memory area for the data for one image as described above. can get.

  FIG. 9 is a block diagram showing a main part of another embodiment of the imaging apparatus according to the present invention which can realize such control operation. 11A and 11B are switches, 13A and 13B are semiconductor memories, and 15A and 15B are switches. , 23A, 23B, and 34 are state detection circuits, 35 is a selection signal generation circuit, 36 and 37 are AND gates, 38 to 42 are OR circuits, and 43 to 45 are inverters. Parts corresponding to those in FIG. Is attached.

  In FIG. 9, the left half of FIG. 1, that is, the timing generation circuit 2, the semiconductor memory 12, the image sensor 1, the camera signal processing circuit 17, and the encoder 19 are the same and are omitted. Further, two switches 11, semiconductor memory 13, switch 15, and state detection circuit 23 in FIG. 1 are provided, that is, switches 11A and 11B, semiconductor memories 13A and 13B, switches 15A and 15B, and state detection circuits 23A and 23B. Is provided. Although not shown in FIG. 9, the timing generation circuit 7 also generates a clock CL1 and an address signal Ad1 as in the case shown in FIG.

  The feature of this embodiment is that it is arranged independently for each image stored in the semiconductor memory 13 so that access control of image data can be executed independently for each image data. is there. In this embodiment, the number of images to be stored is two. Therefore, as described above, the semiconductor memory 13, the switches 11, 15 and the state detection circuit 23 in FIG. .

  Here, each of the semiconductor memories 13A and 13B for storing data for one image is composed of one (or a plurality) of commercially available semiconductor memory ICs. According to the logic level of the chip enable signal supplied to this terminal, for example, when it is “H”, the enable terminal CE is operated by the clock CL, the address signal Ad, and the read / write switching signal (R / −W). When it is “L”, it does not accept any operation control as described above, and has a function of separating the input / output impedance of the data input / output terminal I / O from the external circuit as a high impedance. In this embodiment, the semiconductor memories 13A and 13B are selected by using such a function.

  Therefore, in this embodiment, the operation control signal MC supplied to the timing generation circuit 7 via the AND gate 6 is also supplied to the selection signal generation circuit 35 constituted by a counter or a shift register. The selection signal generation circuit 35 generates selection signals S1 and S2 for selecting the semiconductor memories 13A and 13B.

  In this embodiment as well, as in the above-described embodiment, the semiconductor memories 13A and 13B are accessed in units of images, so that the selection signals S1 and S2 simultaneously select the semiconductor memories 13A and 13B. The level (here, the selection level is “H”) is not reached. Further, from the external device, the connector 14 includes a preparation status instruction signal CSSa1 that becomes “H” when the semiconductor memory 13A is selected and a preparation status instruction signal CSSa2 that becomes “H” when the semiconductor memory 13B is selected. Is supplied through.

  Here, when the timing generation circuit 7 receives the operation control signal MC supplied from the timing generation circuit 2 in conjunction with the closing of the recording trigger switch 5 shown in FIG. In the signal generation circuit 35, the selection signal S1 becomes "H" and the selection signal S2 becomes "L" by one closing of the recording trigger switch 5, and the selection signal S1 becomes by the next closing of the recording trigger switch 5. Becomes “L”, the selection signal S2 becomes “H”, and when the recording trigger switch 5 is further closed, the selection signals S1 and S2 return to the first level, and thereafter, the selection signals S1 and S2 The change of the level is repeated as described above every time the recording trigger switch 5 is closed.

  The selection signals S1 and S2 are supplied to the AND gates 36 and 37, respectively, and become "L" when the operation of the timing generation circuit 7 starts. In order to maintain the levels of the AND gates 36 and 37 during the operation. The operation end signal ME is inverted in level by the inverter 43 and supplied to the AND gates 36 and 37. The output signals of the AND gates 36 and 37 are supplied to the chip enable terminals CE of the semiconductor memories 13A and 13B as chip enable signals via the OR circuits 38 and 39, respectively. As a result, the semiconductor memories 13A and 13B are alternately selected every time the timing generation circuit 7 executes an operation by closing the recording trigger switch 5.

  The selection signals S1 and S2 are inverted in level by the inverters 44 and 45, respectively, and then supplied to the state detection circuits 23A and 23B via the OR circuits 41 and 42, respectively. The operation end signal ME is also supplied to the state detection circuits 23A and 23B via these OR circuits 41 and 42. As a result, the output signal of the OR circuit 41 is “L” only during the period when the semiconductor memory 13A is accessed by the timing generation circuit 7 and “H” during the other periods. Similarly, the output signal of the OR circuit 42 is “L” only during the period when the semiconductor memory 13B is accessed by the timing generation circuit 7, and “H” during the other periods. The output signals of these OR circuits 41 and 42 are substituted for the operation end signal ME in the state detection circuit 23 in FIG. 1 in the state detection circuits 23A and 23B.

  The status detection circuit 23A is supplied with a preparation status instruction signal CSSa1 from an external device, and the state detection circuit 23B is supplied with a preparation status instruction signal CSSa2, and these preparation status instruction signals CSSa1 and CSSa2 are supplied with the status detection in FIG. This is the same as the preparation status instruction signal CSSa supplied to the circuit 23. Also, the transfer operation end signal CSSb from the external device is supplied to both the state detection circuits 23A and 23B.

  Here, the external device sets the preparation status instruction signal CSSa1 to “H” when accessing the semiconductor memory 13A, and sets the preparation status instruction signal CSSa2 to “H” when accessing the semiconductor memory 13B. Do not set it to H ”. Further, even when the external device accesses either one of the semiconductor memories 13A and 13B, the external device generates the pulsed transfer operation end signal CSSb as shown in FIG. 5 every time the access operation of the selected semiconductor memory is completed. .

  With the above configuration, the state detection circuit 23A performs the same operation as the state detection circuit 23 shown in FIG. 4, and when the semiconductor memory 13A is accessed by the timing generation circuit 7, it does not depend on the state of the preparation status instruction signal CSSa1. When the state detection signal SDa is held at “L” and this access is not made, the state detection signal SDa can be switched to “H” by setting the preparation state instruction signal CSSa1 to “H”.

  When the state detection signal SDa is “H”, the switches 11A and 15A are switched so that the respective terminals of the semiconductor memory 13A can be connected to an external device, and are connected to the chip enable terminal CE of the semiconductor memory 13A via the OR circuit 38. Supplied and make it operational. Further, it notifies the external device via the OR circuit 40 that the semiconductor memory 13 has become accessible. Similarly, access to the semiconductor memory 13B is switched by the operation of the state detection circuit 23B.

  The state detection signals SDa and SDb are also supplied to the state detection circuit 34. In the embodiment shown in FIG. 1, the state detection signal SD output from the state detection circuit 23 is supplied to the AND gate 6 via the inverter 9, and this state detection circuit 23 is controlled by the timing generation circuit 2. Although used for control for waiting for the output of the signal MC, in this embodiment shown in FIG. 9, such an operation is performed using the state detection circuit 34.

  That is, the state detection circuit 34 can detect whether the semiconductor memory to be selected by the selection signal generation circuit 35 in the next operation is the semiconductor memory 13A or the semiconductor memory 13B from the levels of the selection signals S1 and S2. The selection state of the semiconductor memories 13A and 13B by the external device is known from the logic level of the state detection signal SDa or SDb, and when the semiconductor memory 13A or 13B to be selected is not accessed by the external device, the operation starts immediately. When the memory is being accessed, it waits, or the semiconductor memory 13A, 13B that is not accessed is selected to start the operation.

  FIG. 10 is a block diagram showing a specific example of the state detection circuit 34 in FIG. 9, wherein 34a and 34b are AND gates, 34c is a NOR circuit, and parts corresponding to those in FIG. .

  In the figure, when the selection signal S1 is “H”, the selection signal generation circuit 35 switches the selection signal S2 to “H” and the selection signal S1 to “L” when the next operation control signal MC is input. When the selection signal S2 is “H”, the selection signal S1 is switched to “H” and the selection signal S2 is switched to “L” when the next operation control signal MC is input.

  In the state detection circuit 34, the selection signal S2 and the state detection signal SDa are supplied to the AND gate 34a, and the selection signal S1 and the signal SDb are supplied to the AND gate 34b. When the semiconductor memory 13A or 13B matches the semiconductor memory 13A or 13B that is scheduled to be accessed by the next operation of the timing generation circuit 7, an "H" signal is output from one of the AND gates 34a and 34b. Is output. At this time, since the output signal of the NOR circuit 34c becomes “L”, the AND gate 6 prevents the operation control signal MC from passing, and when the state detection signal SDa or SDb becomes “L”, the above-described operation is performed. During the period until the coincidence state is canceled, the standby operation state is established.

  In the embodiment shown in FIG. 9, a total of two images are stored one by one in each of the two systems of semiconductor memories 13A and 13B. However, the semiconductor memory 13 is added and the switches 11, 15 are added accordingly. In addition, by adding a circuit configuration including the state detection circuit 23 and the OR circuit 38, two or more images can be stored. At this time, the number of the state detection circuits 34 may be one, but FIG. 11 shows a specific example of the state detection circuit 34 in the case where N semiconductor memories 13 are used. However, in the figure, 341, 342, 343, 344,..., 34N are AND gates corresponding to the AND gates 34a and 34b in FIG. 10, and the portions corresponding to FIG. .

  In FIG. 11, a selection signal generation circuit 35 in which the number of stages of counters or shift registers is set corresponding to N semiconductor memories 13 generates N selection signals S1, S2, S3, S4,. These are supplied to AND gates 341, 342, 343, 344,..., 34N of the state detection circuit 34, respectively. Although not shown, N circuits corresponding to the state detection circuits 23A and 23A in FIG. 9 are provided, and the state detection signals SD1, SD2, SD3, SD4,. , 342, 343, 344,..., 34N. With this configuration, when any system of the semiconductor memory 13 to be accessed is accessed by an external device by the next operation of the timing generation circuit 7, the execution of the operation of the timing generation circuit 7 is put on standby. be able to.

  10 and 11, the selection signal generation circuit 35 is supplied with an initial reset signal INS upon power-on, and by resetting the counter and the like, a set of selection signals in an initial state (generally, The first selection signal S1 is "H").

  Further, a digital addition circuit for adding 1 to the current count number and a function for loading the addition result into this counter are added to the counter of the selection signal generation circuit 35 in FIG. 10 or FIG. The AND gate 6 prevents the operation control signal MC from being configured so that the load is executed at the timing when the output signal is “L” and the operation control signal MC is inverted from “L” to “H”. When this occurs, the condition that the selection signal generation circuit 35 automatically counts up and the output signal of the NOR circuit 34c becomes "L" is canceled, and the selection signal is generated by the operation control signal MC passing through the AND gate 6 by this cancellation. By counting up the generation circuit 35 again, a semiconductor memory system that is not accessed by an external device is selected and writing is executed. It is possible to become so that.

  As described above, even if the semiconductor memory 13 is divided into a plurality of memory blocks that can be accessed independently, the same effect as that of the embodiment shown in FIG. 1 can be obtained. When any of the blocks is accessed by an external device, the memory block that is not automatically accessed can be selected, and the semiconductor memory 13 can be accessed by an imaging operation or a reproduction operation. Therefore, when the semiconductor memory 13 having a plurality of image recording areas is employed, even when the access to the semiconductor memory 13 by the external device is being performed, recording excluding the recording area currently accessed by the external device is excluded. A plurality of images can be taken and recorded in the area.

  In the embodiment shown in FIGS. 1 and 9, the recording trigger switch 5 for starting the operation is arranged in the apparatus. However, the present invention is not limited to this, and for example, infrared rays are used. The operation can be started by a remote controller, or an operation start can be instructed from an external device connected to the connector 14.

  In the embodiment shown in FIGS. 1 and 9, a memory means such as a magnetic disk may be employed instead of the semiconductor memory 13, and the switching control of these memory accesses is performed in the same manner as described above. It can be configured to run.

  Furthermore, in the embodiment shown in FIGS. 1 and 9, the image data is compressed or expanded, but such a function is not essential in the present invention. Although the semiconductor memory 12 is used as a buffer memory, the semiconductor memory 12 is not indispensable particularly in an embodiment that does not have an image data compression / decompression function, and captured image information is recorded in the semiconductor memory 13 in real time. You may comprise.

  Furthermore, when the above-described flash memory elements that generate a ready / busy signal are used as the semiconductor memories 13, 13A, and 13B in FIGS. 1 and 9, the ready / busy signal generated by them and the state detection signal are generated. A signal obtained by ORing each of SD, SDa, and SDb may be transmitted to an external device via the connector 14.

  Further, in FIG. 1, a switch corresponding to the switch 11 is further provided between the switch 10 and the semiconductor memory 12, and the data input terminal I and the data output terminal O of the semiconductor memory 12 are respectively switched to FIG. A switch that can be selected and connected to the connection relationship shown and the connection relationship with an external device via the connector 14 is provided, and this switch is used as a signal indicating the operation state of the timing generation circuit 2 as an operation end signal ME. Instead, or by being configured to be switched by the output signal of the state detection circuit 23 used in addition to the operation end signal ME, image data not compressed from the external device is written into the semiconductor memory 12, and this is converted into an image. Compressed by the data compression processing circuit 21 and written to the semiconductor memory 13, or compressed by an external device The image data is written in the semiconductor memory 13, restored by the image data decompression processing circuit 125, once taken into the semiconductor memory 12, and then the restored image information from the semiconductor memory 12 is read out to an external device. realizable. At this time, the access of the semiconductor memory 12 started by the user operating the recording trigger switch 5 at an arbitrary timing and the access of the individual semiconductor memory 12 by an external device may also overlap. Therefore, data of a plurality of images are not mixed in one image data.

  12A and 12B are an external view and an example of use of an embodiment of an imaging apparatus according to the present invention. Here, 46 is an image pickup apparatus according to the present invention, 47 is a light-receiving lens for image pickup, 48 is a viewfinder similar to a conventional film camera, and 49 is a lens hood.

  FIG. 12A shows the appearance of the imaging apparatus, which is provided with an imaging light-receiving lens 47, a finder 48, and a lens hood 49 similar to those of a conventional film camera. Also, like the conventional film camera, the recording trigger switch 5 is provided on the left side of the upper surface in the drawing, and the connector 14 is attached to the right side surface of the drawing. Here, when the semiconductor memory 13 that is detachably incorporated in the apparatus is used, the illustrated thickness D can be made extremely thin.

  FIGS. 12B to 12E show an example in which an external device is a personal computer PC and the image pickup device 46 is attached to the external computer PC, and FIG. 12B shows the connector 14 of the image pickup device 46 being personal. The case where it connects directly to the socket inside computer PC is shown.

  FIG. 12C shows an example in which the connector 14 of the imaging device 46 is connected to the personal computer PC via the socket 50 and the cable 51.

  In FIG. 12D, the imaging device 46 is mounted on an adapter 52 having a built-in power supply circuit such as a known AC / DC converter that generates a DC voltage from an AC power supply, and the adapter 52 is connected to the personal computer PC. . In this case, for example, operating power is supplied from the operating power input terminal provided in the connector 14 to the imaging device 46, and input / output signals of the connector 14 are installed in the adapter 52, such as an electric circuit, such as an electric wiring or a signal buffer. A personal computer PC is connected via a circuit or the like. The adapter 52 may include a known DC power source such as a dry battery. In this case, the adapter 52 is configured exclusively for supplying operating power and used together with the imaging device 46 when used outdoors. You can do anything.

  FIG. 12 (e) shows an example in which the adapter 53 having the same mechanism as that of a known tabletop illuminator stand is attached to the personal computer PC. In this case, for example, by setting the imaging device 46 inside the circle drawn by the fluorescent tubes of the round fluorescent lamps 54a and 54b, the subject illuminated by the fluorescent lamps 54a and 54b is imaged, and the image information is stored in a personal computer. It can be configured to transmit to a PC.

  Here, the terminal position of the connector 14 shown in FIG. 12A is defined so as to be based on the device exterior surface on the side opposite to the direction of the incident light of the imaging light-receiving lens 47, so that FIG. In operations (b) to (e), etc., when the reference surface is attached to an adapter or the like, the incident light direction is opened without being blocked, so it is attached to a personal computer PC or an adapter or the like. Images can be taken in a state.

It is a block diagram which shows one Embodiment of the imaging device by this invention. It is a schematic diagram which shows the FIFO type memory used for the conventional imaging device. FIG. 2 is a timing diagram showing an operation of the semiconductor memory in FIG. 1. FIG. 2 is a block diagram illustrating a specific example of a state detection circuit in FIG. 1. FIG. 5 is a timing chart showing a signal transmission / reception function with the external device of the embodiment shown in FIG. 1 and an operation of the state detection circuit shown in FIG. 4. It is a block diagram which shows the other specific example of the state detection circuit in FIG. FIG. 7 is a timing diagram illustrating an operation of the state detection circuit illustrated in FIG. 6. FIG. 2 is a timing chart showing an image reproduction operation of the embodiment shown in FIG. 1. It is a block diagram which shows the principal part of other embodiment of the imaging device by this invention. FIG. 10 is a block diagram illustrating a specific example of the state detection circuit in FIG. 9. It is a block diagram which shows the other specific example of the state detection circuit in FIG. It is a figure which shows the external appearance of one Embodiment of the imaging device by this invention, and its usage example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image pick-up element 2 Timing generation circuit 4 Power switch 5 Recording trigger switch 7 Timing generation circuit 10, 11, 11A, 11B Switch 12, 13, 13A, 13B Semiconductor memory 14 Connector 15, 15A, 15B, 16 switch 17 Camera signal processing circuit Reference Signs List 18 switch 19 encoder 20 output terminal 21 image data compression processing circuit 22 image data decompression processing circuit 23, 23A, 23B state detection circuit 24 fitting detection switch 25 external device 34 state detection circuit 35 selection signal generation circuit

Claims (4)

An imaging device to which an external device can be connected,
A recording switch for instructing recording;
An imaging means for generating an image signal from the optical image;
Memory means for storing an image signal generated by the imaging means;
Connection means for enabling connection of the external device;
Control means for controlling writing to the memory means;
Have
The control means includes a state detection means for detecting a write preparation state of the image signal from the external device to the memory means, and when the write preparation state is detected by the state detection means, the operation of the recording switch Control to prohibit writing of a new image signal to the memory means linked to
An imaging apparatus characterized by the above. An imaging device to which an external device can be connected,
A recording switch for instructing recording;
An imaging means for generating an image signal from the optical image;
Memory means for storing an image signal generated by the imaging means in response to an operation of the recording switch;
Connection means for enabling connection of the external device;
Control means for controlling writing to the memory means;
Have
The control means includes a state detection means for detecting a write preparation state of the image signal from the external device to the memory means, and when the write preparation state is detected by the state detection means, the operation of the recording switch Control to ignore
An imaging apparatus characterized by the above. An imaging device to which an external device can be connected,
A recording switch for instructing recording;
An imaging means for generating an image signal from the optical image;
Memory means for storing an image signal generated by the imaging means;
Connection means for enabling connection of the external device;
Control means for controlling writing to the memory means;
Have
The control means includes a state detection means for detecting a write preparation state of the image signal from the external device to the memory means, and when the write preparation state is detected by the state detection means, the operation of the recording switch Control to prohibit imaging operations started in conjunction with
An imaging apparatus characterized by the above. An imaging device to which an external device can be connected,
A recording switch for instructing recording;
An imaging means for generating an image signal from the optical image;
Memory means for storing an image signal generated by the imaging means in response to an operation of the recording switch;
Connection means for enabling connection of the external device;
Control means for controlling writing to the memory means;
Have
The control means includes a state detection means for detecting a write preparation state of the image signal from the external device to the memory means, and when the write preparation state is detected by the state detection means, the operation of the recording switch Control to prohibit operation by
An imaging apparatus characterized by the above.

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