JPH10322323A - Serial data transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust phase differences between received serial data in a data reception unit by selecting the selection signal of the largest delay from the selection signals whose number is equal to that of data transmission units and delaying other received serial data so that it is synchronized with the selection signal. SOLUTION: Transmission data of the optionally preset number of times are transmitted from the three data transmission units. A data selection part 15 adds number of times parity check results similar to the number of transmission data. The data selection part 15 sends the selection signal selecting a data parity check part 16 having the most probability to a selector 17 and a delay quantity measuring part 19. The delay quantity measuring part 19 selects the selection signal of the largest delay from the selection signals. A delay quantity correction part 20 adds correction delay quantity to selection data from the selector 17. Thus, received serial data which is phase-synchronized with selection data having the largest delay quantity can be fetched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transmission system, and more particularly to a serial transmission system for receiving serial data transmitted from a plurality of data transmission units and obtaining serial data whose phases are all synchronized.

[0002]

2. Description of the Related Art Conventionally, a serial transmission system has a one-to-one transmission / reception relationship, and performs serial communication in synchronization with a clock and a frame synchronization signal on a transmission side.
The receiving side has verified the normality of the received data by a parity check or the like.

[0003]

In the conventional serial data transmission system, a plurality of data transmission units transmit serial data with parity bits in a reference clock and a frame synchronization signal transmitted from a clock generation unit, and a data reception unit transmits the data. Receives serial data transmitted from a plurality of data transmission units using the reference clock and the frame synchronization signal transmitted from the clock generation unit. At this time, a parity error may occur in the serial data from the data transmission unit. The reason is that when transmission / reception is performed at a data rate at which a transmission delay due to variations in each driver IC and each receiver IC element cannot be ignored, each driver IC
The reason is that the received data has a phase difference from the reference clock and the frame synchronization signal due to the transmission delay difference between the receiver ICs, so that normal data cannot be received.

In the conventional serial data transmission system, a phase difference occurs between serial data transmitted from a plurality of data transmission units. The reason is that the operation delay of the transmission unit of each data transmission unit and
This is because a phase difference occurs between the received serial data due to a delay difference due to a difference in transmission distance from each data transmission unit to the reception unit.

It is an object of the present invention to reduce a transmission delay difference between each driver IC and a receiver IC, an operation delay difference between a transmission unit of each data transmission unit, a delay difference due to a difference in transmission distance from each data transmission unit to a reception unit, and the like. Without consideration
It is an object of the present invention to provide a serial data transmission system in which a data receiving unit can match a phase difference between normal received serial data and each received serial data.

[0006]

According to the serial data transmission system of the present invention, the receiving section of the data receiving unit has the same number of check and select sections as the number of the data transmission units. Means for sampling received serial data with several types of parity check clocks shifted in phase by a half clock of the received clock generated from the frame synchronization signal, and performing a parity check on each sampled data; Based on the transmission data of an arbitrarily set number of times, the results of the parity check performed the same number of times as the number of transmission data are totaled and the parity check N.P. G. FIG. Means for selecting the received serial data sampled by the parity check clock having a small number of bits, means for selecting the received serial data by this select signal, and a delay having the largest delay among the same number of the select signals as the data transmission unit. Means for selecting one and delaying other received serial data so as to synchronize with the select signal.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of this embodiment.
A reference clock and a frame synchronization signal are generated in the clock generation unit 1, transmitted to the data transmission unit 3 and the data reception unit 4 by the driver IC 6, and received by the receiver IC 7.

A plurality of (three in the figure) data transmitting units 3 convert transmission data into serial signals by a reference clock and a frame synchronizing signal in a transmitting unit 5 and
The serial data is transmitted to the data receiving unit 2 from C6.

The data receiving unit 2 receives the serial data from each data transmitting unit 3 and
, And is input to the receiving unit 4 to obtain phase-synchronized received serial data.

Next, the operation of this embodiment will be described with reference to the detailed diagram of the receiving section 4 of the data receiving unit 2 of FIG. 2 and the time chart of FIG.

In the transmitting section 5 of each of the three data transmitting units 3, one parity bit P is added to the eight bits D0 to D7 of the transmission data, the reference clock is used as the transmission clock (a in FIG. 3), and the transmission frame synchronization signal is used. The case where serial data (FIG. 3C) synchronized with (FIG. 3B) is output from the driver IC 6 and the data receiving unit 2 obtains phase-synchronized received serial data will be described.

The serial data output from each data transmission unit 3 is received by the receiver IC 7 of the data reception unit 2 and input to the reception unit 4. At this time, due to the transmission delay difference between each driver IC 6 and each receiver IC 7, the received data (f in FIG. 3) is in the same position as the received clock (d in FIG. 3) using the reference clock and the received frame synchronization signal (e in FIG. 3). A phase difference occurs.

A phase difference also occurs between received serial data due to a delay difference due to a transmission distance from each data transmission unit 3 to the reception unit 2 and an operation delay difference of the transmission unit 5 of the data transmission unit 3.

The receiving section 4 of the data receiving unit 2 has the same number of three check and select sections 13 as the data transmitting unit 3 as shown in FIG.

One check and select unit 13 will be described in detail.

The parity check timing generator 14 generates a plurality of parity check clocks from the received clock and the received frame synchronization signal. These parity check clocks are four types,... (G, i, k, and m in FIG. 3), each having a phase shifted by a half clock of the reception clock.

These four types of parity check clocks are sent to four data parity check units 16, respectively. Each of the data parity check units 16 is configured to receive 8 bits of data and 1 parity bit of the received serial data sampled by each parity check clock.
The parity check is performed on the bits, and the resulting parity errors,,, (((h, j,
l, n) to the data select generator 15.

The three data transmission units 3 transmit transmission data of an arbitrarily set number of times in advance, and the data select generation unit 15 counts the parity check results the same number of times as the number of transmission data to obtain the most probable (parity) A select signal (P in FIG. 3) for selecting the data parity check unit 16 with the least check NG is sent to the selector 17 and the delay amount measurement unit 19.

The select 7 sends the select data (O in FIG. 3) of the data parity check unit 16 selected by the select signal from the data select generation unit 15 to the delay amount correction unit 20.

The delay amount measuring section 19 selects a select signal having the longest delay from the select signals from the data select generating section 15 of each check & select section 13 and sends it to the delay amount correcting section 20.

In the delay amount correction section 20, the correction delay amount is added to the select data, and the reception serial data phase-synchronized with the select data having the largest delay amount is started to be taken into the unit.

[0023]

According to the serial data transmission system of the present invention, the most reliable received data can be obtained without considering the delay factor of each unit in the data receiving unit. The received data can be phase-synchronized and taken in the unit.

The reason is that arbitrarily set line transmission data is transmitted from the data transmission unit, and the reception data delayed in the data reception unit is sampled by a parity check clock shifted by a half clock of the reception clock. The respective parity check results are totaled for the number of transmissions of the transmission data, and the parity check N.N. This is because the received data sampled by the parity check clock having the least G can be obtained, and the phase can be synchronized with the received serial data having the largest delay amount.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a detailed diagram of a receiving unit according to an embodiment of the present invention.

FIG. 3 is a timing chart showing one embodiment of the present invention.

[Description of Signs] 1 clock generation unit 2 data reception unit 3 data transmission unit 4 reception unit 5 transmission unit 6 driver IC 7 receiver IC 8 reference clock 9 frame synchronization signal 10 transmission data 11 reception serial data 12 serial data 13 check & select Unit 14 parity check timing generation unit 15 data select unit 16 data parity check unit 17 selector 18 parity check clock 19 delay amount measurement unit 20 delay amount correction unit 21 select data 22 select signal

Claims (3)

[Claims] 1. A receiving section of a data receiving unit has the same number of check and select sections as the number of data transmitting units, and each of the check and select sections has a phase of a half clock of a reception clock generated by a reception clock and a frame synchronization signal. Means for sampling the received serial data by using several kinds of parity check clocks shifted from each other, and performing a parity check of each sampled data, and transmitting the data based on a predetermined number of times of transmission data transmitted from the data transmission unit. The results of the parity check performed the same number of times as the number of data are totaled and the parity check N.N. G. FIG. Means for selecting the received serial data sampled by the parity check clock having a small number of bits, means for selecting the received serial data by this select signal, and a delay with the longest delay among the same number of the select signals as the data transmission unit. Means for selecting one of the serial data and delaying another received serial data so as to synchronize with the select signal. 2. A plurality of data transmission units transmit serial data with parity bits according to a reference clock and a frame synchronization signal transmitted from a clock generation unit, and a reference clock transmitted from the clock generation unit in a data reception unit. And a serial transmission system for receiving serial data transmitted from the plurality of data transmission units using a frame synchronization signal, wherein the data reception unit prevents a parity error of the serial data received by the data reception unit. And a means for eliminating a phase difference between a plurality of serial data received by the data receiving unit. 3. A parity check timing generator for generating, from a reference clock and a frame synchronization signal received from the clock generation unit, a plurality of types of parity check clocks having phases shifted by half a clock of a received clock, The received serial data is sampled by the parity check clock, and the parity check of each sampled data is performed by a plurality of data parity check units, based on transmission data of a predetermined number of times transmitted from the data transmission unit, The results of the parity check performed the same number of times as the number of transmission data are totaled, and the parity check N.N. G. FIG. A data select generation unit that generates a select signal for selecting a data parity check unit with a small number of bits; and a selector that selects serial data sampled by a parity check clock in the data parity check unit based on the select signal, and outputs the serial data as select data. And a check & select unit having the same number as the number of the data transmission units, and a delay amount measurement unit for selecting a select signal having the largest delay from the same number of the select signals as the number of the data transmission units. 3. The serial data transmission system according to claim 2, further comprising: a delay measuring unit that adds a correction delay amount to a plurality of the select data in accordance with the selected select signal and performs phase synchronization.