JPH08154091A - Communication interface circuit - Google Patents

Abstract

PURPOSE: To reduce an error of a delay control without proportionally increasing a circuit scale even if an adjusting delay time becomes long when a delay time of an addition circuit (driver/receiver, etc.) in a communication control circuit to be used in an ISDN basic user/network interface, etc. is compensated. CONSTITUTION: A clock signal is extracted from a reception signal by a clock extraction part 3 and the signal phase information on the extracted clock is delivered to a phase comparison part 4. When the phase information on a transmitted extracted clock signal is matched with a preliminarily set reference phase value in the phase comparison part 4, a phase matching detection signal is outputted to a clock generation part 5 for transmission. By initializing the internal state in the clock generation part 5 for transmission when the phase matching detection signal is transmitted, the clock delaying the extracted clock signal by the part corresponding to the preliminarily set reference phase value is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control circuit for compensating for a delay time due to an additional circuit (driver, receiver, etc.) when transmitting and receiving data via a communication line, and more particularly to I.
The present invention relates to a communication interface circuit at an SDN basic user / network interface reference point S / T.

[0002]

2. Description of the Related Art Generally, data at a reference point S / T of an ISDN basic user / network interface includes data (reception side data) flowing from a network terminating device (NT) toward an ISDN terminal device (TE) and an ISDN terminal device. Data (sending side data) flowing from (TE) to network terminator (NT)
The timing is different between.

FIG. 4 is a frame structure diagram at the ISDN basic user / network interface reference point S / T.

In the figure, one frame is 48 bits (2
50 μs), and a frame transmitted in the direction from NT to TE and a frame transmitted in the direction from TE to NT have a 2-bit offset defined. The deviation Δ is in the range of −0.4 μs to +0.8 μs.

Therefore, NT and TE are connected to the line via a driver circuit and a receiver circuit, and are designed so that the total sum of the internal delay of the transmission circuit and the internal delay of the driver circuit and the receiver circuit satisfies the above criteria. Must.

As a method for satisfying the delay time defined by the standard, the phase of the clock extracted from the received signal is shifted stepwise by using a shift circuit and is shifted so as to compensate the delay of the driver circuit and the receiver circuit. A technique for selecting and using a clock signal from a circuit is disclosed in JP-A-2-1710.
No. 50 publication.

Next, the configuration of the communication interface circuit disclosed in the above publication shown in FIG. 5 will be described.

In FIG. 5, the signal received by the receiver circuit 41 is a frame decomposing section 45 and a clock extracting section 42.
And data is added to the driver circuit 48 from the frame assembling unit 46 through the flip-flop 47.
In the ISDN interface circuit at the interface reference point S / T that transmits data based on the clock signal extracted from the clock extraction unit 42, a phase shift circuit 43 that gradually shifts the phase of the clock signal extracted by the clock extraction unit 42. And a selector 44 for selecting the clock signal phase-shifted by the phase shift circuit 43 so as to compensate the delay time of the receiver circuit 41 and the driver circuit 48 and adding it to the driver circuit 48. And driver circuit 48
The delay time is compensated for and the deviation of the transmission / reception timing is kept within the standard.

[0009]

In the prior art of this type, the delay time to be adjusted is associated with the shift bit length, so that the longer the delay time to be adjusted, the more the number of stages of the phase shift circuit 43 and the desired value. The circuit scale of the selector 44 that selects the clock signal increases proportionally.
Further, if the shift clock of the phase shift circuit 43 is not generated in consideration of the cycle and phase of the clock output from the clock extraction unit 42, the error in delay control becomes large.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to solve these problems and provide a communication interface circuit having a small delay control error without proportionally increasing the circuit scale even if the delay time for adjustment becomes long. It is what

[0011]

A communication interface circuit according to a first aspect of the present invention includes a clock extraction unit for extracting a clock signal from a received signal, phase information of the extracted clock signal, and a preset reference phase value. A phase comparison unit that compares the transmission signal, a transmission clock generation unit that generates a clock signal that determines the timing of the transmission signal, and a synchronization that outputs data in synchronization with the transmission clock signal output from the transmission clock generation unit. A transmission clock that is delayed by a certain amount with respect to the clock signal extracted by the clock extraction unit by initializing the internal state of the transmission clock generation unit according to the signal from the phase comparison unit. A signal is generated and data is transmitted in synchronization with the transmission clock signal.

According to a second aspect of the present invention, there is provided a communication interface circuit for compensating for a delay time of a receiver circuit and a driver circuit for transmitting / receiving data via a communication line and adjusting a deviation of transmission / reception timing, from a received signal. A clock extraction unit that extracts a clock signal, a phase comparison unit that compares the phase information of the clock signal extracted by the clock extraction unit with a preset reference phase value, and a clock signal that determines the timing of the transmission signal. A transmission clock generation unit for generating and a synchronous transmission unit for outputting data in synchronization with the transmission clock signal output from the transmission clock generation unit, and the transmission clock according to the signal from the phase comparison unit. The clock extracted by the clock extraction unit by initializing the internal state of the generation unit. It is to send the data to generate a fixed delay transmit clock signal, in synchronism with the transmission clock signal to the items.

The transmission clock generation unit of the communication interface circuit according to the third aspect is a counter circuit.

According to a fourth aspect of the present invention, a clock extraction section of a communication interface circuit operates the counter circuit of the transmission clock generation section and the counter circuit of the clock extraction section with the same clock signal, and sends them according to the signal from the phase comparison section. When the internal state of the trust clock generation unit is initialized, the initialization is performed in synchronization with the clock signal.

[0015]

According to the present invention, the clock extraction unit extracts the clock signal from the received signal, and the signal phase information of the extracted clock is sent to the phase comparison unit. The phase comparison section outputs a phase coincidence detection signal to the transmission clock generation section when the phase information of the transmitted extracted clock signal matches the preset reference phase value. The transmission clock generation unit initializes the internal state when the phase matching detection signal is sent, thereby generating a clock delayed by the reference phase value set in advance with respect to the extracted clock signal.

According to another aspect of the present invention, the clock extraction unit extracts a clock signal from the received signal that has passed through the receiver circuit that transmits and receives data via the communication line, and the signal phase information of the extracted clock is phased. Send to the comparison section. The phase comparison section outputs a phase coincidence detection signal to the transmission clock generation section when the phase information of the transmitted extracted clock signal matches the preset reference phase value. The transmission clock generation unit generates a transmission clock delayed by the preset reference phase value with respect to the extracted clock signal by initializing the internal state when the phase matching detection signal is sent. The data is transmitted to the driver circuit in synchronization with the transmission clock signal.

According to the present invention, the transmission clock generator is a counter circuit, so that it is not necessary to prepare a bit length proportional to the bit length to be adjusted.

According to another aspect of the present invention, the clock extraction unit operates the counter circuit of the transmission clock generation unit and the counter circuit of the clock extraction unit with the same clock signal, and the transmission clock generation unit according to the signal from the phase comparison unit. When the internal state of is initialized, the initialization is performed in synchronization with the clock signal to generate a clock delayed by the reference phase value set in advance with respect to the extracted clock signal.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A communication interface circuit according to an embodiment of the present invention will be described below.

FIG. 1 is a circuit configuration diagram of a communication interface circuit according to a first embodiment of the present invention, in which the communication interface circuit is connected to a line of an ISDN basic user / network interface.

In FIG. 1, 1 is a receiver circuit, which is an IS.
A signal from the DN basic user / network interface line is received and output as a received signal to the frame decomposing unit 2 and the clock extracting unit 3 of this embodiment. The received signal is sent to the frame decomposing unit 2 and decomposed into B1, B2, and D channel data. Reference numeral 3 denotes a clock extraction unit that extracts a clock signal from the received signal output from the receiver circuit 1. Reference numeral 4 denotes a phase comparison unit that compares the phase information of the extracted clock signal output from the clock extraction unit 3 with a preset reference phase value. Reference numeral 5 is a transmission clock generation unit, which is a phase comparison unit 4
The internal state is initialized according to the result of the comparison, and a transmission clock signal having a certain delay with respect to the extracted clock signal is generated. Reference numeral 7 is a flip-flop circuit, which stores the data assembled as a frame by the frame assembling unit 6,
A synchronous transmission unit for transmitting to the driver circuit 8 in synchronization with the clock generated by the transmission clock generation unit 5 is configured. The transmission data is output to the line through the driver circuit 8.

FIG. 2 shows a DPLL as a clock extraction unit used in the communication interface circuit of the first embodiment of the present invention.
It is a circuit configuration block diagram using (digital phase locked loop).

In FIG. 2, reference numeral 21 is an edge detecting section for detecting a change point of a received signal, 22 is a counter circuit for generating a clock (extracted clock signal) having the same cycle as the received signal, and 23 is an edge detecting section 21 for detecting. Latch circuit that latches the output value of the counter circuit 22 at the timing of the generated edge, 24 is a digital loop filter, 25 is a phase control unit that performs phase control based on the output data of the digital loop filter 24, and 26 is a phase control unit 25. Is a counter value setting unit that sets a value in the counter circuit 22 when a phase control request is issued from the.

Here, assuming that the DPLL is operated with a clock that is 64 times the clock of the received signal, the counter circuit 22 can be configured by a 6-bit synchronous counter. Further, the transmission clock generation unit 5 is also configured by the same 6-bit synchronous counter as the counter circuit 22.

FIG. 3 is a timing chart of signals in the communication interface circuit according to the embodiment of the present invention.

In FIG. 3, a is a received signal output from the receiver circuit 1, b is an operation clock of the clock extraction unit 3 and the transmission clock generation unit 5, c is an output signal of the edge detection unit 21, and d is clock extraction. The extracted clock signal output from the unit 3, e is the value of the 6-bit counter of the counter circuit 22, f is the phase matching signal output from the phase comparison unit 4,
g is the value of the 6-bit counter in the transmission clock generation unit 5, and h is the transmission clock signal output from the transmission clock generation unit 5.

Next, the operation of the communication interface circuit of this embodiment will be described.

As described above, the format of the transfer data of the ISDN basic user / network interface is such that the frame is as shown in FIG.

First, the data is transmitted from TE in the NT direction (transmission side)
The frame to be transmitted must be delayed by 2 bits with respect to the frame transmitted (reception side) from the NT to the TE direction. Here, the communication interface circuit of the present embodiment is TE
It is supposed to be used on the side. When the delay time by the driver circuit 8 is 0.5 bit, the frame assembling unit 6
In the following, a case will be described in which the transmission data is output with a 1-bit delay with respect to the reception frame, and the remaining 0.5-bit delay is generated in the transmission clock generation unit 5.

The clock extraction unit 3 extracts a clock from the received signal a to obtain an extracted clock signal d. In the state where the frame synchronization is established, the signal timing is as shown in FIG. Here, the bit data in the received frame is completely synchronized with the extracted clock signal d. The extracted clock signal d output from the clock extraction unit 3 uses the most significant bit value of the counter circuit 22 of the DPLL. In this case, the value e of the 6-bit counter of the counter circuit 22 can be used as the phase information of the extracted clock signal d.

Generating a delay of 0.5 bits in the transmission clock generation unit 5 means that a signal obtained by delaying the extracted clock signal output from the clock extraction unit 3 by 0.5 bits is used in the transmission clock generation unit. 5, the transmission data may be output to the driver circuit 8 in synchronization with the transmission clock.

This 0.5-bit delay amount corresponds to 32 clocks in the operation clock of the DPLL, and the phase comparison unit 4
Is set to (32-1) = 31 as the reference phase value.
When the phase information output from the counter circuit 22 coincides with 31 clocks of the reference phase value, the phase coincidence signal f becomes active, and the synchronous counter of the transmission clock generator 5 is initialized in synchronization with the next rising edge of the operation clock b. (= 0)
To do. Here, when the most significant bit of the 6-bit synchronous counter in the transmission clock generator 5 is output, a waveform like the transmission clock signal h is obtained. As is clear from the waveform of the transmission clock signal h, the transmission clock signal h is a signal obtained by delaying the extracted clock signal d by 0.5 cycle, so that the flip-flop circuit 7 synchronizes with the transmission clock signal h. By outputting the transmission data, 0.
A delay time of 5 bits can be generated. The delayed transmission clock signal h is applied to the flip-flop circuit 7
By using the operation clock of, the transmission data generated by the frame assembling unit 6 can be delayed with respect to the extracted clock signal d by a certain time and then output.

In particular, the delay time due to the driver circuit 1 and the receiver circuit 8 can be compensated by setting the preset reference phase value to an appropriate value.

In this embodiment, the extracted clock signal d
Although the transmission clock signal h is generated as a clock signal whose phase is delayed, the clock signal whose phase is advanced with respect to the extracted clock signal d can be generated. Delaying the phase of the ΔT cycle with respect to the cycle T of the extracted clock signal d is the same as advancing the (T−ΔT) phase.

As described above, the communication interface circuit according to the present embodiment compensates the delay time of the receiver circuit 1 and the driver circuit 8 for transmitting / receiving data via the communication line and adjusts the deviation of the transmission / reception timing. , A clock extraction unit 3 for extracting a clock signal from the received signal a, and the extracted extracted clock signal d
A phase comparison section 4 for comparing the phase information of the above with a preset reference phase value, a transmission clock generation section 5 for generating a transmission clock signal h for determining the timing of the transmission signal,
A synchronous transmission unit including a flip-flop circuit 7 that outputs data in synchronization with the transmission clock signal h output from the transmission clock generation unit 5, and the transmission clock according to the signal from the phase comparison unit 4. By initializing the internal state of the generation unit 5, a transmission clock signal h that is delayed by a certain amount with respect to the extracted clock signal d extracted by the clock extraction unit 3 is generated and synchronized with the transmission clock signal h. Then, the data is transmitted, and this can be the embodiment of claim 2.

Therefore, from the received signal a which has passed through the receiver circuit 1 for transmitting and receiving data via the communication line,
The clock extraction unit 3 extracts the extracted clock signal d from the received signal, and sends the signal phase information of the extracted clock signal d to the phase comparison unit 4. The phase comparison unit 4 outputs a phase matching detection signal f to the transmission clock generation unit 5 when the phase information of the sent extracted clock signal d matches the preset reference phase value. The transmission clock generation unit 5 initializes the internal state when the phase matching detection signal f is sent, so that the transmission clock delayed by the reference phase value set in advance with respect to the extraction clock signal d. The signal h can be generated and the data can be transmitted to the driver circuit 8 in synchronization with the transmission clock signal h. Further, by setting the reference phase value set in advance to an appropriate value, the delay time due to the driver circuit 1, the receiver circuit 8 and the like can be compensated.

Therefore, the circuit for guaranteeing the delay time by the driver circuit 1, the receiver circuit 8 and the like is smaller than the conventional circuit, and if the same operation clock as the clock extraction unit 3 is used, the delay control can be performed. It is possible to reduce the error in the case.

Further, the communication interface circuit of the present embodiment provides the clock extraction unit 3 for extracting a clock signal from the received signal a, the phase information of the extracted clock signal d and the preset reference phase value. The phase comparison unit 4 for comparison, the transmission clock generation unit 5 for generating the transmission clock signal h for determining the timing of the transmission signal, and the transmission clock signal h output from the transmission clock generation unit 5 are synchronized with each other. Flip-flop circuit 7 for outputting data
And a synchronous transmission unit consisting of, and initializes the internal state of the transmission clock generation unit 5 in accordance with the signal from the phase comparison unit 4 so that the extracted clock signal d extracted by the clock extraction unit 3 is To generate a transmission clock signal h delayed by a certain amount, and to generate the transmission clock signal h
The data is transmitted in synchronism with the above, and this can be the embodiment of claim 1.

Therefore, the clock extraction unit 3 extracts the clock signal from the received signal and sends the signal phase information of the extracted clock d to the phase comparison unit 4. The phase comparison unit 4 outputs a phase matching detection signal f to the transmission clock generation unit 5 when the phase information of the sent extracted clock signal d matches the preset reference phase value. The transmission clock generation unit 5 initializes the internal state when the phase matching detection signal f is sent, so that the transmission clock delayed by the reference phase value set in advance with respect to the extraction clock signal d. Generate signal h.

Therefore, the circuit for guaranteeing the delay time by the driver circuit 1 and the receiver circuit 8 is smaller than the conventional circuit, and if the same operation clock as the clock extraction unit 3 is used, the delay control can be performed. It is possible to reduce the error in the case.

The transmission clock generation unit 5 of the communication interface circuit of this embodiment is the counter circuit 22, which can be used as the embodiment of claim 3. In the embodiment of this type, by using the transmission clock generation unit 5 as a counter circuit, it is not necessary to prepare a bit length proportional to the bit length to be adjusted as compared with the conventional shift register, and the circuit is not necessary. Can be miniaturized.

Further, the clock extraction unit 3 of the communication interface circuit of the present embodiment operates the counter circuit of the transmission clock generation unit 5 and the counter circuit 22 of the clock extraction unit 3 with the same clock signal, and the phase comparison unit When the internal state of the transmission clock generation unit 5 is initialized according to the signal from the signal No. 4, the initialization is performed in synchronization with the clock signal, which can be the embodiment of claim 4.
In the embodiment of this type, the counter circuit of the transmission clock generation unit 5 and the counter circuit 22 of the clock extraction unit 3 are operated with the same clock signal, and the transmission clock generation unit 5 is operated according to the signal from the phase comparison unit 4. When the internal state of (1) is initialized, the initialization is performed in synchronization with the clock signal, and a clock delayed by the reference phase value set in advance with respect to the extracted clock signal d is generated. Therefore, by setting the reference phase value set in advance to an appropriate value, the delay time due to the driver circuit 1, the receiver circuit 8 and the like can be compensated. Further, the counter value can be arbitrarily set, the relationship between the bit length to be adjusted and the bit capacity of the counter is not directly proportional, and a counter having a bit length equal to or less than the bit length to be adjusted can be used, so that the size can be reduced.

By the way, in the present embodiment, as the operation clock b of the DPLL, a clock 64 times the clock of the received signal is used, but a clock signal N times (N: integer) the received signal is used as the operation clock b. It is also possible to use it. At this time, the number of bits of the counter circuit 22 inside the DPLL is determined according to the number of bits of the operation clock b.

Then, the DPLL is used as the clock extraction unit 3.
However, when the present invention is implemented, any clock extraction circuit capable of outputting phase information may be used.

Further, the extracted clock signal d and the transmission clock signal h output from the clock extraction unit 3 are the most significant bits of the 6-bit synchronous counter included in each circuit unit in this embodiment. However, when the present invention is carried out, it is only necessary that the clock signals of the same cycle are output, and it is not necessary to have the same number of bits of the synchronous counter or to take out the output signal from the most significant bit. .

[0046]

As described above, according to the communication interface circuit of the first aspect, the clock extracting unit extracts the clock signal from the received signal and sends the signal phase information of the extracted clock to the phase comparing unit. The phase comparison section outputs a phase coincidence detection signal to the transmission clock generation section when the phase information of the transmitted extracted clock signal matches the preset reference phase value. The transmission clock generation unit generates a clock delayed by the preset reference phase value with respect to the extracted clock signal by initializing the internal state when the phase matching detection signal is sent. Therefore, the circuit for guaranteeing the delay time due to the driver circuit and receiver circuit is smaller than the conventional circuit, and if the same operating clock as the clock extraction circuit is used, the error in delay control can be suppressed to a small level. be able to.

According to the second aspect of the communication interface circuit, the clock signal is extracted from the received signal which has passed through the receiver circuit for transmitting and receiving data via the communication line by the clock extraction section, and the extracted clock is extracted. The signal phase information is sent to the phase comparison unit. The phase comparison section outputs a phase coincidence detection signal to the transmission clock generation section when the phase information of the transmitted extracted clock signal matches the preset reference phase value. The transmission clock generation unit generates the transmission clock signal delayed by the preset reference phase value with respect to the extracted clock signal by initializing the internal state when the phase matching detection signal is sent. However, since the data is transmitted to the driver circuit in synchronization with the transmission clock signal, the circuit for guaranteeing the delay time due to the driver circuit and the receiver circuit is smaller than the conventional circuit, If the same operation clock as that of the extraction circuit is used, the error in delay control can be suppressed to be small.

According to the communication interface circuit of the third aspect, by using the transmission clock generation unit as the counter circuit, it is not necessary to prepare a bit length proportional to the bit length to be adjusted, and the transmission clock generation unit is countered. By using a circuit, it is not necessary to prepare a bit length proportional to the bit length to be adjusted as compared with a conventional shift register, and the circuit can be downsized.

According to another aspect of the communication interface circuit of the present invention, the clock extraction unit operates the counter circuit of the transmission clock generation unit and the counter circuit of the clock extraction unit with the same clock signal, and the clock extraction unit operates according to the signal from the phase comparison unit. When the internal state of the transmission clock generation unit is initialized, the initialization is performed in synchronization with the clock signal, and a clock delayed from the extracted clock signal by a preset reference phase value is generated.

Therefore, the counter value can be arbitrarily set, the relationship between the bit length to be adjusted and the bit capacity of the counter is not in direct proportion, and a counter having a bit length equal to or less than the bit length to be adjusted can be used. Can be converted.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a case where a communication interface circuit according to a first embodiment of the present invention is connected to a line of an ISDN basic user / network interface.

FIG. 2 is a block configuration diagram using a DPLL (Digital Phase Locked Loop) as a clock extraction unit used in the communication interface circuit of the first embodiment of the present invention.

FIG. 3 is a timing chart of signals in the communication interface circuit according to the embodiment of the present invention.

FIG. 4 is a frame configuration diagram at an ISDN basic user / network interface reference point S / T.

FIG. 5 is a block diagram of an entire conventional communication interface circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 receiver circuit 2 frame disassembling unit 3 clock extracting unit 4 phase comparing unit 5 transmission clock generating unit 6 frame assembling unit 7 flip-flop circuit 8 driver circuit 22 counter circuit 25 phase control unit 26 counter value setting unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9466-5K H04L 11/02 Z

Claims (4)

[Claims] 1. A clock extraction unit that extracts a clock signal from a received signal, a phase comparison unit that compares phase information of the extracted extracted clock signal with a preset reference phase value, and a timing of the transmission signal. The phase comparison unit includes a transmission clock generation unit that generates a transmission clock signal to be determined, and a synchronous transmission unit that outputs data in synchronization with the transmission clock signal output from the transmission clock generation unit. By initializing the internal state of the transmission clock generation unit according to the signal from, the transmission clock signal is generated with a certain delay with respect to the extracted clock signal extracted by the clock extraction unit. A communication interface circuit characterized by transmitting data in synchronization with. 2. A clock extraction unit for extracting a clock signal from a received signal in a communication interface circuit for compensating for a delay time of a receiver circuit and a driver circuit for transmitting / receiving data via a communication line and adjusting a deviation of a transmission / reception timing. And a phase comparison unit that compares the phase information of the extracted clock signal extracted by the clock extraction unit with a preset reference phase value, and a transmission clock that generates a transmission clock signal that determines the timing of the transmission signal. The internal state of the transmission clock generation unit includes a generation unit and a synchronous transmission unit that outputs data in synchronization with the transmission clock signal output from the transmission clock generation unit, according to a signal from the phase comparison unit. By initializing the clock, a fixed delay is applied to the extracted clock signal extracted by the clock extraction unit. Communication interface circuitry credit generates a clock signal, and transmits data in synchronism with the transmission clock signal. 3. The communication interface circuit according to claim 1, wherein the transmission clock generation unit is a counter circuit. 4. The clock extraction unit operates the counter circuit of the transmission clock generation unit and the counter circuit of the clock extraction unit with the same clock signal, and the internal circuit of the transmission clock generation unit according to the signal from the phase comparison unit. 4. The communication interface circuit according to claim 1, wherein when the state is initialized, the initialization is performed in synchronization with the clock signal.