JPH10320983A - Non-volatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set a threshold voltage margin to a small value to realize low voltage drive and multi-level memory by using MOS transistor for voltage generation which is formed in the structure different from MOS transistor forming a memory cell to provide a changing rate of threshold voltage depending on the particular temperature. SOLUTION: Using a MOS transistor having a changing rate of threshold value due to the temperature of 50 to 150% of that of the MOS transistor forming a memory, its threshold voltage is added to the voltage having the changing rate by temperature equal to -20% to 20% of the MOS transistor forming the memory cell. A charge accumulating layer of transistor MC is set to the electrically floating condition like the memory cell, the control gate and drain are connected in common and are then connected to the power supply end 1 via a resistance element R. The source of transistor MC is connected to an input end 2 and a small constant voltage Vbgr which changes depending on temperature is input to the input end 2 to read a voltage of the output end 3 as the read voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device in which the temperature dependence of a read voltage and a verify voltage is close to the temperature dependence of a threshold voltage of a memory cell. .

[0002]

2. Description of the Related Art Conventionally, in a read-only nonvolatile semiconductor memory device (ROM), two kinds of threshold voltages Vt (Vt1, Vt2) of memory cell transistors are provided, so that data "0" and "0" are respectively obtained. 1 "is stored. The threshold voltage Vt is Vt = Vfb + X {2Fi × Fn × (2Fi-Vbs) + g × Fs (2Fi-Vbs)}
Expressed as ^1/2 . Here, Vfb is the flat band voltage (which is proportional to the difference Fi-ms between the work function of the gate and the silicon substrate), and X is the polarity of the channel (+1, n-channel).
In the case of p-channel -1), Fi is Fermi potential, Fn is a correction coefficient of a narrow channel effect, Vbs is a potential difference between a substrate and a source, g is a back bias effect coefficient, Fs
Is a short channel effect correction coefficient. Usually, the two types of threshold voltages can be changed by changing the dose amount of the channel implantation and changing the Fi-ms.

At the time of reading, the gate voltage Vg of the memory cell is
Is set between two types of threshold voltages (Vt1 <Vt2). When a memory cell with the threshold voltage Vt1 is read, the memory cell transistor is turned on, and a drain current flows. On the other hand, when the memory cell of the threshold voltage Vt2 is read, the drain current does not flow because the memory cell transistor is turned off. Therefore, data can be read by detecting whether or not a drain current flows.

By the way, when the temperature changes, the difference Fi-ms between the work function of the gate and the silicon substrate and the Fermi potential Fi change, so that the threshold voltage of the memory cell changes. On the other hand, the gate voltage for reading is a power supply voltage or a divided voltage, and does not fluctuate even with a fluctuation in temperature. Therefore, even if the threshold voltage fluctuates due to a temperature change, etc.
It was necessary to ensure a sufficient difference between the two threshold voltages.

However, if an attempt is made to increase the amount of information per unit memory cell by lowering the power supply voltage or by giving the memory cells three or more threshold voltages, this large threshold voltage margin becomes a problem. Come.

FIG. 10 shows an example of a conventional read voltage generation circuit for reference. This is a voltage dividing circuit by resistance division using two resistors R17 and R18 made of the same material. FIG. 11 is a diagram for explaining a threshold voltage margin. The solid line is the threshold voltage distribution at normal temperature, and the dashed line is the threshold voltage distribution at high temperature. The higher the temperature, the lower the threshold voltage. Therefore, even if the read margin is appropriately set at normal temperature, the minimum value of the higher threshold voltage Vt2 becomes small at high temperature and protrudes into the margin area, so that the actual read margin is smaller than the original read margin. .

On the other hand, in a nonvolatile semiconductor memory device (EEPROM) having electrically rewritable means, an FET-MOS structure in which a charge storage layer (floating gate) and a control gate are stacked is used as a memory cell. EEP
In a ROM, usually, a voltage higher than a power supply voltage is applied to a memory cell at the time of rewriting, and a charge amount of a charge storage layer is controlled by a tunnel current or the like. Since the threshold voltage of the memory cell changes according to the amount of charge, two types of threshold voltages (Vt1 <Vt2) can be obtained. At the time of erasing, all data are set to one threshold voltage (for example, Vt1) in a data unit of a certain length.
Writing is performed selectively for each bit, the threshold voltage of the selected memory cell is set to Vt2, and the threshold voltage of the non-selected memory cell is kept at Vt1.

In order to minimize the threshold voltage of a memory cell to be erased or the threshold voltage of a memory cell to be written, the verify read is performed. This is reading for confirming whether or not all bits of each bit or the erasing unit have been sufficiently written or erased after writing or erasing. In order to secure a sufficient margin between the two types of threshold voltages, a voltage Vvrfy higher than the normal read voltage Vread is applied to the gate of the memory cell, for example, during write verification.

In this type of EEPROM, as in the above-described ROM, the threshold voltage of the memory cell changes when the temperature changes, but the read voltage and the verify voltage are constant regardless of the temperature. For this reason, it is necessary to secure a sufficient difference between the two threshold voltages. Also,
This threshold voltage margin needs to be larger than that of the ROM. For example, verify voltage Vvr
This is because the temperature may be high when fy is applied and low when normal read voltage Vread is applied. Further, as in the case of the ROM, the power supply voltage may drop, or three
If an attempt is made to increase the amount of information per unit memory cell by providing more than two types of threshold voltages, this large threshold voltage margin becomes a larger problem.

[0010]

As described above, the conventional RO
In nonvolatile semiconductor memory devices such as M and EEPROM, the threshold voltage of the cell transistor fluctuates due to a temperature change, so that it is necessary to set a large threshold voltage margin. It was an obstacle to realizing it.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to set a small threshold voltage margin, thereby contributing to low-voltage driving and the realization of a multi-valued memory. The present invention provides a nonvolatile semiconductor memory device that can be used.

[0012]

[Means for Solving the Problems]

(Structure) In order to solve the above problem, the present invention employs the following structure.

That is, the present invention (claim 1) provides a nonvolatile semiconductor memory device for reading stored data by applying a read voltage to a memory cell having a different threshold voltage depending on a data storage state. And a structure different from the MOS transistor forming the memory cell, wherein the rate of change of the threshold voltage due to temperature is 50 to 150% of that of the MOS transistor forming the memory cell. A MOS transistor is used, and the threshold voltage of the voltage generating MOS transistor and the rate of change due to temperature change the Mth of the memory cell.
A means for adding a voltage between -20% and 20% of that of the OS transistor is provided.

According to the present invention (claim 2), there is provided a memory cell having a threshold voltage different depending on a data storage state, and a verify voltage for confirming whether or not rewriting has been sufficiently performed at the time of rewriting data. In the electrically rewritable nonvolatile semiconductor memory device to which the voltage is applied, in order to generate the verify voltage, an MO forming the memory cell is formed.
It has a structure different from that of the S transistor, and the rate of change of the threshold voltage due to temperature is 50 to 150% of that of the MOS transistor forming the memory cell.
The ratio of the threshold voltage of the MOS transistor for generating voltage and the rate of change due to temperature is -20% to 20% of that of the MOS transistor forming the memory cell.
%, A means for adding the voltage in%.

Here, preferred embodiments of the present invention include the following.

(1) The memory cells constitute a read-only nonvolatile semiconductor memory device (ROM). (2) The memory cells constitute an electrically rewritable nonvolatile semiconductor memory device (EEPROM). (3) The MOS transistor forming the memory cell has a two-layer gate structure having a floating gate and a control gate, and the voltage generating MOS transistor has a single-layer gate structure.

(4) A MOS transistor having a single-layer gate structure used as a means for generating a read voltage has a gate and a drain connected in common, and is connected to a power supply terminal via a load resistor. No constant voltage (the rate of change due to temperature is
(A voltage in the range of -20% to 20% of that of the transistor), and taking out an output voltage appearing at the drain when the MOS transistor is in an on state as a read voltage.

(5) A single-layer gate MOS transistor used as a means for generating a read voltage is a plurality of types of single-layer gate MOS transistors mounted on the same chip as a two-layer gate MOS transistor constituting a memory cell. Among the transistors, a MOS transistor having the closest temperature dependence of the threshold voltage to the MOS transistor having the two-layer gate structure. (6) The MOS transistor having a single-layer gate structure used as a means for generating a read voltage has a positive threshold voltage.

(7) A MOS transistor having a single-layer gate structure used as a means for generating a verify voltage has a gate and a drain commonly connected and is connected to a power supply terminal via a load resistor, and the source has almost no temperature dependence. No constant voltage (the rate of change due to temperature is
Voltage at -20% to 20% of that of S transistor)
Is applied, and an output voltage appearing at the drain when the MOS transistor is on is taken out as a verify voltage.

(8) A single-layer gate MOS transistor used as a means for generating a verify voltage is a plurality of types of single-layer gate MOS transistors mounted on the same chip as a two-layer gate MOS transistor constituting a memory cell. Among the transistors, a MOS transistor having the closest temperature dependence of the threshold voltage to the MOS transistor having the two-layer gate structure. (9) A single-layer gate MOS transistor used as a means for generating a verify voltage has a positive threshold voltage.

(10) As means for generating a constant voltage having almost no temperature dependence, a resistor R1 connected between the non-inverting input terminal and the output terminal of the operational amplifier and a resistor R1 connected between the non-inverting input terminal and the ground terminal are used. , A resistor R2 connected between the inverting input terminal and the output terminal of the operational amplifier, and a series circuit of a resistor R3 and a diode D2 inserted between the inverting input terminal and the ground terminal. Having prepared.

(11) As a means for generating a constant voltage having almost no temperature dependence, a diode having a breakdown voltage with small temperature dependence is used, and the reference voltage obtained by the diode is divided. (12) A diode used as a means for generating a constant voltage having almost no temperature dependency has a breakdown voltage of 4 V or more and 6 V or less. (13) The memory cell has three or more threshold voltages.

The present invention (claim 7) comprises a MOS transistor having a two-layer gate structure having a charge storage layer and a control gate in an electrically floating state,
In a nonvolatile semiconductor memory device that reads stored data by applying a read voltage to a memory cell having a threshold voltage that differs depending on a data storage state, an electrically floating state is used to generate the read voltage. A MOS transistor for generating a voltage having the same structure as that of the memory cell having a charge storage layer and a control gate, wherein a threshold voltage of the MOS transistor for generating a voltage and a rate of change due to temperature change the MOS transistor forming the memory cell.
A means is provided for adding a voltage between -20% and 20% of that of the transistor.

The present invention (claim 8) comprises a MOS transistor having a two-layer gate structure having a charge storage layer and a control gate in an electrically floating state,
An electrically rewritable nonvolatile semiconductor memory device having memory cells having different threshold voltages depending on the storage state of data and applying a verify voltage for confirming whether or not the data has been sufficiently rewritten when rewriting data A voltage generating MOS having the same structure as the memory cell having a charge storage layer and a control gate which are electrically floating to generate the verify voltage.
The ratio of the change in the threshold voltage of the voltage generating MOS transistor to the temperature is -20% to 20% of that of the MOS transistor forming the memory cell.
And a means for adding the voltage of (1).

In the present invention, the above (1) to (1)
The preferred embodiment shown in 3) can be applied.

(Function) In the present invention (claim 1), the read voltage is substantially equal to the threshold voltage Vt 'of the MOS transistor other than the memory cell having the temperature dependence of the threshold voltage close to the memory cell. Constant voltage Vbg without temperature dependency
Since the sum is equal to the sum of r and (Vbgr + Vt '), the temperature dependence of the read voltage can be made substantially equal to the temperature dependence of the threshold voltage of the memory cell. Therefore, even if the threshold voltage of the memory cell fluctuates due to a temperature change, data is not erroneously read.

According to the present invention (claim 2), the verify voltage is substantially temperature dependent on the threshold voltage Vt 'of the MOS transistor other than the memory cell having a temperature dependence of the threshold voltage close to the memory cell. Constant voltage Vbgr
(Vbgr + Vt '), the temperature dependence of the verify voltage can be made equal to the temperature dependence of the threshold voltage of the memory cell.

Further, according to the present invention (claim 7), the read voltage is determined as the sum (Vbgr + Vt) of the constant voltage Vbgr having substantially no temperature dependence and the threshold voltage Vt of the memory cell having temperature dependence. Therefore, the temperature dependence of the read voltage can be made equal to the temperature dependence of the threshold voltage of the memory cell. Therefore, even if the threshold voltage of the memory cell fluctuates due to a temperature change, data is not erroneously read.

Further, in the present invention (claim 8), the verify voltage is a sum (Vbgr + Vt) of the constant voltage Vbgr having substantially no temperature dependence and the threshold voltage Vt of the memory cell having temperature dependence. Therefore, the temperature dependency of the verify voltage can be made equal to the temperature dependency of the threshold voltage of the memory cell.

Therefore, according to the present invention, the threshold voltage margin can be set small, which can contribute to the realization of low-voltage driving and a multi-valued memory. Further, in the present invention (claims 1 and 2), since a MOS transistor (single-layer gate structure) different from a MOS transistor (two-layer gate structure) forming a memory cell is used as the voltage generation means, The degree of freedom of design when constructing is increased. Further, in the present invention (claims 7 and 8), since the MOS transistor (two-layer gate structure) having exactly the same structure as the MOS transistor forming the memory cell is used as the voltage generating means, There is no danger of increasing the number of manufacturing processes.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 13 is a circuit configuration diagram showing a temperature-compensated read voltage generation circuit in the nonvolatile semiconductor memory device according to the embodiment.

This circuit has a voltage-generating MOS transistor MC having the same structure formed by the same process as the MOS transistor of the memory cell constituting the ROM or EEPROM.
And a high-resistance element R. Transistor MC
The charge storage layer is electrically floating like the memory cell portion. The control gate and the drain are commonly connected, and these are connected to the power supply terminal 1 via the resistance element R. The source of the transistor MC is the input terminal 2
The input terminal 2 is supplied with a constant voltage Vbgr having a small temperature dependency. The drain of the transistor MC is connected to the output terminal 3, and the output voltage appearing at the output terminal 3 is used as a read voltage.

The output voltage Vg appearing at the output terminal 3 of the read voltage generation circuit in the present embodiment is
Vg = Vbgr + Vt using the threshold voltage Vt of If the amount of change in the threshold voltage Vt of the transistor MC when the temperature changes is dVt, and the amount of change in the output voltage, that is, the gate voltage Vg of the memory cell is dVg, Vbgr
DVg = dVt. That is, the amount of change in the read voltage is equal to the amount of change in the threshold voltage. However, since it is not good that the threshold voltage of the transistor MC is changed by the injection (writing) of the charge into the charge storage layer, the voltage applied to the transistor MC should be limited to a level that does not cause the injection of the charge into the charge storage layer. It is desirable to design a circuit.

As described above, according to the present embodiment, the temperature fluctuation of the read voltage used for reading data from the memory cell can be made equal to the temperature fluctuation of the threshold voltage of the memory cell. It is not necessary to take an unneeded margin, and low-voltage operation and multi-valued memory can be easily realized. In this case, since the transistor MC can be configured exactly the same as the memory cell without connecting the charge storage layer to the gate, the manufacturing process does not increase due to the transistor MC of the read voltage generation circuit.

FIG. 2 shows a constant voltage Vbg having a small temperature dependency.
FIG. 3 is a diagram illustrating a bandgap reference circuit that outputs r.

The resistor R1 is connected between the non-inverting input terminal and the output terminal of the operational amplifier 4, the diode D1 is inserted between the non-inverting input terminal and the ground terminal, and the inverting input terminal and the output terminal of the operational amplifier 4 are connected. A resistor R2 is connected between the inverting input terminal and the ground terminal, and a series circuit of a resistor R3 and a diode D2 is inserted between the inverting input terminal and the ground terminal. The output terminal of the operational amplifier 4 is connected to the input terminal 2 of the read voltage generation circuit.

This circuit is known as a bandgap reference circuit (analog integrated circuit design technology (above): Baifukan, p275-276, PR Gray / R.
G. FIG. As shown by the following equation, the output voltage Vbgr remains constant even when the temperature changes.

The _{Vbgr = Vf1 + αV T V T} = kT / q where the ratio of α resistor (R2 / R1) and a constant determined by (R2 / R3), etc., k is Boltzmann's constant, T is the absolute temperature, q is the elementary charge Quantity.

FIG. 3 is a diagram showing a circuit for outputting a constant voltage Vbgr having a small temperature dependency using a diode D3 having a breakdown voltage having a small temperature dependency. This circuit is also known as a bandgap reference circuit (analog integrated circuit design technology (above): Baifukan, p270-272, PR Gray / RG Mayer) and changes in temperature. Also, the output voltage remains constant as in the above equation.

Incidentally, reference numeral 5 in the drawing denotes a voltage generation circuit, and R6 to R6.
Reference numeral 9 denotes a resistance element, and Qp1 denotes a pMOS transistor. As the diode D3, it is preferable to use a diode having a breakdown voltage having little temperature dependency of 4 V or more and 6 V or less.

FIG. 4 is an improved version of the circuit of FIG. 3, showing a circuit capable of outputting a plurality of temperature-compensated read voltage levels.

The output of the operational amplifier is input to the gate of the pMOS transistor Qp2 whose drain is connected to the power supply terminal, and the drain of the transistor Qp2 is connected to the non-inverting input terminal of the operational amplifier via the resistor R10. A constant voltage Vbgr is input to the inverting input terminal of the operational amplifier.
The non-inverting input terminal of the operational amplifier includes a resistor R1
1, R12, R13 are connected in series, and the resistance elements R11, R12
Is connected to the input terminal 2 of the read voltage generation circuit shown in FIG. The connection point between the resistance elements R12 and R13 is nM
The resistance element R13 is connected to the ground terminal via the nMOS transistor Qn2, and is connected to the ground terminal via the OS transistor Qn1.

In such a configuration, the resistance elements R11, R11,
Assuming that the resistance values of R12 and R13 are r1, r2 and r3 respectively, when the input voltage V1 is "H", the output voltage Vg1 becomes Vg1 = r2 / (r1 + r2) .times.Vbgr, and when the voltage V2 is "H". The output voltage Vg2 is as follows: Vg2 = (r2 + r3) / (r1 + r2 + r3) × Vbgr Since Vg1 <Vg2, the write verify voltage Vread is set to (Vg2 + Vt), and the normal read voltage Vvrfy is set to (Vg1 + Vt), so that Vre at the time of temperature change is changed.
The amount of change between ad and Vvrfy can be made equal. Therefore, a margin between adjacent threshold voltages does not need to be taken unnecessarily, and a low-voltage operation and a multi-valued memory can be easily realized.

(Second Embodiment) In this embodiment, a temperature-compensated read voltage and verify voltage are generated by optimizing the parameters of the bandgap reference circuit shown in FIG. The temperature dependency of the threshold voltage of the memory cell is -2 mV / ° C, and the normal temperature T ₀
The case where the read voltage is 1.0 V and the verify voltage is 1.5 V is considered.

FIG. 5 is a diagram showing a band gap reference circuit according to the present embodiment. 2, two diodes D1, D2 and three resistors R1, R
2, R3, and one operational amplifier 4. However,
The resistor R3 is divided into resistors r1 and r2 (R3 = r1 + r2)
The nMOS transistor Qn3 is connected in parallel with r2.

It is known that the output voltage Vbgr at this time is given by Vbgr = Vf1 + αVtα = R2 / R3 · Ln {(R2 × A2) / (R1 × A1)} Vt = kT / q Here, Vf1 is a forward bias of the diode D1, A1 and A2 are junction areas of the diodes D1 and D2, k is a Boltzmann constant, T is an absolute temperature, and q is an elementary charge. Resistance R1
Even if R3 has a temperature dependency, the ratio does not have a temperature dependency, so that the temperature dependency of Vbgr can be changed by a constant α.

Now, the read voltage and the verify voltage are set to V
When obtained by resistance division of bgr, the temperature coefficient also changes by the division ratio. Therefore, the constant α for each voltage
Need to give. Voltage at room temperature T ₀ Vf1 = _0.
When the voltage coefficient is 6 V and the temperature coefficient is −2 mV / ° C., the voltage Vbgr at the temperature T is as follows: Vbgr = (0.6−0.024α) + 8 × 10 ⁻⁵ (α−25) (T−T ₀ ) When the gate voltage of the memory cell (read voltage and verify voltage) Vcg is to be obtained by the β times the voltage Vbgr, Vcg = βVbgr this time, the gate voltage Vcg at normal temperature T ₀ and the voltage Vbg
Assuming that r is Vcg0 and Vbgr0, respectively, Vcg0 = 1.0
The parameter α for each of V and 1.5 V needs to take the value of (Table 1) below.

[0049]

[Table 1]

Table 1 also shows the voltage Vbgr0 and the coefficient β at that time. Given the parameter α, 5
Although one parameter set, that is, three resistance values and two diode pn junction areas cannot be uniquely determined, for example, A1 = A2, R1 = 25 kΩ, R1
2 = 100 kΩ, R3 = 22 kΩ (Vcg0 = 1.0
V), 29 kΩ (Vcg0 = 1.5 V).

FIG. 5 shows a circuit for generating two gate voltages, to which a signal RE which is "H" at the time of reading and "L" at the time of verification is input. Here, r1 = 7k
Ω, r2 = 22 kΩ.

FIG. 6 shows a state in which the voltage Vbgr is inputted and the gate voltage V
This is a circuit that outputs cg. This is a kind of voltage conversion circuit, and R4 = 2.5k corresponding to the value of β in (Table 1).
Ω, R5 = 4.4 kΩ, and R6 = 3.1 kΩ. To this circuit, a signal VRFY that becomes “H” at the time of verification is input together with the signal RE. With this configuration, two voltages Vcg can be obtained by one circuit.

That is, the circuit of FIG. 5 outputs a constant voltage Vbgr having a desired temperature characteristic, and the circuit of FIG.
The required read voltage Vcg is generated from bgr. Further, in the circuit of FIG. 5, the temperature characteristic of the constant voltage Vbgr is determined so that the temperature characteristic at the read voltage Vcg becomes equal to the temperature characteristic of the threshold voltage Vt of the memory cell.

As described above, according to the present embodiment, the constant voltage generation circuit and the voltage conversion circuit are provided for generating the read voltage, and the parameters of the constant voltage generation circuit are optimized, so that the threshold of the memory cell is obtained. A read voltage having the same temperature dependency as the value voltage Vt can be generated. Therefore, effects similar to those of the first embodiment can be obtained.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
FIG. 13 is a circuit configuration diagram showing a temperature-compensated read voltage generation circuit in the nonvolatile semiconductor memory device according to the embodiment.

This circuit is composed of a transistor Q having a different structure formed by a process different from that of the memory cell MC constituting the ROM or the EEPROM, and a high-resistance resistance element R. That is, while the MOS transistor forming the memory cell has a two-layer gate structure forming a floating gate and a control gate, the MOS transistor Q forming a voltage generating circuit has a single-layer gate structure.

The gate of the transistor Q is connected to the drain, and further connected to the power supply terminal 1 via the resistance element R. The source of the transistor Q is connected to the input terminal 2,
The input terminal 2 is supplied with a constant voltage Vbgr having a small temperature dependency. The drain of the transistor Q is connected to the output terminal 3
And an output voltage appearing at the output terminal 3 is used as a read voltage.

Using the threshold voltage Vt 'of the transistor Q, the output voltage Vg appearing at the output terminal 3 of the read voltage generation circuit in the present embodiment becomes Vg = Vbgr + Vt'. Assuming that the amount of change in the threshold voltage Vt 'of the transistor Q when the temperature changes is dVt' and the amount of change in the output voltage, that is, the gate voltage Vg of the memory cell is dVg, Vbg
The temperature fluctuation amount of r can be ignored, and dVg = dVt '. That is, the amount of change in the read voltage is equal to the amount of change in the threshold voltage.

At this time, as the transistor Q, a MOS transistor which forms a memory cell has a temperature dependence of a threshold voltage which is close to that of a MOS transistor. It can be made substantially the same as the temperature fluctuation amount of the threshold voltage. As a result, the margin between adjacent threshold voltages does not need to be unnecessarily large, and low-voltage operation and multi-valued memory can be easily realized.

Here, a chip on which a memory cell is mounted has various MOs other than the MOS transistor of the memory cell.
There is an S transistor. The following (Table 2) shows an example of the temperature dependence of the threshold voltage (Vt) of all the nMOS transistors in the nonvolatile semiconductor memory device.

[0061]

[Table 2]

Here, Vcc-nMOS-E is a transistor to which Vcc is applied to the gate and drain, and Vpp-nMO
SE, -I, and -D denote transistors whose threshold voltages to which a high voltage Vpp used for rewriting data is applied to the gate and drain are positive, ０0 V, and negative, respectively. The threshold voltage of the nMOS transistor of the memory cell fluctuates by 0.15 V due to a temperature fluctuation of 60 ° C. On the other hand, in the case of Vcc-nMOS-E, 0.11 V (73
%), 0.14 V (93%) for Vpp-nMOS-E,
0.02 V (13%) for Vpp-nMOS-I, Vpp-
In the nMOS-D, it fluctuates by 0.12 V (80%).

Of these, it is desirable to select Vpp-nMOS-E which has the temperature dependence of the threshold voltage closest to the nMOS transistor of the memory cell.
It is also possible to use nMOS-E or Vpp-nMOS-D. According to experiments by the present inventors, the rate of change in threshold voltage due to temperature is 50 to 150%, preferably 80 to 12%, for the nMOS transistor forming a memory cell.
It has been found that a sufficient effect can be obtained if the MOS transistor is at 0%.

In the circuit of FIG. 7, instead of the nMOS transistor of the memory cell, the nMOS transistor of the memory cell has a temperature dependency.
Vpp-nMOS-E [Vt (2
5 ° C.) − Vt (85 ° C.) = 0.14 V]. This is the ratio of the temperature variation of the threshold voltage of the nMOS transistor of the memory cell to 0.14 / 0.15 = 93.
%.

Conventionally, when the temperature fluctuates by 120 ° C. from −35 ° C. to + 85 ° C., which is the compensation temperature range of the semiconductor memory,
The variation of the threshold voltage of the memory cell is 0.30 V (= 0.
15V × 2), it was necessary to increase the margin between the threshold voltage distributions by 0.30V. On the other hand, when the circuit of this embodiment is used, even if the threshold voltage of the memory cell varies by 0.30 V due to the temperature variation, the read or verify voltage varies by 0.28 V in conjunction therewith. The variation of the apparent threshold voltage is only 0.02V. Therefore, the margin between the threshold voltage distributions may be increased by a net 0.02V.

As described above, since it is not necessary to secure a sufficient margin between the threshold voltage distributions, the interval between the threshold voltage distributions can be narrowed, and the reliability of the memory cell can be improved. In this case, since the temperature characteristics of a desired MOS transistor existing in the chip can be used,
The threshold voltage margin can be reduced while maintaining a high degree of design freedom.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
FIG. 13 is a circuit configuration diagram showing a temperature-compensated read voltage generation circuit in the nonvolatile semiconductor memory device according to the embodiment.

This embodiment is a voltage dividing circuit based on resistance division using two resistors R10 and R11 having different temperature characteristics. One end of each of the resistors R10 and R11 is connected to the input terminal 2 of the reference voltage, and the common connection portion, which is the other end of each of the resistors R10 and R11, is connected to the output terminal 3. Here, when the rates of change of the resistance values of the resistors R10 and R11 with temperature are represented by a0 and a1, respectively, a material satisfying a0> a1 is selected. Then, when the temperature rises, the output voltage V0 falls, and when the temperature falls, V0 rises.

The rate of change due to temperature is changed from 50% of the rate of change in threshold voltage of the memory cell due to temperature to 15%.
The resistance values of the two resistance elements and the magnitudes of the two reference voltages are determined so as to be 0%. By using this V0 as the read voltage and the verify voltage of the memory cell, the rate of change of the apparent threshold voltage due to temperature can be suppressed within 50%.

(Fifth Embodiment) The present invention is applied to multi-level (four-level)
FIG. 9 shows an example applied to a memory. Assuming that the four values are "0", "1", "2", and "3", the threshold voltage changes with temperature at each value.

As described in the first embodiment, in the binary memory, the margin between adjacent threshold voltages can be reduced by dVt as compared with the prior art. Similarly, also in the third embodiment, the margin between threshold voltages can be reduced by about dVt. In a quaternary memory cell, since there are three margins between threshold voltages in the quaternary memory cell, the total margin can be reduced by 3 dVt.

Generally, a nonvolatile N-valued EEPROM (N
In ≧ 3), the threshold voltage of the memory at the “0” value often increases due to repeated read operations, and the threshold voltage of the “N−1” value decreases over time, Causes a data error. The frequency of occurrence of such an error depends on the difference in threshold voltage between "0" and "N-1", and the smaller the difference in threshold voltage, the higher the frequency. It has been difficult to reduce the margin between the total threshold voltages in the memory. .

On the other hand, in the present embodiment, a memory cell having a total margin between threshold voltages of N values is (N-1)
× dVt. For this reason, the threshold voltage difference between “0” and “N−1” can be set small, and a more reliable multi-valued memory cell can be realized by reducing the error frequency.

The present invention is not limited to the above embodiments. Memory cell is ROM or EEPROM
The threshold voltage is not limited to that constituting M, but may be any as long as it has a plurality of threshold voltages. Further, the present invention is not limited to the read voltage and the verify voltage, and can be applied to a portion requiring a voltage having the same temperature characteristic as the threshold voltage of the memory cell transistor. In addition, various modifications can be made without departing from the scope of the present invention.

[0075]

As described above in detail, according to the present invention, a structure different from a MOS transistor forming a memory cell is provided.
A MOS transistor for generating a voltage in which the rate of change of the threshold voltage due to temperature is 50 to 150% of that of the MOS transistor forming the memory cell, or a voltage generating MO having the same structure as the MOS transistor forming the memory cell
The ratio of the threshold voltage of the MOS transistor for generating voltage and the rate of change due to temperature is -20% to 20% of that of the MOS transistor forming the memory cell.
%, The temperature dependence of the read voltage and the verify voltage can be made closer to the temperature dependence of the threshold voltage of the memory cell, so that the threshold voltage margin can be reduced. As a result, it is possible to contribute to the realization of low-voltage driving and multi-valued memory.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a temperature-compensated read voltage generation circuit according to a first embodiment.

FIG. 2 is a diagram illustrating a circuit that outputs a constant voltage with small temperature dependence.

FIG. 3 is a diagram showing a circuit that outputs a constant voltage with small temperature dependence.

FIG. 4 is a diagram showing a circuit that can output a plurality of temperature compensation read voltage levels.

FIG. 5 is a diagram showing a constant voltage generation circuit having a temperature coefficient according to a read voltage.

FIG. 6 is a diagram showing a circuit for generating a read voltage Vcg corresponding to a constant voltage Vbgr.

FIG. 7 is a circuit configuration diagram showing a temperature-compensated read voltage generation circuit according to a third embodiment.

FIG. 8 is a circuit configuration diagram showing a temperature-compensated read voltage generation circuit according to a fourth embodiment.

FIG. 9 is a diagram showing an example in which the present invention is applied to a multi-level (quaternary) memory.

FIG. 10 is a diagram showing an example of a conventional read voltage generation circuit.

FIG. 11 is a diagram illustrating a threshold voltage margin.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Power supply terminal 2 ... Input terminal 3 ... Output terminal 4 ... Op amp MC ... Voltage generating transistor (double layer gate structure) Q ... Voltage generating transistor (single layer gate structure) Qn ... n channel MOS transistor Qp ... p channel MOS Transistors R, R1 to R17 ... resistors D1 to D3 ... diodes

Claims (8)

[Claims] 1. A nonvolatile semiconductor memory device for reading data stored by applying a read voltage to a memory cell having a different threshold voltage depending on a storage state of the data. It has a structure different from that of the MOS transistor forming the memory cell, and the rate of change of the threshold voltage due to temperature is different from that of the MO transistor forming the memory cell.
A MOS transistor for voltage generation which is 50 to 150% of that of the S transistor is used, and the ratio of the threshold voltage of the MOS transistor for voltage generation and the rate of change due to temperature is -20 of that of the MOS transistor forming the memory cell.
%. A nonvolatile semiconductor memory device comprising means for adding a voltage in the range of% to 20%. 2. An electrically rewritable memory cell having a memory cell having a threshold voltage which differs depending on a data storage state, and applying a verify voltage for confirming whether or not the data has been sufficiently rewritten when rewriting data. In the non-volatile semiconductor memory device, in order to generate the verify voltage, the MOS transistor forming the memory cell has a different structure, and the rate of change of the threshold voltage due to temperature is M
A voltage generating MOS transistor which is 50 to 150% of that of the OS transistor is used.
The rate of change due to the threshold voltage of the transistor and the temperature is -2 of that of the MOS transistor forming the memory cell.
A nonvolatile semiconductor memory device comprising a means for adding a voltage between 0% and 20%. 3. The MOS transistor forming the memory cell has a two-layer gate structure having a charge storage layer and a control gate, and the voltage generating MOS transistor has a single-layer gate structure. 3. The nonvolatile semiconductor memory device according to item 2. 4. The voltage-generating MOS transistor has a gate and a drain connected in common and is connected to a power supply terminal via a load resistor, and a source has a rate of change due to temperature corresponding to that of the MOS transistor forming the memory cell. Of -2
A voltage in the range of 0% to 20% is applied.
4. The nonvolatile semiconductor memory device according to claim 3, wherein an output voltage appearing at the drain when the OS transistor is in an on state is taken out as a read voltage or a verify voltage. 5. The voltage-generating MOS transistor is one of a plurality of types of single-layer gate MOS transistors mounted on the same chip as the two-layer gate MOS transistor forming the memory cell. Structure MO
MO transistor having the closest temperature dependency between S transistor and threshold
4. The nonvolatile semiconductor memory device according to claim 3, wherein the nonvolatile semiconductor memory device is an S transistor. 6. The nonvolatile semiconductor memory device according to claim 5, wherein said MOS transistor for generating voltage has a positive threshold voltage. 7. A two-layer gate MOS having an electrically floating charge storage layer and a control gate.
In a nonvolatile semiconductor memory device that includes a transistor and reads data stored by applying a read voltage to a memory cell having a different threshold voltage depending on a data storage state, in order to generate the read voltage, A voltage generating MOS transistor having the same structure as that of the memory cell having the charge storage layer and the control gate in a floating state is used. A nonvolatile semiconductor memory device comprising means for adding a voltage between -20% and 20% of that of a MOS transistor forming a cell. 8. A two-layer gate MOS having a charge storage layer and a control gate in an electrically floating state.
An electrically rewritable nonvolatile memory that includes a transistor and has a memory cell having a different threshold voltage depending on a data storage state, and applying a verify voltage to confirm whether or not the data has been sufficiently rewritten when rewriting data. In the nonvolatile semiconductor memory device, in order to generate the verify voltage, a voltage generating MOS transistor having the same structure as the memory cell having a charge storage layer and a control gate in an electrically floating state is used. Non-volatile memory comprising means for adding a threshold voltage of the generating MOS transistor and a voltage at which the rate of change due to temperature is in the range of -20% to 20% of that of the MOS transistor forming the memory cell. Semiconductor storage device.