JP2007299489A - Method and apparatus for generating reading/verification operation in nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To disclose a method and apparatus which generate word line voltage. <P>SOLUTION: The apparatus for generating the word line voltage is provided with a first current source, an adjustable current source and a voltage converter, and they are connected with a current addition node. The first current source generates first current, and voltage derived from the first current at least partially comprises a cell position dependent temperature coefficient varying with the position of a memory cell in the string of bit cells connected with each other. The adjustable current source generates second current which is independent substantially from temperature variation. The voltage converter is constituted so as to generate a word line signal having the word line voltage proportional to the first current. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory. More particularly, the present invention relates to compensation for temperature fluctuations that occur during the operation of a semiconductor memory.

  Non-volatile semiconductor memory has become increasingly popular in a wide range of areas, from computer systems to personal electronic products such as mobile phones, personal digital assistants, cameras and music players. With increasing popularity, there is an increasing need to place large amounts of data in individual devices and operate the devices with low power consumption.

  Nonvolatile memories, such as electrically erasable programmable memory (EEPROM) and flash EEPROM, store information in field effect transistors (FETs) using a floating gate disposed between the substrate and the control gate. FIG. 1 shows a flash cell comprising a conventional transistor used in a flash memory. The flash cell 10 includes a drain 12, a source 14, a floating gate 16, and a control gate 18. The floating gate 16 is insulated from the control gate 18 and the substrate by dielectric layers formed above and below the floating gate 16. In flash memory, the control gates of a plurality of flash cells are coupled to a word line. Thus, here the signal on the control gate or its variation is represented as Vwl.

  Assuming that the flash cell is erased first, the flash cell is programmed by placing charge on the floating gate. When charge is stored in the floating gate, it is effectively trapped in the floating gate and is not lost when power is removed. Thereafter, the stored charge is removed from the floating gate using an erase process. Programming and erasing are accomplished using various well-known mechanisms such as avalanche implantation, channel implantation, tunneling, etc., depending on the structure of the flash cell.

  FIG. 2 represents the current characteristics of the flash cell as a current versus voltage curve. In operation, an erased flash cell exhibits a current characteristic represented by curve 20 and defined as a binary “1”. As the flash cell is programmed, the additional charge on the floating gate moves the current characteristics of the flash cell to the higher voltage. The more charge is stored in the floating gate, the more the current curve moves to the right. Curve 30 shows the current characteristics of a flash cell that is safely programmed as binary “0”. Curve 25 shows the current characteristics of the flash cell with the minimum allowable programming that should be considered “0”. Line 40 shows the current threshold (Ith) that distinguishes between the programmed and unprogrammed flash cells for the sense amplifier. A flash cell is considered programmed if the current from the flash cell (Icell) is less than Ith, and a flash cell is considered unprogrammed if Icell is greater than Ith. . In other words, there is a threshold voltage (Vth), represented by line 50, through which the flash cell carries a sufficiently large current that the sense amplifier can detect. That is, after programming, the flash cell can be read by applying a voltage that is intermediate between the unprogrammed voltage and the programmed voltage. If a current is sensed by applying this voltage, the flash cell is considered unprogrammed (ie, “1” in this case). If no current is sensed, the flash cell is considered programmed (ie, “0” in this case).

  FIG. 3 represents the margin present in the flash cell being programmed for the voltage used on the word line during the read process. Curve 25 shows the current characteristics of the flash cell with the minimum allowable programming that should be considered programmed. After the flash cell is programmed, a verification process is performed. In the verification process, the flash cell is read using a verification word line voltage (Vwl_v) that provides the current Icell that is the highest voltage allowed to read the programmed flash cell and is smaller than the threshold current Ith. After this verification process, if the flash cell is not detected as being programmed, the flash cell is reprogrammed or marked as a bad cell and replaced with a replacement cell. In other words, Vwl_v represents the highest voltage on the word line from which unprogrammed flash cells are read. That is, when a flash cell is read during a normal read operation period, it is smaller than Vwl_v to ensure that there is a margin for distinguishing between programmed and unprogrammed flash cells. A word line voltage (Vwl_r) can be used.

  As described above, the current characteristics of flash cells vary with changes in temperature. This variation is shown in FIG. Curve 25L shows a flash cell programmed at a low temperature. Line Vwl_v (LT) indicates that the flash cell can be verified to be at an acceptable level at low temperatures. However, when the device is at a high temperature, the flash cell exhibits a current curve 25H. At high temperature, the highest voltage verified that the flash cell is programmed is denoted by Vwl_v (HT). That is, if the read word line voltage Vwl_r is the same voltage for the low temperature and the high temperature, the verification margin is reduced in the flash cell programmed at the low temperature and read at the high temperature, as shown in FIG. Since the current characteristics of the flash cell vary with temperature changes, this temperature change reduces the margin available to distinguish between programmed and unprogrammed flash cells.

  Also, the position of the cells in the series chain of flash memory cells dominates the threshold voltage of the flash memory cell. A temperature change also causes a change in the current flowing through the series chain of memory cells. In FIG. 5, the NAND flash array consists of an array 87 of floating gate cells arranged in series cell chains 88,89. Each floating gate cell is coupled between the drain and source in series cell chains 88 and 89. Word lines (WL_0-WL_15) through the plurality of serial cell chains 88, 89 are coupled to the control gate of any floating gate cell to control its operation.

  In operation, the word lines (WL_0-WL_15) select individual floating gate memory cells in the serial cell chain 88, 89 to be written or read, and the rest in each serial cell chain 88, 89. The floating gate memory cell is operated in the pass mode. Each series cell chain 88, 89 of floating gate memory cells is coupled to source line 90 by source select gates 94, 95, and to individual bit lines (BL1-BLN) by drain select gates 91, 92. Combined. The source selection gates 94 and 95 are controlled by a source selection gate control line SG (S) 96 to which a control gate is coupled. The drain selection gates 91 and 92 are controlled by a drain selection gate control line SG (D) 93.

  As can be seen from FIG. 5, to read one memory cell, current must flow through the other memory cells in the series cell chain 88,89. Thus, the remaining cells have a parasitic resistance in series with the drain or source connection. Since the lowest cell_0 98 in series cell chain 88 is closest to the array ground, it experiences 15 voltage drops on the drain line and one voltage drop on the source line. Cell — 15 97 located at the top of series cell chain 88 experiences 15 voltage drops on the source line and experiences 1 voltage drop on the drain line.

As is known, the current of any transistor (eg, memory cell) is determined by the transistor's V _gs and V _ds depending on the mode of operation. In saturation mode, the cell current varies mostly with V _gs and is not a function of V _ds . The transistor current varies with the square of _Vgs . In the linear mode, the current through the cell varies with V _ds .

Assuming that a particular cell is operating in saturation mode to obtain maximum gain, the bottom cell 98 of the series cell chain 88 does not experience a voltage drop at its V _gs . The top cell 97 in the series cell chain 88 experiences 15 voltage drops in the source voltage. Since the cell current is a function of (V _gs −V _t ) ² , if V _t (ie, threshold voltage) is the same, the source voltage difference is squared to reflect the change in cell current.

Relationship between the temperature and the threshold voltage or V _t level is a function of the position of the cell in the chain of the cell strings or memory cell. The variation in threshold voltage or Vt level is not only a function of temperature, but also varies with the position of the cell in the cell string over temperature variations.

Since the current characteristics of the flash cell change with temperature, this temperature change reduces the margin available to distinguish between programmed and unprogrammed flash cells. The threshold voltage, or V _t level, is also a function of the cell position in the string of memory cells, so the word line voltage depends on the temperature, the characteristics of the flash cell and the position of the flash cell in the cell string. There is a need to generate a word line voltage to increase the margin by modification.

  A method and apparatus for generating a word line voltage is provided. In one embodiment of the present invention, the word line voltage generator is a current source coupled to a current summing node, the cell changing with the position of the memory cell in the string of interconnected bit cells. A first current source configured to generate a first current having a position dependent temperature coefficient is provided. The word line voltage generator also includes an adjustable current source configured to generate a second current substantially independent of temperature changes, and a voltage converter that generates a word line voltage proportional to the first current. I have.

  In another embodiment of the present invention, the method generates a first current having a cell location dependent temperature coefficient that varies with the location of the memory cell in the string of interconnected bit cells. A second current is also generated, which is substantially independent of the temperature change. The first current and the second current are combined to generate a reference current, which is converted to a word line voltage by flowing through a voltage converter.

  Another embodiment comprises a word line voltage generator, a semiconductor wafer including a device having a word line voltage generator, and an electronic system including a memory device having a word line voltage generator as described herein.

  Some of the circuits in this description include a well-known circuit configuration known as a diode-connected transistor. A diode connected transistor is formed when connecting the gate and drain of a complementary metal oxide semiconductor (CMOS) transistor or when connecting the base and collector of a bipolar transistor. When connected in this way, the transistor operates with the same voltage and current characteristics as a pn junction diode. Thus, the circuit elements shown as diodes in the figure can be any device that creates a pn junction with diode characteristics, such as a conventional diode, a bipolar transistor connected in a diode configuration, a CMOS connected in a diode configuration. It can be realized in the device. Also, appropriate devices having diode characteristics will be referred to as diodes, pn junction elements, diode-connected CMOS transistors, and diode-connected bipolar transistors.

  In this description, the nonvolatile memory is referred to as an electrically erasable programmable memory (EEPROM) cell, a flash EEPROM cell, and a flash cell. As will be appreciated, embodiments of the invention may be implemented with any of these non-volatile memory cells.

  In many embodiments, the present invention is intended to extend the margin by modifying the word line voltage depending on temperature, flash cell characteristics, and flash cell string or flash cell position in the series chain. Includes circuits and methods. FIG. 6 illustrates the verification margin extended by varying the read word line voltage Vwl_r for different temperatures and different locations of the flash cells in the string of flash cells or series chain. Similar to FIG. 4, curve 25L shows a flash cell programmed at low temperature and curve 25H shows a flash cell read at high temperature. Vwl_v (LT) indicates the highest voltage at which the flash cell is verified at a low temperature, and similarly Vwl_v (HT) indicates the maximum voltage at which the flash cell is verified at a high temperature. Vwl_r is the read word line voltage when no compensation is attempted to match the current characteristics of the flash cell or to compensate for the current temperature. Similar to FIG. 4, a relatively small verification margin is shown as an “uncompensated verification margin” between Vwl_r and Vwl_v (HT). However, if the word line voltage to be read is corrected, the verification margin can be widened. Vwl_r (HT) indicates the modified voltage for the read process during the high temperature period. By lowering the word line voltage during the read process, the verification margin is widened as indicated by the “compensated verification margin” as the difference between Vwl_v (HT) and Vwl_r (HT).

  Another way to indicate the programmed value for the flash cell is the probability distribution of the flash cell threshold voltage versus the word line voltage. FIG. 7 shows a bi-level flash cell distribution with the flash cells in two states (ie, a programmed state and an unprogrammed state). Line 60L shows the Vth distribution for an unprogrammed flash cell at low temperature, and line 60H shows the Vth distribution for an unprogrammed flash cell at high temperature. Similarly, line 62L shows the Vth distribution for a programmed flash cell at low temperature, and line 62H shows the Vth distribution for a programmed flash cell at high temperature. Line 68 shows the voltage level used during the read period to distinguish between programmed and unprogrammed flash cells. FIG. 7 shows the programmed state as binary ones and the unprogrammed state as binary zeros. However, as those skilled in the art will recognize, this is an arbitrary definition and may be defined in reverse.

  The flash cell may be multi-level and the flash cell may be programmed with multiple Vth levels to indicate more than two binary states. FIG. 8 shows a four level flash cell. The Vth distribution for flash cells programmed to the “11” state at low temperature is shown by line 70L, and the Vth distribution for flash cells programmed to the “11” state at high temperature is shown by line 70H. Similarly, the Vth distribution for a flash cell programmed to a “10” state at low temperature is represented by line 72L, and the Vth distribution for a flash cell programmed to a “10” state at high temperature is represented by line 72H. The Vth distribution for a flash cell programmed to a “00” state at low temperature is shown by line 74L, and the Vth distribution for a flash cell programmed to a “00” state at high temperature is shown by line 74H. Finally, the Vth distribution for the flash cell programmed to the “01” state at low temperature is shown by line 76L, and the Vth distribution for the flash cell programmed to the “01” state at high temperature is shown by line 76H. Lines 82, 84 and 86 show the voltage levels used during the readout period to distinguish between the four programmed states. FIG. 8 shows possible assignments for binary values representing four different distributions. However, as those skilled in the art will appreciate, this state definition can be defined by other binary combinations. Furthermore, as those skilled in the art will appreciate, many states other than 2 or 4 fall within the scope of the present invention.

  FIG. 9 is a circuit model of the word line voltage generator 100 including the first current source 110, the adjustable current source 120 and the voltage converter 140. The first current source 110 is coupled to the current summing node 150 and is configured to generate a first current (It). The voltage derived from the first current includes a temperature coefficient substantially equal to the temperature coefficient of the threshold voltage of the flash cell. In other words, if only the first current source 110 is coupled to the voltage converter 140, the first current source 110 has a voltage drop across the voltage converter 140 substantially equal to the temperature coefficient of the flash cell threshold voltage. Configured to be equal. In other words, dVwl / dT = d (R * It) / dT to dVt_cell / dT. However, R is the resistance value of the voltage converter 140, and Vt_cell is the threshold voltage of the flash cell.

  Adjustable current source 120 is coupled to current summing node 150 and is configured to generate a second current (Ich) that is substantially independent of temperature changes. The first current source 110 and the adjustable current source 120 are combined to cause the current summing node 150 to generate a reference current. The voltage converter 140 is configured to create an IR drop that is proportional to the current at the current summing node 150 by reducing the reference current in a converter element, such as a resistive element.

  The first current source 110 adapts and modifies the amount of current supplied to the current summing node 150 depending on the temperature and flash cell characteristics. That is, a change in current from the first current source 110 causes a change in voltage on the word line. In other words, It is a function of temperature in a manner related to Vt_cell being a function of temperature (ie, It = f (T)).

  The adjustable current source 120 has a charging current (Ith) that can be adjusted to have a first current source current during a verification operation period and a second current source current during a read operation period (this is also called a second current). Generate. In other words, Ich = A * Ic during the verification operation period, and Ich = B * Ic during the read operation period. Further, the adjustable current source 120 is configured to be substantially independent of temperature changes so as not to distort the total sum current due to the temperature difference between the read operation and the verify operation.

  Therefore, the resulting current at current summing node 150 is Isum = It + Ich, that is, Isum = f (T) + A * Ic during the verify operation period and Isum = f (T) + B * Ic during the read operation period. With this configuration, it is possible to generate a word line voltage that is configured to adapt to temperature changes in the same way that the flash cell adapts during the read and verify operations. Also, the values of A and B generate a plurality of voltages for the word lines coupled to the multi-level flash cell, in addition to the difference between the read and verify operations at each of the multi-levels. Are selected to produce a plurality of summing currents suitable for

  FIG. 10 is a circuit model of a word line voltage generator 100 'including a first current source 110', an adjustable current source 120 ', an adjustable current sink 130' and a voltage converter 140 '. The first current source 110 'is similar to the first current source 110 of FIG. 9 by having a temperature coefficient substantially equal to the temperature coefficient of the flash cell.

  The adjustable current source 120 'generates a charging current (Ich) that can be adjusted to have a first current source current during the verify operation period and a second current source current during the read operation period. In other words, Ich = A * Ic during the verification operation period, and Ich = B * Ic during the read operation period. Further, the adjustable current source 120 'is configured to be substantially independent of temperature changes so as not to distort the total sum current due to the temperature difference between the read operation and the verify operation.

  As with the adjustable current source 120 ′, the adjustable current sink 130 ′ has a first sink current during the verify operation period and a discharge current (Idis) that can be adjusted to have the second sink current during the read operation period. (This is also called the third current). In other words, Idis = C * Id during the verification operation period, and Idis = D * Id during the read operation period. Further, the adjustable current sink 130 'is configured to be substantially independent of temperature changes so as not to distort the total sum current due to a temperature difference between the read operation and the verify operation.

  Therefore, the resulting current at current summing node 150 ′ is Isum = It + Ich + Idis, ie, Isum = f (T) + A * Ic + C * Id during the verify operation period and Isum = f (T) + B * Ic + D during the read operation period. * Id. With this configuration, it is possible to generate a word line voltage that is configured to adapt to temperature changes in the same way that the flash cell adapts during the read and verify operations.

  As a configuration example, the word line voltage generator 100 ′ of FIG. 10 may be configured with C = 0 during the verification operation period and B = 0 during the read operation period. In this configuration, during the verification period, the variable current source provides current to the current summing node 150 ', but the variable current sink is effectively off. Similarly, during the read operation period, the variable current source is effectively off and the variable current sink adds a sink current to the current summing node 150 '. Of course, as those skilled in the art will appreciate, many other combinations of coefficients A, B, C, D can be envisioned within the scope of the present invention. In addition, the values of A, B, C, and D may include a plurality of values for the word lines coupled to the multilevel flash cell, in addition to the difference between the read operation and the verify operation at each multilevel level. It is selected to produce a plurality of summing currents suitable for generating a voltage.

  FIG. 11 shows a word line voltage generator 100 ″ comprising a first current source 110 ″, an adjustable current source 120 ″, an adjustable current sink 130 ″ and a voltage converter 140 ″, a variable current controller 170 and a variable current selector 180. In operation, the word line voltage generator operates in a manner similar to the previously discussed embodiment of Figures 9 and 10. In the embodiment of Figure 11, the voltage converter 140 "is a current summing node. 150 ″ and ground can be implemented as a resistive element R. Further, the first current source 110 ″ can be a p-channel transistor with a source coupled to the power supply and a drain coupled to the current summing node 150 ″. The gate of the p-channel transistor Ps can be implemented as a transistor (Ps), and the matching current controller is controlled to control the amount of current flowing through Ps. 160 is coupled to a temperature compensated bias signal 165 generated by. This matching current controller 160 will be described in detail later.

  Variable current controller 170 and variable current selector 180 control adjustable current source 120 "and adjustable current sink 130". The variable current controller 170 will be described in detail later. The generated signal is coupled to the gates of p-channel transistors 1A, 2A, 4A and to the gates of n-channel transistors 1B, 2B, 4B. The p-channel transistors 1A, 2A, 4A are configured to have a binary weighted gate size so that the size of 2A is twice that of 1A and the size of 4A is twice that of 2A . The variable current selector 180 generates signals trm_1p, trm_2p, trm_4p, trm_1n, trm_2n, trm_4n. With this configuration, the variable current controller 170 can assert or negate trm_1p, trm_2p, trm_4p so that a weighted current can be applied to the current summing node 150 ″. For example, the p-channel transistor 1A has 10 μA. If so, p-channel transistor 2A is configured to supply 20 μA, p-channel transistor 4A is configured to supply 40 μA, and adjustable current source 120 ″ is configured to supply a current of 0-70 μA. However, it is not limited to this.

  Adjustable current sink 130 "operates similarly by controlling binary weighted n-channel transistors 1B, 2B, 4B. Needless to say, binary weighting is adjustable current source 120" and adjustable. One exemplary method for making the current sink 130 ". As those skilled in the art will appreciate, many other methods can be implemented within the scope of the present invention. In addition, binary weighting is , May be increased or decreased to modify the dynamic range of the selected element, for example, binary weighting is reduced to a selection of 0-3 or increased to a selection of 0-15, but is not limited to this is not.

  The variable current controller 170 finely adjusts the amount of current flowing through the p-channel transistors 1A, 2A, 4A by controlling the bias voltage at node 172 (vgp_c). Similarly, the amount of current flowing through n-channel transistors 1B, 2B, 4B is fine tuned by controlling the bias voltage at node 174 (vgn_c). Using this combination of fine adjustment and binary weighting, by combining each binary weighted current source from the variable current source, an overall second current Ich that is substantially independent of temperature changes is obtained. Can be made. Similarly, by combining each binary weighted current sink from the variable current sink using a combination of fine adjustment and binary weighting, an overall third current that is substantially independent of temperature changes. Idis can be made.

  12A-12G are circuit diagrams of various embodiments of the matching current controller 160 of FIG. 12A-12D have a matching current source 163 comprising p-channel transistors P1, P2 coupled in a current mirror configuration and n-channel transistors N1, N2 coupled in a current mirror configuration. This matching current source 163, as is well known for current summing mirror configurations, has a first current I1 through P1 and a second current I2 through P2, which have equal current if the transistors are matched to have the same size. And make.

  FIG. 12A shows a matching current controller 160 having a negative temperature coefficient. Resistive element R1 produces a predetermined voltage drop and creates a second current through N2. However, in a diode, the pn junction has a negative temperature coefficient, and the change in voltage drop at the pn junction is inversely proportional to the temperature change. In other words, the voltage drop at the pn junction decreases as the temperature increases. For example, in the case of silicon, the voltage drop at the pn junction is approximately -2.2 mV / ° C and is inversely proportional to the temperature change. Thus, diode D1 exhibits a diode voltage drop with a negative temperature coefficient. The matching current source operates to keep the currents I1, I2 substantially the same so that the temperature compensated bias signal 165 has a negative temperature coefficient related to the negative temperature coefficient of the diode D1.

FIG. 12B shows a matching current controller 160 having a positive temperature coefficient. The diodes D1 and D2 are configured to have a junction area of relative size such that the diode D1 has a junction area of relative size 1 and the diode D2 has a junction area N times the size of the diode D1. Two diodes of different sizes but the same emitter current will have different current densities, resulting in a slightly different voltage drop at the pn junction. When the temperature rises due to the negative temperature coefficient of the diode, the voltage drop of the diode D1 drops at a rate greater than the voltage drop of the diode D2. In general, this difference is called ΔV _be and represents the difference in voltage drop between the two diodes D1 and D2. Thus, the voltage drop across the first diode D1 is equal to the combination of the voltage drop across the second diode D2 and the voltage drop across the resistor R1. Therefore, to keep the first current I1 and the second current I2 substantially the same, the voltage drop (ΔV _be ) at the resistor R1 has a direct temperature correlation (ie, the voltage change increases with increasing temperature). To do). ΔV _be is also called a voltage that is absolute temperature proportional (PTAT). This is a voltage proportional to the temperature change, with a positive temperature coefficient substantially opposite to the negative temperature coefficient of diode D1, so that the temperature compensated bias signal 165 continues to be substantially temperature independent. Is adjusted.

FIG. 12C shows a matching current controller 160 with a temperature coefficient between the embodiment of FIG. 12A and the embodiment of FIG. 12B. In operation, the embodiment of FIG. 11C operates similarly to the embodiment of FIG. 11B. However, the embodiment of FIG. 11C has a resistance R2. As a result, the second current I2 is divided into a subcurrent I2a and a subcurrent I2b. The subcurrent I2a is directly related to the temperature change due to the aforementioned ΔV _be term. On the other hand, the secondary current I2b operates to increase the current I2, and as a result, the second current I2 has a positive temperature coefficient having an offset (Iptco). In this case, the secondary current I2a generates a positive temperature coefficient, and the secondary current I2b generates an offset. As a result, the temperature compensated bias signal 165 has a voltage directly related to Iptco. Select different resistance ratios between R1 and R2 for N1, N2 transistor sizes to modify temperature compensated bias signal 165 to different values while remaining substantially independent of temperature changes. May be.

  The embodiment of FIG. 12D is the same as the embodiment of FIG. 12C, but differs in that bypass transistors N3 and N4 are provided in resistors R1t and R2t, respectively. This configuration allows a fine adjustment capability to correct the voltage drop due to the subcurrent I2a flowing through R1 (and R1t). Similarly, the voltage drop due to the secondary current I2a flowing through R2 (and R2t) is corrected. Needless to say, this fine-tuning capability can be expanded to more than one selectable resistance.

  FIG. 12E illustrates a matching current controller 160 that uses the flash memory cell M1 to create the characteristics of the selected flash memory cell. The p-channel transistor P3 is connected in a diode configuration to create a current source. The flash memory cell M1 operates with current characteristics and temperature dependence similar to the current characteristics of the flash memory cells in the memory array. N-channel transistor N5 is controlled by bias voltage Vbias to further modify the current through p-channel transistor P3 and, as a result, modify the voltage output to temperature compensated bias signal 165.

  FIG. 12F shows a matching current controller 160 for creating the characteristics of the selected flash memory cell using the flash memory cell M2, similar to FIG. 12E. The p-channel transistor P3 is connected in a diode configuration to create a current source. The flash memory cell M2 operates with current characteristics and temperature dependence similar to the current characteristics of the flash memory cells in the memory array. However, in the embodiment of FIG. 12F, the control gate and floating gate of the flash memory cell are operatively coupled. With this arrangement, programmed flash cells can be made more accurately, eliminating the need to provide a mechanism for generating programming operations for flash memory cell M2. N-channel transistor N5 is controlled by bias voltage Vbias to further modify the current through p-channel transistor P3 and, as a result, modify temperature compensated bias signal 165.

  FIG. 12G shows a matching current controller 160 that uses n-channel transistor N6 to create the characteristics of the selected flash memory cell. The p-channel transistors are connected in a diode configuration to create a current source. N-channel transistor N6 operates with current characteristics and temperature dependence similar to those of flash memory cells in the memory array. N-channel transistor N5 is controlled by bias voltage Vbias to further modify the current through p-channel transistor P3 and, as a result, modify temperature compensated bias signal 165.

  FIG. 13 is a circuit diagram of a representative embodiment of the variable current controller 170 of FIG. p-channel transistors P3, P4, n-channel transistors N7, N8, diodes D3, D4 and resistors R3, R4 are positive temperature coefficient with offset (Iptco) in a manner similar to the matching current controller 160 of FIG. 12C. Works to make. The result is a node 172 (vgp_c) that is substantially independent of temperature variations, which creates a bias level for the p-channel transistor of the adjustable current source 120 ″ shown in FIG. Transistor P5 and n-channel transistor N9 are biased at node 174 (vgn_c) relative to node 172 (vgp_c) at an appropriate bias level relative to the n-channel transistor of adjustable current sink 130 ″ shown in FIG. Operates to generate a signal.

  As mentioned above, not only does temperature affect the verification margin by changing the current flowing through the individual memory cells, but the current flowing through the memory cells is also affected by the location of the memory cells in the string or chain of memory cells. Is done. While the cell position in the flash memory cell series chain dominates the threshold voltage of the memory cell, temperature changes also cause changes in the current flowing through the memory cell series chain.

14A shows an equivalent circuit of the memory cell_0 98, and FIG. 14B shows an equivalent circuit of the memory cell_1597. As described with reference to FIG. 5, a NAND flash array consists of an array of floating gate cells arranged in a string or cell chain, each floating gate cell being drained in a series cell chain 88 '. And the source is combined. In operation, the word lines (WL_0-WL_15) select individual floating gate memory cells in the series cell chain to be written or read and the remaining floating gate memory in each series cell chain. • Operate the cell in pass-through mode. For example, FIG. 14A shows an equivalent circuit when cell_0 98 is selected and each other cell is configured in pass mode. As shown, the upper resistance of cell_0 98 is identified as R _d0 and is equivalent to the sum of the resistances in the chain of cells. Specifically, R _d0 = R _SGD + R _CELL-15 + R _CELL-14 +... + R _CELL-1 and R _s0 = R _SGS . Here, R _SGD is the resistance of the drain selection gate, and R _SGS is the resistance of the source selection gate. Similarly, FIG. 14B shows an equivalent circuit when cell — 1597 is selected and each other cell is configured in pass mode. As illustrated, the upper resistance of the cell _15 97 is identified as R _s15, it is equivalent to the sum of the resistances in the chain of cells. Specifically, R _s15 = R _SGS + R _CELL-14 + R _CELL-13 +... + R _CELL-0 , and R _d15 = R _SGD .

  Obviously, to read one memory cell, current must flow through the other memory cells in the series cell chain. Thus, the remaining cells have a parasitic resistance in series with the drain or source connection. Since the bottom cell_0 98 of series cell chain 88 is closest to the array ground, it experiences 15 voltage drops on the drain line and one voltage drop on the source line. The uppermost cell_0 97 of the series cell chain 88 experiences 15 voltage drops on the source line and 1 voltage drop on the drain line.

FIG. 15 is a graph showing typical currents flowing through the memory cells when activated by the word line voltage Vwl, plotted at high and low temperatures. As shown, the graphs of the high temperature (HT) and low temperature (LT) currents on the logarithmic scale do not match each other and the programmed flash cell current Icell having the first threshold current Ith1 and the second threshold current Ith2 is Create an area identified to have. As is apparent from the graph, there is a position-dependent temperature coefficient that varies with the position of the cells in the string or chain of interconnected flash memory cells. The temperature dependence of the first threshold current Ith1 results in R _s0 (HT)> R _s0 (LT) and R _s15 (HT)> R _s15 (LT), and the temperature dependence of Vt due to the temperature dependence of Rs is | DVt0 / dT | <| dVt15 / dT |. The temperature dependence of the second threshold current Ith2 results in R _s0 (HT) <R _s0 (LT) and R _s15 (HT) <R _s15 (LT), and the temperature dependence of Vt due to the temperature dependence of Rs is | DVt0 / dT | <| dVt15 / dT |.

  FIG. 16A shows the first threshold current for cell locations across a typical string or chain of 16 memory cells, and FIG. 16B illustrates the string or chain of a typical 16 memory cell. The second threshold current for the cell positions at both ends is shown. As shown, cell positions in a string or chain of memory cells indicate temperature variations. For example, in the case of the second threshold current Ith2 in FIG. 16B, since the cell_15 is closer to the bit line than the cell_0, the cell_15 has a lower source voltage than the cell_0. Therefore, the source voltage of the cell_15 decreases as the temperature increases. This is because the cell current is decreased and Vt_cell is increased according to the temperature, resulting in the temperature dependence shown in FIG. 16B. Thus, temperature compensation related to the location of memory cells in a string or chain of memory cells further contributes to an increased verification margin for temperature variations.

  FIG. 17 illustrates a word line voltage generator 100 having a first current source 110 ′ ″, an adjustable current source 120 ″, an adjustable current sink 130 ″, a voltage converter 140 ″, a variable current controller 170, and a variable current selector 180. In operation, the word line voltage generator operates in the same manner as in the embodiment of FIGS. 9 to 11 described above, but in the embodiment of FIG. '' 'Comprises a word line adjustable current source 310 coupled to a current summing node 150' ''.

  Variable current controller 170 and variable current selector 180 control adjustable current source 120 "and adjustable current sink 130". The generated signal is coupled to the gates of p-channel transistors 1A, 2A, 4A and n-channel transistors 1B, 2B, 4B, respectively. The p-channel transistors 1A, 2A, 4A are configured to have a binary weighted gate size such that 2A is twice the size of 1A and 4A is twice the size of 2A. The The variable current selector 180 generates signals trm_1p, trm_2p, trm_4p, trm_1n, trm_2n, trm_4n. With this configuration, the variable current controller 170 can assert or negate trm_1p, trm_2p, trm_4p to allow weighted current to the current summing node 150 "". For example, when p-channel transistor 1A is configured to supply 10 μA, p-channel transistor 2A is configured to supply 20 μA, and p-channel transistor 4A is configured to supply 40 μA, an adjustable current source 120 ″ is configured to supply a current of 0 to 70 μA, but is not limited thereto.

  The adjustable current sink 130 "operates similarly by controlling the binary weighted transistors 1B, 2B, 4B. Of course, the binary weighting is adjustable current source 120" and adjustable current sink 130. Is one exemplary method for producing ". As those skilled in the art will appreciate, many other methods can be implemented within the scope of the present invention. In addition, binary weighting is selected. It can be increased or decreased to modify the current dynamic range, for example, binary weighting can be reduced for selections of 0-3 and increased for 0-15, It is not limited to.

  The variable current controller 170 fine tunes the amount of current flowing through the p-channel transistors 1A, 2A, 4A by controlling the bias voltage at node 172 (vgp_c). Similarly, the amount of current flowing through n-channel transistors 1B, 2B, 4B is fine tuned by controlling the bias voltage at node 174 (vgn_c). By using this combination of fine adjustment and variable weighting, by combining each weighted current source from the variable current source, an overall second current Ich that is substantially independent of temperature changes can be created. . Similarly, using a combination of fine tuning and variable weighting to create a comprehensive third current Idis that is substantially independent of temperature changes by combining each weighted current source from the variable current source. Can do.

  The first current source 110 ″ ″ is configured to include a matching controller 160 for controlling the amount of current flowing through the word line adjustable current source 310. Matching controller 160 generates temperature compensated bias signal 165 to control the current through word line adjustable current source 310 as described above. The matching controller 160 and the word line current selector 320 control the word line adjustable current source 310. Temperature compensated bias signal 165 from matching controller 160 is coupled to the gates of p-channel transistors 1A, 2A, 4A. p-channel transistors 1A, 2A, 4A are configured to have a gate weight that is binary weighted so that 2A is twice the size of 1A and 4A is twice the size of 2A . The word line current selector 320 generates signals trmt_1b, trmt_2b, and trmt_4b. With this configuration, the word line current selector 320 can assert or negate trmt_1b, trmt_2b, trmt_4b so that a weighted current can be applied to the current summing node 150 ″ according to the word line address.

  FIG. 18 shows the logic of the word line current selector 320 according to an embodiment of the present invention. For example, the word line current selector 320 is illustrated for a typical 16 word line string or chain of memory cells, but is not so limited. As is well known, the quantity of 16 word lines is uniquely addressed using 4 binary address lines (RA3, RA2, RA1, RA0). In this embodiment, the signals trmt_1b, trmt_2b, trmt_4b for controlling the word line adjustable current source 310 of FIG. 17 are input to a binary adder that uses carry addition to add 0, 0, RA3. The constant base values trmt_1b_base = 1, trmt_2b_base = 1, and trmt_4b_base = 0. The added output from the binary adder generates a control signal. When RA3 = 0, trmt_1b = 1, trmt_2b = 1, trmt_4b = 0, and when RA3 = 1, trmt_1b = 0, trmt_2b = 0, trmt_4b = 1.

  FIG. 19 illustrates the logic of the word line current selector 320 according to another embodiment of the invention. Using a similar example, the word line current selector 320 is illustrated for a typical 16 word line string or chain of memory cells, where as many as 16 word lines are 4 binary address lines (RA3, RA2,. (RA1, RA0) are uniquely addressed. In this embodiment, the signals trmt_1b, trmt_2b, trmt_4b for controlling the word line adjustable current source 310 of FIG. 17 are input to a binary adder using carry addition that adds 0, RA3, RA2. Constant base values trmt_1b_base = 1, trmt_2b_base = 1, trmt_4b_base = 0. The added output from the binary adder produces the control signals shown in the truth table of FIG.

  FIG. 20 is a block diagram of a representative embodiment of a flash memory comprising a word line voltage generator 100 according to one embodiment of the present invention. The flash memory includes an array 210 of flash memory cells, a row decoder 220 that selects an appropriate word line based on an address input, and a column decoder 225. The selected column is sent to the sense amplifier block 230 for reading. In addition, sense amplifier block 230 is used to apply appropriate voltages to the source of the flash cell, the drain of the flash cell, or both during programming and erasing. The interface block 235 includes a circuit for interfacing data input and data output between the external circuit and the sense amplifier block 230. Controller 240 and command buffer 245 control various operations within the flash memory and commands received from external circuitry. The address buffer 250 temporarily stores an address between the external circuit and the row decoder 220 and the column decoder 225. Depending on the architecture of memory array 210, address buffer 250 sends a portion of the address to row decoder 220 and column decoder 225.

  Switch 290 selects an appropriate one of the word lines according to the current operation mode. The Vwl generator 100 generates a word line voltage for a read operation and a verify operation according to an embodiment of the present invention. Vpgm generator 262 generates word line voltages for programming operations.

  As shown in FIG. 21, a semiconductor wafer 400 includes a plurality of semiconductor memories 300 in accordance with the present invention, each semiconductor memory 300 incorporating at least one embodiment of word line voltage generation or a method described herein. Yes. It will be appreciated that the semiconductor memory 300 may be a substrate other than a silicon wafer, such as a silicon on insulator (SOI) substrate, a silicon on glass (SOG) substrate, or a silicon on sapphire (SOS). Can be made on a substrate.

  As shown in FIG. 22, in accordance with the present invention, electronic system 500 includes an input device 510, an output device 520, a processor 530, and a memory device 540. Memory device 540 includes at least one semiconductor memory 300 'that incorporates into memory device 540 at least one embodiment of word line voltage generation or a method described herein.

  Although the present invention has been described in terms of a preferred embodiment, the present invention is not limited to the embodiments, as those skilled in the art will recognize and understand. Rather, many additions, deletions, and modifications may be made to the preferred embodiment without departing from the scope of the claimed invention. Furthermore, the features of one embodiment can be combined with the features of another embodiment in a manner that is within the scope of the invention contemplated by the inventors.

FIG. 3 is a circuit diagram of a flash memory cell. 2 is a graphical representation of various currents in a flash memory cell. 4 is a graphical representation of verification margin in a flash memory cell. FIG. 6 is a graphical representation of reduced verification margin in a flash memory cell. A simplified diagram of a portion of a flash memory array shows a serial chain of flash memory cells. FIG. 6 is a graphical representation of a compensated verification margin in a flash memory cell. Figure 6 is a threshold voltage distribution graph for a dual level flash memory cell. 6 is a threshold voltage distribution graph for a multi-level flash memory cell. It is a circuit model of typical embodiment of the present invention. It is a circuit model of other typical embodiments of the present invention. It is a circuit diagram of other typical embodiment of the present invention. FIG. 6 is a circuit diagram of various embodiments of a matching current controller. FIG. 6 is a circuit diagram of various embodiments of a matching current controller. FIG. 6 is a circuit diagram of various embodiments of a matching current controller. FIG. 6 is a circuit diagram of various embodiments of a matching current controller. FIG. 6 is a circuit diagram of various embodiments of a matching current controller. FIG. 6 is a circuit diagram of various embodiments of a matching current controller. FIG. 6 is a circuit diagram of various embodiments of a matching current controller. 1 is a circuit diagram of a variable current controller according to a representative embodiment of the present invention. FIG. 3 shows an equivalent circuit of various memory cells in a string or chain of memory cells. FIG. 3 shows an equivalent circuit of various memory cells in a string or chain of memory cells. It is a graph which shows the temperature dependence of a cell transistor. Figure 7 is a graph showing the temperature dependence of various cells in a string or chain of memory cells. Figure 7 is a graph showing the temperature dependence of various cells in a string or chain of memory cells. FIG. 4 is a circuit diagram of various current selectors responsive to row address positions in a string or chain of memory cells, according to an exemplary embodiment of the present invention. It is a figure which shows the logic of the word line current selector 320 concerning embodiment of this invention. It is a figure which shows the logic of the word line current selector 320 concerning other embodiment of this invention. 1 is a block diagram of a flash memory including a word line voltage generator according to an exemplary embodiment of the present invention. 1 is a semiconductor wafer including a plurality of semiconductor devices including a word line voltage generator according to a representative embodiment of the present invention. 1 is a calculation system diagram showing a plurality of semiconductor memories including a word line voltage generator according to a representative embodiment of the present invention. FIG.

Claims (29)

A word line voltage generator,
A current source coupled to a current summing node and configured to generate a first current, wherein the voltage derived from the first current, together with the position of the memory cell in the string of interconnected bit cells A first current source that at least partially includes a varying cell location dependent temperature coefficient;
An adjustable current source coupled to the current summing node and configured to generate a second current substantially independent of temperature changes;
A voltage converter coupled to the current summing node for generating a word line signal having a word line voltage proportional to the first current;
A word line voltage generator comprising:   The word line voltage generator of claim 1, wherein the first current of the first current source further has a temperature coefficient substantially equal to a temperature coefficient of a threshold voltage of at least one bit cell.   A plurality of current sources configured to generate the first current at a plurality of different current source levels in response to at least a portion of a location of a memory cell in a string of interconnected bit cells; The word line voltage generator of claim 1, comprising a current source generator.   The word line voltage generator of claim 1, wherein the cell location dependent temperature coefficient is determined from a most significant address bit of a memory cell location in a string of interconnected bit cells.   The word line voltage generator of claim 1, wherein the cell location dependent temperature coefficient is determined from a plurality of address bits of memory cell locations in a string of interconnected bit cells.   4. The plurality of current source generators are configured to generate the first current at the plurality of different current source levels in response at least in part to a temperature compensated bias signal from a matching current controller. The word line voltage generator described in 1. The matching current controller is
A matched current source that generates a first current signal and a second current signal that is substantially equal to the current current and that is related to the temperature compensated bias signal;
A first pn junction element coupled between the first current signal and ground;
A first resistive element coupled between the second current signal and ground;
The word line voltage generator according to claim 6. The matching current controller is
A matched current source that generates a first current signal and a second current signal that is substantially equal to the current current and that is related to the temperature compensated bias signal;
A first pn junction element coupled between the first current signal and ground;
A first resistance element and a second pn junction element coupled in series between the second current signal and ground;
The word line voltage generator according to claim 6. The matching current controller is
A matched current source that generates a first current signal and a second current signal that is substantially equal to the current current and that is related to the temperature compensated bias signal;
A first pn junction element coupled between the first current signal and ground;
A first resistance element and a second pn junction element coupled in series between the second current signal and ground;
A second resistive element coupled between the second current signal and ground;
The word line voltage generator according to claim 6.   The word line voltage generator according to claim 9, wherein the first resistance element and the second resistance element are configured to be selectively variable.   The word line voltage generator of claim 6, wherein the matching current controller generates the temperature compensated bias signal from a biased current flowing through substantially the same flash cell as at least one bit cell.   The word line voltage generator of claim 1, wherein the adjustable current source is configured to generate a first current source current during a verification process and a second current source current during a read process.   The word line voltage generator of claim 1, wherein the adjustable current source comprises a plurality of current source generators configured to generate the second current source current at a plurality of different current source levels.   The level of one of the plurality of different current source levels is generated during a verification process period and the other level of the plurality of different current source levels is generated during a read process period. Word line voltage generator. The at least one bit cell is at least one multi-level bit cell;
At least one level of the plurality of different current source levels is generated for a first voltage level of the at least one multi-level bit cell;
Another level of at least one of the plurality of different current source levels is generated for an additional voltage level of the at least one multi-level bit cell;
The word line voltage generator according to claim 13.   The word line voltage generator of claim 1, further comprising an adjustable current sink coupled to the current summing node and configured to sink a third current substantially independent of temperature changes. Generating a first current and deriving from the first current a voltage that at least partially includes a cell location dependent temperature coefficient that varies with the location of the memory cell in the string of interconnected bit cells;
Generating a second current substantially independent of the temperature change;
Combining the first current and the second current to generate a reference current;
Converting the reference current to a word line voltage by passing the reference current through a voltage converter;
A method comprising:   The step of generating a first current generates the first current, from which a voltage further including a temperature coefficient substantially equal to the temperature coefficient of the threshold voltage of the interconnected bit cells is derived. 18. The method of claim 17, comprising the step of:   The method of claim 17, wherein generating the first current comprises generating a plurality of first currents at least partially in response to a location of a memory in a string of interconnected bit cells. .   20. The method of claim 19, wherein the plurality of first currents are determined from a most significant address bit of a memory location in a string of interconnected bit cells.   20. The method of claim 19, wherein the step of generating a plurality of first currents is determined from a plurality of address bits at a memory location in a string of interconnected bit cells. Said step of generating a second current comprises:
Generating a first current source current during the verification process;
Generating a second current source current during a read process;
The method of claim 17, comprising: Generating a third current generated from the adjustable current sink and substantially independent of temperature changes;
Combining the third current with the first current and the second current to generate the reference current;
The method of claim 17, further comprising: A semiconductor memory comprising at least one word line voltage generator,
A current source coupled to a current summing node and configured to generate a first current, wherein the voltage derived from the first current, together with the position of the memory cell in the string of interconnected bit cells A first current source that at least partially includes a varying cell location dependent temperature coefficient;
A voltage converter coupled to the current summing node and configured to generate a word line signal having a word line voltage proportional to the first current;
A semiconductor memory comprising:   A plurality of current sources configured to generate the first current at a plurality of different current source levels in response to at least a portion of a location of a memory cell in a string of interconnected bit cells; 25. The semiconductor memory of claim 24, comprising a current source generator.   25. The semiconductor memory of claim 24, wherein the cell location dependent temperature coefficient is determined from a most significant address bit of a memory cell location in a string of interconnected bit cells.   25. The semiconductor memory of claim 24, wherein the cell location dependent temperature coefficient is determined from a plurality of address bits of memory cell locations in a string of interconnected bit cells. A semiconductor wafer,
Comprising at least one semiconductor device having at least one word line voltage generator;
The word line voltage generator is
A current source coupled to a current summing node and configured to generate a first current, wherein the voltage derived from the first current, together with the position of the memory cell in the string of interconnected bit cells A first current source that at least partially includes a varying cell location dependent temperature coefficient;
A voltage converter coupled to the current summing node and configured to generate a word line signal having a word line voltage proportional to the first current;
A semiconductor wafer comprising: An electronic system,
At least one input device;
At least one output device;
A processor;
At least one memory device having at least one word line voltage generator, the word line voltage generator comprising:
A current source coupled to a current summing node and configured to generate a first current, wherein the voltage derived from the first current, together with the position of the memory cell in the string of interconnected bit cells A first current source including at least partially a varying cell location dependent temperature coefficient;
A voltage converter coupled to the current summing node and configured to generate a word line signal having a word line voltage proportional to the first current;
A memory device comprising:
An electronic system comprising:

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