JPH10320921A - Circuit and method for detecting synchronous pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit and a method for detecting a synchronous pattern, whereby the synchronous pattern can be detected and protected with high reliability with the use of an independent clock. SOLUTION: A natural time interval of synchronous patterns generated at a frame counter 16 on the basis of a reference clock is compared by a comparator 17 with an estimated value of an estimated value holding part 15. A detection window generating part 18 generates a detection window with a timing corresponding to the obtained comparison result. A synchronous processing part 13 updates, depending on whether or not the synchronous pattern is detected within a time period of the detection window, the estimated value held in the holding part 15 to a value obtained by adding a difference value of an actually measured time interval of the synchronous pattern from an output of a synchronous pattern detecting part 12 and the estimated value. Accordingly, the synchronous pattern can be detected with the use of the stable reference clock and the detection window can be a short period because of the updating of the estimated value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous pattern detecting circuit and a synchronous pattern detecting method. The present invention relates to a synchronous pattern detection circuit and a synchronous pattern detection method.

[0002]

2. Description of the Related Art Generally, when data is recorded on a physical medium, the data is digitally modulated so as to conform to the characteristics of the medium, and the data is serially recorded as a data bit string. Since the digital modulation is performed using a block code, the bit string is composed of a continuous number of codewords having a fixed number or a natural number times the fixed number of bits. In a medium reproducing system, it is necessary to correctly detect a codeword boundary in order to correctly demodulate a bit string. For this purpose, synchronization patterns are inserted into the bit string at regular intervals. In other words, the reproduction system detects the synchronization pattern and performs digital demodulation processing on the subsequent bit sequence for every fixed number of bits. The interval between the synchronization patterns differs according to the characteristics of the medium. For example, in the case of an optical disk, a synchronization pattern of several tens of bits is inserted for every data of about 1000 bits. The synchronization pattern and the data bit string immediately before the next synchronization pattern are collectively called a frame.

In detecting a synchronization pattern, a detection window is often set. As shown in FIG. 6A, a data pattern in which the synchronization pattern 1 is inserted into the data bit sequence 2 at regular intervals is received as an input,
When the synchronization pattern 1 is detected, the timing is predicted by predicting the timing at which the next synchronization pattern 1 appears, and by generating a detection window signal as shown in FIG. You. The purpose of this is to eliminate the possibility that a synchronization pattern appears accidentally in a data bit string or the possibility that a reproduced bit string contains a bit error, resulting in a false detection of a synchronization pattern.

In some cases, the synchronization pattern itself includes a bit error. In this case, the synchronization pattern cannot be detected even within the detection window. Therefore, assuming that pattern detection has been performed at the end of the detection window, prediction of the pattern interval and setting of the detection window are continued. This operation is called synchronization protection. If the detection within the detection window fails continuously more than the predetermined number of times, it is determined that synchronization has been lost, and the detection window is reset and the resynchronization is performed based on the detected synchronization pattern only after the setting of the detection window is released. It has also been done.

[0005]

By the way, a phase-locked loop (PL) is usually provided before the synchronous pattern detection circuit.
An L: Phase Locked Loop) circuit is provided, and a bit clock can be used to determine a bit boundary of a reproduced bit string. Since the number of bits in a recorded frame is constant, a method of counting a bit clock by the number of bits in a frame is mainly used in order to predict the timing at which the next synchronization pattern appears. When this method is used, the stability of the PLL circuit may become a problem.

That is, when the PLL circuit becomes unstable due to a defect on the medium, the synchronization protection may not be performed correctly. As an example, a case where the bit clock is out of synchronization on the higher frequency side in a defective section will be described.
As shown in FIG. 7A, a defect 3
Exists, the counter for prediction operates earlier than the normal state in the section of the defect 3. Therefore, as shown in FIG. 7B, the timing for setting the detection window of the detection window signal is correct. It will be faster. At this time, although the synchronization pattern itself does not include an error, the pattern cannot be detected in the detection window, so that synchronization protection is performed at an incorrect timing.

As a prediction method for solving this problem, PL
It is known to use an independent constant frequency clock generation system without using a bit clock generated by an L circuit. In general, the bit rate (the number of bits read per unit time) that is continuously read from a medium is constant in a small section, so that the time to read one frame is considered to be equal between adjacent frames. That is, a stable prediction interval can be generated by an independent clock. Further, when the read bit rate is different at a different position beyond the above section on the medium, a voltage controlled oscillator (VCO) is used for the clock generation system, and the VCO is controlled by the position information on the medium to obtain an appropriate prediction interval. be able to.

However, the bit rate fluctuates even in the above-mentioned small section, which may cause a problem.
For example, in the case of an optical disk, if the center of the disk and the center of the spindle are fixed differently due to eccentricity of the optical disk, the angular velocity in one rotation is constant, but the reading radial position fluctuates. Fluctuates periodically. Therefore, the interval of the synchronization pattern also fluctuates periodically in accordance with this. When an independent clock is used, even in this situation, a long detection window corresponding to the maximum fluctuation width must be set in order to detect a synchronization pattern within the detection window. This goes against the original purpose of the detection window, which is to prevent erroneous detection of a synchronization pattern caused by a bit error.

[0009] The present invention has been made in view of the above points,
It is an object of the present invention to provide a synchronous pattern detection circuit and a synchronous pattern detection method capable of detecting and protecting a highly reliable synchronous pattern using an independent clock.

[0010]

In order to achieve the above object, a synchronous pattern detecting circuit according to the present invention is provided with a detecting means for receiving an input data bit sequence, detecting a synchronous pattern in the data bit sequence, and a reference clock. A generated reference clock generator, holding means for holding a predicted value of a time interval of the synchronization pattern, and timing according to a comparison result between the original time interval and the predicted value of the synchronization pattern generated based on the reference clock A detection window generating means for generating a detection window of a fixed period, a difference value between a time interval of a synchronization pattern actually measured by a detection signal from the detection means and a predicted value held in the holding means, and Is detected within the period of the detection window, and is held in the holding means based on the detection result and the difference value Synchronization processing means for determining whether or not to update the measured value, wherein the synchronization processing means outputs a synchronization establishment signal when a synchronization pattern is detected within the period of the detection window, and updates the predicted value. It is what it was.

According to the circuit of the present invention, a detection window is generated at a timing corresponding to a comparison result between the original time interval of the synchronization pattern generated based on the reference clock and the predicted value, and the synchronization pattern is generated within the period of the detection window. The stored predicted value is updated to a value obtained by adding a difference value between the time interval of the actually measured synchronization pattern and the predicted value according to whether or not the detected data is detected. The synchronization pattern can be detected using a stable reference clock without using a bit clock synchronized with the bit string, and the detection window can be shortened by updating the predicted value.

In particular, when there is a storage means for storing the above detection result and the difference value, and the prediction value held in the holding means is updated in consideration of the past history from this storage means. Can obtain a more accurate predicted value.

According to another aspect of the present invention, there is provided a synchronous pattern detecting method for predicting a time interval of a synchronous pattern when the synchronous pattern is detected in a standby state for detecting the synchronous pattern of an input data bit string. A value is set and held, and for a synchronization pattern detected thereafter, the synchronization pattern is determined based on a comparison result between the original time interval of the synchronization pattern generated based on the reference clock and the predicted value. Judgment whether or not it was detected within the detection window of the fixed period generated at the timing, and the result obtained by performing the prediction processing when the detection judgment was obtained and when the detection judgment was not obtained but less than the set period Based on the above, the prediction value is updated and the synchronization establishment signal is output, and the determination is performed again. When the detection determination is not obtained for the set period or more, the process returns to the synchronization pattern detection standby state. Those were Unishi.

Here, the prediction processing in the method of the present invention is as follows.
When the synchronization pattern is detected within the detection window, the difference between the actually measured synchronization pattern time interval based on the detected synchronization pattern and the held prediction value is added to the held prediction value. The updated value is updated as the next predicted value, and when the synchronization pattern is not detected within the period of the detection window, the predicted value held without updating is held as it is.

According to the method of the present invention, a detection window is generated at a timing corresponding to the result of comparison between the original time interval of the synchronization pattern generated based on the reference clock and the predicted value, and the synchronization pattern is generated within the period of the detection window. Since the prediction value is updated by performing the prediction processing according to whether or not the detected data pattern is detected, the synchronization pattern is not synchronized with the input data bit string but with a stable reference clock. Can be detected, and the detection window can be shortened by updating the prediction value.

[0016]

Next, an embodiment of the present invention will be described.

FIG. 1 is a block diagram showing an embodiment of a synchronous pattern detecting circuit according to the present invention. As shown in FIG. 1, this embodiment includes a reference clock generator 11, a synchronization pattern detection unit 12, a synchronization processing unit 13, a detection counter 1
4, a prediction value holding unit 15, a frame counter 16, a comparator 17, and a detection window generation unit 18.

The reference clock generator 11 is a circuit for generating a reference clock for each circuit block of the synchronous pattern detection circuit to operate synchronously. That is, all the time periods described later are represented by this reference clock number. The synchronization pattern detection unit 12 detects a synchronization pattern of a frame period from a bit string read from the medium 10 such as an optical disk, and sends a trigger signal for notifying the synchronization processing unit 13 of the detection.

The predicted value holding unit 15 holds a predicted value of the synchronization pattern interval, and receives information for updating the content from the synchronization processing unit 13. The frame counter 16 is incremented by the reference clock, and is reset to 0 by a trigger from the comparator 17 or a trigger from the synchronization processing unit 13.

The comparator 17 compares the predicted value of the synchronization pattern interval with the count value of the frame counter 16,
The trigger signal is output to the frame counter 16 and the detection window generator 18. Among these trigger signals, the output trigger signal to the frame counter 16 is generated with the same value of the predicted value of the synchronization pattern interval and the count value of the frame counter 16, while the output trigger signal to the detection window generator 18 is In order to make the center of the window coincide with the frame boundary, the signal is output by a half of the detection window period earlier than the trigger signal output to the frame counter 16.

The detection window generator 18 outputs a detection window signal of a fixed period as shown in FIG. 6B in response to a trigger signal from the comparator 17. This detection window period (FIG. 6A)
The high-level period is determined in consideration of the degree of bit rate fluctuation and the reference clock frequency. For example, if the detection window period is set to 9 reference clocks, the synchronization , And whether a synchronization pattern has been detected earlier or later than expected can be detected at each of the four levels.

The detection counter 14 holds the number of times the synchronization pattern has not been detected during the detection window period, and functions so that the synchronization processing unit 13 can reset to 0, increment, and refer to the value. When the value of the detection counter 14 exceeds a preset value in the synchronization processing unit 13, it is determined that the synchronization processing of the frame is not correctly performed, and the synchronization processing is also performed by detecting the synchronization pattern outside the detection window. This function is called a resynchronization function, which is a known technique and has no relation to the present invention.

This embodiment lies in a synchronization process executed by the synchronization processing unit 13. The synchronization processing unit 13 is realized here as a logic circuit configuring a state machine having three states. However, an arithmetic processing unit driven by software and performing the same processing can also be used as the synchronization processing unit 13.

Next, the operation of the synchronization processing which is a feature of this embodiment will be described in detail. FIG. 2 shows a state transition diagram of the synchronization processing unit 13. In the figure, a state A is an initial state (a synchronization pattern detection standby state), that is, a state in which synchronization processing is started, or a state after it is determined that resynchronization is necessary. When a synchronization pattern is detected in this state A, the state shifts to state B regardless of the setting of the detection window (transition 1).

State B is a state in which information for prediction has not been obtained yet, and the timing of the next detection window is determined using a predetermined value as a predicted value. In this state B, if no synchronization pattern is detected in the detection window, the process proceeds to state A (transition 2), and if detected, the process proceeds to state C (transition 3).

State C is a state in which synchronization has been established (transition 4). Here, if no synchronization pattern is detected within the detection window, the value of the detection counter is evaluated. If it is determined that resynchronization is necessary as the evaluation result, the state shifts to state A (transition 5).

Hereinafter, the processing in each state will be described in detail, but before that, some terms are defined for simplification of the description. “DET” represents an event in which a synchronization pattern is detected, and “WDET” represents an event in which a synchronization pattern is detected within a detection window. “WP” is a timing value at which the synchronization pattern within the detection window is detected. WP = 0 in the case of the center of the detection window, WP has a negative value if it is earlier than the center, and WP has a positive value if it is later. The unit is the number of reference clocks in the detection window. WP is obtained by the means for detecting a difference value according to the present invention.

Further, "NDC" is a count value of the detection counter 14, and "THNDC" is a predetermined value which is an upper limit value of the NDC. “INC” is the count value of the frame counter 16. The unit is the number of reference clocks. "T
"HINC" is a predicted value of the synchronization pattern interval held by the predicted value holding unit 15, and the unit is a reference clock number.
“PTHINC” is a set value set in THINC when there is no information for calculating a predicted value of the synchronization pattern interval. "DETF" is a prediction process for calculating THINC.

Next, the processing in each state will be described in detail.
First, in the state A, the synchronization processing unit 13 evaluates only an input from the synchronization pattern detection unit 12, and determines whether to shift to the state B according to the flowchart shown in FIG. That is, in FIG. 3, when the state is the state A (step 10).
1) It is monitored whether or not the trigger input from the synchronization pattern detection unit 12 is a DET indicating that a synchronization pattern has been detected (step 102). (Step 10
3).

In the state B, the synchronization processing unit 13 determines whether to shift to the state C or A according to the flowchart shown in FIG. That is, in FIG. 4, when the state is B (step 201), the count value INC of the frame counter 16 is initialized to 0 as an initialization step (step 202), and the predicted value THINC of the predicted value holding unit 15 is set to the default value PTHINC. (Step 203). It is desirable that the predetermined value PTHINC be a value corresponding to the most probable synchronization pattern period when there is a bit rate fluctuation.

Subsequently, it is determined whether or not an event WDET in which a synchronization pattern is detected in the detection window is established (step 204). If WDET is not established, the DE in state A is determined.
It returns to state A as T is not a correct detection (step 205). When WDET is established, it is determined that WDET is a likely detection, and a prediction process DETF described later is performed.
Is performed, and the prediction value THIN of the prediction value holding unit 15 is
C is updated (step 206). Thereafter, the synchronization processing unit 13 clears the count value NDC of the detection counter 14 to 0 (Step 207), outputs a synchronization establishment signal to the outside (Step 208), and transits to the state C (Step 20).
9).

In the state C, the synchronization processing unit 13 determines whether to shift to the state C or A according to the flowchart shown in FIG. That is, in FIG. 5, when the state is the state C (step 301), it is determined whether or not the event WDET in which the synchronization pattern is detected in the detection window is established (step 302). When the WDET is established, the state is determined. The same processing as when WDET of B is established is performed, and the state C is held.
That is, the synchronization processing unit 13 performs the prediction process DETF, updates the prediction value THINC of the prediction value holding unit 15 with the result (step 303), and then clears the count value NDC of the detection counter 14 to 0 (step 304). , And outputs a synchronization establishment signal to the outside (step 305), and holds the state C (step 306).

On the other hand, if WDET is not established, the count value NDC of the detection counter 14 is incremented (step 307). Therefore, this count value NDC
Indicates the number of times the synchronization pattern has not been detected during the detection window period. Subsequently, this count value NDC is equal to the upper limit value THN.
A comparison is made as to whether the difference is equal to or less than DC (step 308).
The upper limit value THNDC is the maximum number of consecutive synchronization protections.

When NDC ≦ THNDC, synchronization protection is performed. That is, a prediction process DETF described later is executed, and after updating the prediction value THINC of the prediction value holding unit 15 with the result (step 309), a synchronization establishment signal is output to the outside (step 305), and the state C is held. (Step 306). On the other hand, when NDC> THNDC, that is, when the count value NDC exceeds the upper limit value THNDC (when the synchronization pattern is not detected for a predetermined period related to THNDC), it is determined that correct synchronization processing is not performed. Then, since resynchronization is required, the state transits to the state A (step 310).

Next, the prediction processing DETF will be described. DETF is a process of determining a new predicted value THINC so that the next synchronization pattern detection is located at the center of the detection window as much as possible. DETF is the input to the last WD
The timing value WP indicating the difference between the ET determination result, the predicted value THINC, and the actually measured value is used. The output is the predicted value holding unit 1
5 is the predicted value THINC to be updated.

In this embodiment, the DETF is simply realized, and if WDET is established, the effective W
P exists, but only by this WP new prediction value T
HINC is determined. New predicted value THIN
C is given by the sum of the previous predicted value THINC and WP. If WDET is not established, the predicted value THI
NC does not update. That is, the prediction processing DETF is as shown in Table 1.
Update the predicted value THINC according to. In Table 1,
THINC on the left side is a value after updating, and THINC on the right side is a value before updating.

[0037]

[Table 1] The prediction process DETF is not limited to the above example, and the following example can be considered in a case where a finer tracking process is performed in response to a large bit rate fluctuation.

In this example, a memory for storing WDET establishment and WP is provided in the synchronization processing unit 13 and when the storage contents of these memories are QWDET and QWP, respectively, these are used for determining a new predicted value THINC. is there. That is, when the current WDET is established, the effective W
P exists, but when QWDET, which is the previous WDET, also holds, a new prediction value THINC is determined by adding the current QWP and the current WP to the prediction value before update, and the previous WDET is used in the previous WDET. If a certain QWDET does not hold, the new prediction value THINC is equal to the previous prediction value and W
Determined by the sum of P.

Even when the current WDET is not established, if the previous WDET, QWDET, is established, the new predicted value THINC is determined by adding the current QWP to the predicted value before updating, WDE last time and this time
If T does not hold, the predicted value THINC is not updated. To summarize the above, the predicted value THIN according to this example
The updating of C is performed according to Table 2. In Table 2, THINC on the left side is a value before updating, and THINC on the right side is a value before updating.

[0040]

[Table 2] By this processing, good tracking performance can be expected even when the increase or decrease of the bit rate changes sharply. In addition,
Although QWDET and QWP do not exist in the DETF in the state B, in this case, it is sufficient to treat QWDET as unsatisfied.

[0041]

As described above, according to the present invention,
A detection window is generated at a timing according to the comparison result between the original time interval of the synchronization pattern generated based on the reference clock and the predicted value, and the detection window is determined according to whether the synchronization pattern is detected within the period of the detection window. And the retained prediction value
By updating to the value obtained by adding the difference between the time interval of the actually measured synchronization pattern and the predicted value, the synchronization pattern can be updated using a stable reference clock without using a bit clock synchronized with the input data bit string. In addition to the detection, the detection window can be shortened by updating the prediction value, so that the synchronization pattern can be detected more accurately than in the past, and erroneous detection can be suppressed.

Further, according to the present invention, the prediction of the time interval of the synchronization pattern is performed by using the actual measurement or the history of the actual measurement. It is suitable to be applied to a reproduction system or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a state transition diagram of a synchronization processing unit in FIG. 1;

FIG. 3 is a processing flowchart in a state A of the synchronization processing unit in FIG. 1;

FIG. 4 is a processing flowchart in a state B of the synchronization processing unit in FIG. 1;

FIG. 5 is a processing flowchart in a state C of the synchronization processing unit in FIG. 1;

FIG. 6 is a diagram illustrating prediction of a pattern interval and setting of a detection window.

FIG. 7 is a diagram illustrating an example of a case where prediction of a pattern interval and setting of a detection window are incorrect.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Medium 11 Reference clock generator 12 Synchronization pattern detection part (detection means) 13 Synchronization processing part (synchronization processing means) 14 Detection counter 15 Predicted value holding part (holding means) 16 Frame counter (detection window generation means) 17 Comparator ( (Detection window generator) 18 Detection window generator (detection window generator)

Claims (6)

[Claims] 1. An input data bit sequence is inputted, a detecting means for detecting a synchronization pattern in the data bit sequence, a reference clock generator for generating a reference clock, and holding a predicted value of a time interval of the synchronization pattern. Holding means; detection window generating means for generating a detection window for a fixed period at a timing according to a comparison result between the original time interval of the synchronization pattern generated based on the reference clock and the predicted value; and the detection means The difference between the time interval of the synchronization pattern actually measured by the detection signal from and the predicted value held in the holding unit is obtained, and the synchronization pattern detected by the detection unit is within the period of the detection window. Detecting whether or not the predicted value held by the holding means is updated based on the detection result and the difference value. Processing means, wherein the synchronization processing means outputs a synchronization establishment signal when the synchronization pattern is detected within the period of the detection window, and updates the prediction value. Detection circuit. 2. When the synchronization pattern is detected within a period of the detection window, the synchronization processing unit calculates a value obtained by adding the difference value to a prediction value held in the holding unit for a next prediction. Performing an update held in the holding unit as a value, and when the synchronization pattern is not detected within the period of the detection window, holding the predicted value held in the holding unit as it is without updating. The synchronous pattern detection circuit according to claim 1. 3. A storage unit for storing a past detection result as to whether or not the synchronization pattern is detected within a period of the detection window and the past difference value, wherein the synchronization processing unit is configured to store the synchronization pattern. The previous detection result stored in indicates the detection of the synchronization pattern outside the detection window period, and the prediction value is updated only when the synchronization pattern is not detected within the detection window period this time. When the predicted value held in the holding unit is held as it is without performing, and any of the past detection result and the current detection result indicates the detection of the synchronization pattern within the period of the detection window. Updating a predicted value held in the holding unit using a difference value corresponding to the detection result among the past difference value and the difference value obtained this time stored in the storage unit. The synchronous pattern detection circuit according to claim 1, wherein: 4. The difference value is 0 when the synchronization pattern is detected at the center of the detection window, and is a negative value when the detection timing of the synchronization pattern is earlier than the center of the detection window. 4. The synchronization pattern detection circuit according to claim 1, wherein the detection value of the synchronization pattern is a positive value when the detection timing of the synchronization pattern is later than the center of the window. 5. When a synchronous pattern is detected in a standby state for detecting a synchronous pattern of an input data bit string, a predicted value of a time interval of the synchronous pattern is set and held,
For the synchronous pattern detected thereafter, a fixed period generated at a timing corresponding to the comparison result between the original time interval of the synchronous pattern generated based on the reference clock and the predicted value. The detection value is determined based on the result obtained by performing the prediction process when the detection determination is obtained and when the detection determination is not obtained and the time is less than the set period even if the detection determination is not obtained. And outputting the synchronization establishment signal and performing the determination again, and if the detection determination is not obtained for the set period or more, returns to the synchronization pattern detection standby state. 6. The prediction process, when the synchronization pattern is detected within the period of the detection window, the time interval of an actually measured synchronization pattern based on the detected synchronization pattern and the held prediction. A value obtained by adding the difference value to the held predicted value to the held predicted value is updated as the next predicted value, and when the synchronization pattern is not detected within the period of the detection window, the held pattern is not updated and is not stored. 6. The synchronous pattern detection method according to claim 5, wherein the process is a process of retaining the predicted value as it is.