JPH11266238A - Signal interruption-restoration detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the interrupt and restoration of supply, while considering the fluctuations of the period for signals such as clock signals having periodicity. SOLUTION: In this signal interruption/restoration detection circuit provided with an interrupt detection means 101 for detecting an interrupt state where the input of the signals of a monitoring object is stopped and a restoration detection means 102 for detecting the restoration point of time at which the input of the signals of the monitoring object is restored to be normal, the restoration detection means 102 is provided with a period discriminating means 111 for discriminating whether or not the period of the signals of the monitoring object is within a prescribed range corresponding to the input restart of the signals of the monitoring object, a holding means 112 for holding the discriminated results for the plural periods by the period discriminating means 111 as history information and a discriminating means 113 for discriminating whether or not the input state of the signals of the monitoring object has been completely restored, based on the history information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal disconnection / recovery detecting circuit for detecting disconnection and recovery of a monitored signal in a circuit which operates by receiving a periodic signal such as a clock signal. For example, in a transmission device or the like that operates in a synchronous transfer mode, various circuits operate in synchronization with a clock signal supplied from a network, and therefore, it is necessary to accurately detect disconnection and recovery of the clock signal.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration example of a conventional clock cut / recovery detection circuit. Also, FIG.
FIG. 4 is a timing chart illustrating the operation of the recovery detection circuit. In FIG. 7, a monostable multivibrator (hereinafter abbreviated as "monomulti") 401 is configured to be periodically retriggered by a change point of a clock signal.

Therefore, when a clock signal is normally supplied, as shown in FIG.
Is kept at logic "0". On the other hand, when the supply of the clock signal is interrupted, no re-triggering is performed within the time T1, which is the time constant of the monomulti 401, so that the output of the monomulti 401 is set to logic "1". The output of the flip-flop 402 shown in FIG. 7 becomes logic “1” (see FIGS. 8B and 8D), and is used as a clock disconnection detection signal indicating that the disconnection of the clock signal has been detected. Provided.

After that, as shown in FIG. 8A, when the supply of the clock signal is restarted, the above-mentioned mono-multi 401 is supplied.
Is reset to logic "0", and in response to this fall, the output of another monomulti 403 is set to logic "1", and the recovery detection operation is started.

In the clock disconnection / restoration detection circuit shown in FIG. 7, when the clock signal is supplied for a time T2 which is the time constant of the monomulti 403, it is determined that the supply of the clock signal is restored. Then, the mono-multi 403 is retriggered to reset its output to logic “0”, thereby resetting the flip-flop 402 and resetting the clock loss detection signal (FIGS. 8C and 8C). d)).

As described above, the time T2 is set as the recovery time from the restart of the supply of the clock signal, and after the recovery time has elapsed,
By adopting a configuration that detects recovery of the clock signal,
Although the supply of the clock signal is restarted, an incomplete period in which the cycle is unstable is eliminated. During a period in which the frequency of the clock signal is unstable, for example, when a slave-synchronized oscillator is used according to the source of the clock signal, the operation of adjusting the clock signal obtained from the signal from the oscillator to the phase of the host device Is performed, and after this period, a normal clock signal with a stable frequency is supplied.

Therefore, in the conventional clock disconnection / recovery detection circuit, the time constant of the monomulti 403 is considered in consideration of the time required for performing the above-described phase matching operation at the clock signal supply source. T2 needs to be determined.

[0008]

In the above-mentioned conventional clock disconnection / recovery detection circuit, although an unstable period when the supply of the clock signal is resumed is taken into consideration, a clock having an unstable frequency is considered. The period in which the signal is supplied and the period in which the clock signal is supplied at a normal frequency cannot be distinguished from each other, and cannot be used for detection of disconnection and recovery of the clock signal.

However, for example, in a clock transfer circuit provided in a transmission device in a synchronous transfer mode, it is an important issue whether or not the period of a clock signal supplied from the outside is stable. In addition, it is necessary to strictly distinguish the unstable period and the normal state as described above. The present invention provides a signal disconnection / detection method for detecting supply disconnection and restoration of a signal having periodicity such as a clock signal while considering fluctuations in the period.
It is an object to provide a recovery detection circuit.

[0010]

FIG. 1 is a block diagram showing the principle of the present invention. The invention according to claim 1 is a disconnection detecting means 101 for detecting a disconnection state in which input of a signal to be monitored is interrupted,
In a signal disconnection / recovery detection circuit including recovery recovery means 102 for detecting a recovery point at which the input of the signal to be monitored is recovered to normal, the recovery detection means 102 performs monitoring in response to resumption of input of the signal to be monitored. A period determining unit 111 for determining whether the period of the target signal is within a predetermined range; a holding unit 112 for holding determination results for a plurality of periods by the period determining unit 111 as history information; And a judgment unit 113 for judging whether or not the input state of the signal to be monitored has been completely restored.

According to the first aspect of the present invention, the disconnection detecting means 10
After the disconnection of the signal to be monitored is detected by 1, the determination result of the period of the signal to be monitored obtained by the period determination unit 111 is retained over a plurality of periods in response to the restart of the input of the signal to be monitored. Since it is held by the means 112,
The determining unit 113 can determine whether the period of the signal to be monitored has stabilized.

According to a second aspect of the present invention, in the signal disconnection / recovery detection circuit according to the first aspect, the period determining means 111 inputs a reference signal having a shorter cycle than a signal to be monitored. Change point detecting means 115 for detecting a change point of a signal to be monitored, and change point detecting means 11
5, a counting means 116 for performing a counting operation in synchronization with a reference signal from a predetermined initial value, and a discrimination index indicating an allowable range with respect to a period of a signal to be monitored with respect to the count value by the counting means 116. The index generating means 117 and the judging means 118 for judging whether or not the count value of the counting means 116 is within the allowable range indicated by the discrimination index in accordance with the detection of the change point by the change point detecting means 115. It is characterized by having a configuration provided.

According to the second aspect of the present invention, the counting means performs the counting operation in synchronization with the reference signal input by the reference signal input means in response to the detection result by the change point detecting means. In addition, the cycle of the signal to be monitored can be evaluated using the reference signal as a unit. If the index generation unit 117 obtains, as a discrimination index, the range of the count value of the counting unit 116 indicating the permissible range of the period of the signal to be monitored,
By comparing the count value of the counting means 116 with this determination index, the determining means 118 can determine whether or not the period of the signal to be monitored is within the allowable range.

According to a third aspect of the present invention, in the signal disconnection / recovery detecting circuit according to the second aspect, the reference signal input means 114 is provided.
Is characterized in that a spare clock signal supplied together with the clock signal to be monitored is introduced as a reference signal in order to generate a spare clock signal to replace the clock signal to be monitored. When the invention of claim 3 is applied to a system to which a backup clock signal is supplied together with at least one working clock signal, the backup clock signal can be used as a reference signal.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 shows an embodiment of the signal disconnection / recovery detection circuit according to the first and second aspects.
FIGS. 3 and 4 are timing charts showing the operation of detecting disconnection and restoration of this signal.

In FIG. 2, a counter 211 corresponds to the counting means 116 described in claim 2, and performs a counting operation in synchronization with a reference signal generated by an oscillator 212 corresponding to the reference signal input means 114. Configuration. 2, the signal generation unit 213 receives the count output of the counter 211, generates a signal (described later) relating to the magnitude of the count value, and outputs the signal to the determination circuit 21.
4 is sent.

The edge detecting section 215 corresponds to the change point detecting means 115, detects a rising edge of a signal to be monitored (for example, a clock signal), and determines an edge detection signal indicating the detection result. The data is sent to the terminal 214 and input to the “0” load ([0] load) terminal of the counter 211 described above. Therefore, as shown in FIG. 3, the clock signal to be monitored (FIG.
(see (a)), the counter 211 counts up to a value corresponding to the period of the clock signal to be monitored, and then initializes the count value according to the output of the edge detection unit 215. The operation of returning to the value “0” is repeated (FIG. 3
(b)).

Here, the count value of the counter 211 is:
Since the elapsed time from the detection of the rising edge of the clock signal to be monitored is expressed in terms of the period of the reference signal, the range of the threshold value T1 at which the clock signal should be judged to have been interrupted and the range of the period appropriate for the clock signal are specified. It can be associated with the count value of the counter 211. In the signal generation unit 213 shown in FIG. 2, the window signal generation unit 216 previously sets the range of the count value corresponding to the above-described range of the appropriate period as the window (see FIG. 3 (b)). The range is indicated by diagonal lines), an in-window signal indicating that the count value of the counter 211 is within the range of the window (in FIG. 2, indicated by a symbol “in”), An out-of-window signal indicating that the signal is out of the range (indicated by a symbol “out” in the figure),
What is necessary is just to make it the structure sent to the determination circuit 214.

As described above, the function of the index generating means 117 described in claim 2 is realized by operating the window signal generating section 216 based on the count value of the counter 211, and the periodic fluctuation of the signal to be monitored is realized. Can be generated and used for the operation of the determination circuit 214 described later. The counter 211 has a configuration in which all bits of the count value become logical “1” when the above-described threshold value T1 has elapsed from the edge detection. The overflow signal is received and sent to the determination circuit 214 as a clock cutoff signal (see FIG. 3C) indicating that the clock signal has been interrupted.

In this case, the occurrence of overflow of the counter 211 means the interruption of the clock signal. The function of the means 101 can be realized. In FIG. 2, the above-mentioned clock cutoff signal is invertedly input to the enable terminal of the counter 211, and has a configuration in which the counting operation is disabled when the interruption of the clock signal is detected.

Thus, once the interruption of the clock signal is detected, the clock interruption signal is changed to a logic "indicating the interruption of the clock signal" until the count value returns to the initial value "0" in response to the detection of a new edge. 1 "(Fig. 3
(c)). Of course, the signal generation unit 213 may be configured as a disconnection detecting unit 101 including a circuit that compares the count value of the counter 211 with a threshold value corresponding to the time T1, and outputs the comparison result as a clock disconnection signal. .

Next, the detailed configuration and operation of the decision circuit 214 will be described. In the determination circuit 214 shown in FIG. 2, the counter 221 controls the oscillator 21 according to a control signal (described later) obtained by the counter control unit 222.
The counting operation is synchronized with the reference signal obtained in step 2. Also, a flip-flop (FF) 223
Is set in response to the clock disconnection signal described above, outputs logic "1" as a clock disconnection detection signal indicating that the clock has been interrupted, and is reset in response to the overflow signal of the counter 221 to generate a clock disconnection detection signal. And outputs a logic “0” to indicate that the clock has been restored.

The counter control unit 222 shown in FIG.
, The AND gate 224 is configured to obtain the logical product of the edge detection signal and the signal in the window. In this case, when the edge of the clock signal is detected by the above-described edge detection unit 215 while the signal in the window keeps the logic "1", the output of the AND gate 224 becomes the logic "1", It is shown that the period of the signal falls within the range indicated by the window.

On the other hand, the edge detection signal is input to one of the input terminals of the AND gate 225 shown in FIG. 2, and the signal in the window is inverted to the other input terminal. Becomes logic "1" when the edge of the clock signal is detected when the signal in the window is logic "0", indicating that the cycle of the clock signal has fluctuated beyond the range indicated by the window.

As described above, the counter 211 described above is used.
By operating the AND gates 224 and 225 using the in-window signal obtained by the signal generation unit 213 as an index, the function of the determination unit 118 described in claim 2 is realized, and the edge detection unit 215 detects the function. For each of the edges, it can be determined whether or not the cycle of the clock signal is within a predetermined range.

That is, the functions of the period determining means 111 described in claim 1 are realized by these units, and a state where the period of the clock signal is stable and an unstable state are distinguished from each other. This can be used for a recovery operation from a clock interruption. In the counter control unit 222 shown in FIG. 2, the OR gate 226 is the AND gate 2 described above.
By calculating the logical sum of the output of the control signal 25 and the out-of-window signal, the state in which the clock is cut off and the state in which the cycle of the clock signal is shifted are synthesized.

The output of the OR gate and the output of the AND gate are input to the "0" load terminal and the enable terminal as control signals for the counter 221. Thus, the AND gate 224
, The counting operation of the counter 221 is enabled according to the output of the OR gate 226, and the count value is returned to the initial value “0” in accordance with the output of the OR gate 226. During this period, the counter 221 increments the count value in response to the rise of the edge detection signal, and the count value of the counter 221 changes to the initial value “0” in response to the occurrence of the clock interruption or the periodic fluctuation of the clock signal. (See FIG. 3D).

That is, the count value of the counter 221 is history information relating to the input of a clock signal having a normal cycle.
A function equivalent to 12 is performed. The counter 221 is configured such that when a clock signal having a normal cycle arrives over a recovery time T2 determined in consideration of a sufficient sample time, all bits of the count value become logic “1”. It has become.

Therefore, the occurrence of overflow of the counter 221 indicates the complete recovery of the clock signal.
The flip-flop 223 may be reset by this overflow signal. In this case, as shown in FIG.
When a clock signal having a stable cycle is supplied over the above-described return time T2, the count value of the counter 221 is incremented without being returned to the initial value, and the flip-flop is operated in accordance with the overflow signal of the counter 221. Step 2
The clock disconnection detection signal held at 23 is reset (see FIGS. 3D and 3E), indicating that the supply of the clock signal has been restored.

As described above, by operating the flip-flop 223 in response to occurrence of overflow of the counter 221, the function of the judgment means 113 described in claim 1 is realized, and the signal to be monitored ( Here, it is possible to detect the complete recovery of the clock signal) and notify the subsequent processing circuit. Also, as described above, the counter 221
Circuit component such as a decoder for generating a signal indicating the expiration of the recovery time from the count value of the counter 221 by directly inputting the overflow signal to the flip-flop 223 and using it for resetting the clock loss detection signal. Is unnecessary, and an increase in circuit scale can be suppressed.

On the other hand, as shown in FIG. 4A, when the supply of the clock signal is restarted, but the cycle of the clock signal is unstable, outside the window set for the count value of the counter 211, Since the edge of the clock signal is detected (see FIG. 4B), the clock cutoff signal is reset in accordance with this edge (see FIG. 4C), but the counter 221 is output in response to the output of the AND gate 225. Is returned to the initial value “0”.

Therefore, when the period of the clock signal is unstable, the count value of the counter 221 is returned to the initial value "0" every time the period deviates from an appropriate range. Regardless, the count value of the counter 221 does not overflow, and the flip-flop 22
The clock disconnection detection signal held at 3 is kept at logic "1" (see FIGS. 4D and 4E).

In this way, when the clock signal period fluctuates with the restart of the supply of the clock signal, the fluctuation can be reliably eliminated regardless of the length of the period in which the period is unstable. And only the clock signal having an appropriate period can be used for the operation of the subsequent circuit. As a result, for example, it is possible to guarantee an accurate operation of a clock transfer circuit or the like, and it is possible to contribute to an improvement in reliability of a device equipped with such a circuit.

Further, by adjusting the frequency and the width of the window of the reference signal, it is possible to detect the periodic fluctuation of the signal to be monitored with a desired accuracy and to utilize it for recovery detection. For example, when the period of the signal to be monitored is 1 ms, the output of an oscillator having a frequency of 1 MHz is input to the counter 211 as a reference signal, and the signal generator 213 outputs a signal having a width of 0.
If a signal within the window indicating the window of 05 ms is generated and supplied to the judgment circuit 214, the period shift of the signal to be monitored is reduced by 5%.
It can be detected with percent accuracy.

If it is sufficient to consider only the case where the period of the signal to be monitored is extended, the signal generation circuit 213 can be further simplified. For example, in the m-bit counter 211, when the range of the count value represented by the (m-1) th bit of the count output is a window, as shown in FIG. Is input to the OR gate 217, and a logical sum thereof is obtained to generate an in-window signal, and the highest-order m-th bit count output is sent to the determination circuit 214 as an out-of-window signal.

In this case, since circuit components such as a decoder and a comparator are not required, the signal generator 213 can be realized by an extremely simple circuit, and the amount of hardware as a whole can be reduced. Further, the above-described signal interruption / restoration detection circuit can detect interruption and restoration of supply of various signals other than the clock signal as described above.

For example, when a periodic pulse such as a frame pulse having a duty ratio of about several thousandths is to be monitored, an oscillator that oscillates at a period of tens of thousands of the period of the frame pulse is used as the oscillator 212. Prepare and
A counter element of about 16 bits may be prepared as the counter 211, and a signal generator 213 may generate an in-window signal indicating a window having a width corresponding to the width of the frame pulse, and supply the generated signal to the determination circuit 214.

On the other hand, when a random signal having a mark rate of about 50%, such as a pseudo noise signal, is set as a signal to be monitored, a signal in the window indicating a sufficiently wide window is generated, What is necessary is just to supply to the circuit 214. By the way, since the clock disconnection / recovery detection circuit shown in FIG. 2 operates using the output signal of the oscillator 212 as a reference signal, the clock of the oscillator 212 has a sufficiently short cycle as compared with the signal to be monitored. Stable oscillation is required.

On the other hand, when a clock signal is duplicated in a transmission system or the like, the clock signal serving as a standby system may satisfy the above-described conditions. For example, a case where a clock signal to be monitored is generated by dividing the frequency of a clock signal supplied via a network. Hereinafter, a method for detecting clock disconnection / recovery using the above-described spare clock signal will be described.

FIG. 6 shows an embodiment of a signal disconnection / restoration circuit to which the invention of claim 3 is applied. The signal disconnection / recovery detection circuit shown in FIG. 6 instead of including the oscillator 212, introduces a spare clock signal received via a network as it is, and inputs the spare clock signal to the counter 211 and the counter 221. It is configured to operate using a signal as a reference signal.

Thus, the reference signal input means 11 according to claim 3 is provided by the supply source of the clock signal and the wiring for introducing the spare clock signal into the signal disconnection / recovery detection circuit.
If the function of No. 4 is realized, it is possible to use the spare clock signal as a reference signal and provide the process of determining the periodic variation of the signal to be monitored. In this case, the oscillator 21
2 becomes unnecessary, all the components constituting the clock disconnection / recovery detection circuit shown in FIG. 5 can be formed by logic circuits.

Therefore, for example, it is possible to integrate the clock disconnection / recovery detection control circuit shown in FIG. 5 together with an LSI in which a clock transfer circuit is integrated, and it is indispensable for a conventional circuit using a mono-multi. Since a conventional external capacitor or the like becomes unnecessary, an effect of reducing the number of components of the entire apparatus can be expected.

On the other hand, in the signal disconnection / recovery detection circuit shown in FIGS. 2, 5 and 6, the portion for detecting interruption of signal input has the same function as that of the conventional mono-multi type. Therefore, disconnection detection is performed using a mono-multi,
The counter 211 may be configured to be used only for a window. In this case, regardless of the threshold value T1 for disconnection detection, for example, the number of bits of the counter 211 can be determined according to the cycle of the signal to be monitored, so that the counter 211 can be configured with a small number of elements. it can.

For example, when a signal disconnection / recovery detection circuit is applied to an existing signal processing circuit, the available mono-multi remaining in the signal processing circuit is used for disconnection detection of the signal disconnection / recovery detection circuit. When the counter 211 is downsized, the circuit scale can be reduced as compared with the case where all of the counter 211 is realized by a digital circuit.

[0045]

As described above, according to the first aspect of the present invention, the stability of the period of the monitored signal itself is evaluated when the input of the monitored signal is resumed after the signal to be monitored has been interrupted. By doing so, it is possible to strictly detect the restoration of the input regardless of the length of the period in which the cycle is unstable. Therefore, it is possible to prevent the signal in the unstable cycle from being supplied to the processing circuit in the subsequent stage. The adverse effects associated with disconnection and restoration can be minimized.

In particular, according to the second aspect of the present invention, the period of the signal to be monitored is objectively evaluated based on the period of the reference signal different from the signal to be monitored, and the deviation from the allowable range is evaluated. Can be reliably detected, so that it is possible to accurately evaluate the stability of the period of the signal to be monitored. Further, according to the third aspect of the present invention, when the signal to be monitored is a duplicated clock signal, the standby system clock signal is used as the reference signal, whereby the reference signal in the disconnection / recovery detection circuit is used. Generation is unnecessary, and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing an embodiment of a signal disconnection / recovery detection circuit according to claim 2;

FIG. 3 is a timing chart illustrating an operation of detecting disconnection and restoration of a signal.

FIG. 4 is a timing chart illustrating an operation of detecting disconnection and restoration of a signal.

FIG. 5 is a diagram showing another embodiment of the signal disconnection / recovery detection circuit of claim 2;

FIG. 6 is a diagram showing an embodiment of a signal disconnection / recovery detection circuit according to claim 3;

FIG. 7 is a diagram illustrating a configuration example of a conventional clock disconnection / recovery detection circuit.

FIG. 8 is a timing chart showing an operation of a conventional clock cut / recovery detection circuit.

[Explanation of symbols]

101 disconnection detecting means 102 recovery detecting means 111 period determining means 112 holding means 113 determining means 114 reference signal input means 115 change point detecting means 116 counting means 117 index generating means 118 determining means 211, 221 counter 212 oscillator 213 signal generating section 214 determining Circuit 215 Edge detection unit 216 Window signal generation unit 217, 226 OR gate 222 Counter control unit 223, 402 Flip-flop (FF) 224, 225 AND gate 401, 403 Monostable multivibrator (mono multi)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Jotaro Koshikawa 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa Prefecture In-house Fujitsu Digital Technology Co., Ltd. (72) Inventor Hiroshi Nishikawa 2-Shin-Yokohama, Kohoku-ku, Yokohama, Kanagawa No.3-9 Fujitsu Digital Technology Stock Company In-house

Claims (3)

[Claims] 1. A signal disconnection device comprising: disconnection detection means for detecting a disconnection state in which input of a signal to be monitored is interrupted; and recovery detection means for detecting a recovery point at which input of the signal to be monitored is restored to normal. In the restoration detection circuit, the restoration detection unit includes: a cycle determination unit that determines whether a cycle of the signal to be monitored is within a predetermined range in response to restart of input of the signal to be monitored; Holding means for holding determination results for a plurality of cycles by the determination means as history information; and determination means for determining whether or not the input state of the signal to be monitored has been completely restored based on the history information. A signal disconnection / restoration detection circuit characterized by having a configuration provided with. 2. The signal disconnection / recovery detection circuit according to claim 1, wherein the period determination unit receives a reference signal having a period shorter than the period of the signal to be monitored and a signal to be monitored. A change point detecting means for detecting a change point of, a counting means for performing a counting operation synchronized with the reference signal from a predetermined initial value in accordance with a detection result by the change point detecting means, and a count value by the counting means. An index generation means for generating a discrimination index indicating an allowable range for the cycle of the signal to be monitored, and a count value of the counting means is indicated by the discrimination index in response to detection of a change point by the change point detection means. A signal disconnection / recovery detection circuit, comprising: a determination unit configured to determine whether the signal is within an allowable range. 3. The signal disconnection / recovery detection circuit according to claim 2, wherein the reference signal input means generates a spare clock signal in place of the clock signal to be monitored together with the clock signal to be monitored. A signal disconnection / recovery detection circuit characterized in that the supplied backup clock signal is introduced as a reference signal.