JPH10320180A - Pseudo-random number generating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a random number through simple hardware and to obtain superior periodicity by latching the output signal of a counter circuit when a composite signal outputted by a gate circuit rises or falls and outputting the numeral of the counter as a pseudo-random number value. SOLUTION: A clock generating means for latching generates different clocks L1 to Ln for latching which have clock pulse widths that are odd multiples of that of a reference clock and relatively prime. An (n)-bit counter 4 counts with (n)-bit width on the basis of a counter clock which has pulse width that is the same with the reference clock or optionally a power-raised multiple of a positive number. A gate circuit 1 puts the clocks for latching together in specific combination. An (n)-bit latch circuit 3 latches the output signal of the (n)-bit counter 4 when the composite signal outputted from the gate circuit 1 rises or fall and outputs the numeral of the counter as a pseudo-random number value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-random number generator used in a pachinko game machine and the like, which is configured to provide a value as close to a natural random number as possible. . It is desirable that the following requirements be satisfied as ideal random numbers required in the gaming machine industry. (1) Equivalent frequency of occurrence of unique random numbers For example, when 1000 random numbers are generated,
It is desirable that the number of “0” and “1” (binary number) is 500 each. (2) Irregularity Even if the sequence (arrangement of random numbers) is irregular, it is specified in the sequence. In random number generators where random numbers appear in a fixed cycle, it is possible to aim easily with an interval timer generator such as a so-called bodily sensation device. (3) Reproducibility at the inspection organization Even if the test results equivalent to the test results from the gaming machine maker side are tested at the inspection organization, It must be reproducible as well.

[0002]

2. Description of the Related Art A conventional random number generation method used in a gaming machine is a pseudo random number generation method. However, even if a sequence of random numbers is relatively irregular, a specific random number is generated at a constant period. Some have appeared. For example, as a random number generation method, a random number by a linear congruential method (b = 0: product congruential method, b ≠ 0 mixed congruential method) is used, and is generated by the following equation. X _{n + 1} ≡aX _n + b (mod m) In such a linear congruential method, the period is limited by m no matter how large a value is selected for a and b, so that it cannot have a period exceeding m.

[0003]

That is, in the linear congruential method, in order to lengthen the period, it is necessary to set m to a large value, but there is a disadvantage that the scale of the hard logic increases in proportion thereto. is there. Although the hardware based on the linear congruential method is composed of four arithmetic operations, for example, if only a multiplication circuit of 16 bits × 16 bits is estimated, about 2000 to 3000 gates (when realized by a parallel operation method) are required. Further, the division circuit requires several times the number of gates. Even if a random number generator having a large cycle can be created, the probability of a jackpot required for a gaming machine is at most about one hundredth, so if it is generated at a large cycle, it will be several hundredths.
Separately requires a lottery circuit to match the probability. Therefore, the present invention has been made in view of the drawbacks of the conventional technology, and can generate random numbers with simpler hardware than a commercially available IC for generating random numbers. It is an object of the present invention to provide a pseudo-random number generator having a periodicity superior to that of the method (1) and capable of being reproduced in an inspection organization in the same manner as a development maker.

[0004]

According to the present invention, there are provided a plurality of latch clock generating means having clock pulse widths each being an odd multiple of the reference clock and being relatively prime, and having the same or arbitrary number of latch clocks. A counter circuit that counts with an n-bit width based on a counter clock having a pulse width that is a multiple of a power of a positive number, a gate circuit that combines the latch clocks by a predetermined combination, and a combined signal output from the gate circuit. This object is achieved by a pseudo-random number generator comprising a latch circuit which latches an output signal of a counter circuit at the time of rising or falling and outputs the value of the counter as a pseudo-random value. According to a second aspect of the present invention, a plurality of latch clock generating means are provided, a selector for the latch clock is interposed therebetween, and an output signal of the counter circuit is output as a pseudo-random value based on an arbitrary latch signal. It is. According to a third aspect of the present invention, there is provided a pseudo-random number generator including a storage unit for storing a random number value output from the latch circuit and inputting an initial value to an n-bit counter circuit. The invention according to claim 4 is a gaming machine control microcomputer incorporating the pseudorandom number generator.

[0005]

In the pseudorandom number generating device according to the present invention, n latch clocks whose pulse widths are odd multiples of the reference clock and which are relatively prime are respectively grouped to calculate a logical product or an exclusive logical sum. Is performed, the synchronizing period can be set as a multiplication value of the respective pulse width ratios. For example, <181 and 187> with respect to the reference clock,
When the ratio combination of <189 and 197> is adopted,
The respective synchronizing cycles are 33847 clocks and 3
This is the 7233th clock. Therefore, any logical product or the like is selected by adopting, for example, a clock having a pulse width of 30,000 as the selector clock. The timing of latching is irregular due to the rise or fall of the signal, and the count value (0 to 2 ⁿ -1) is output from the n-bit counter, and the latch circuit latches this value. Is output as a pseudo-random value. Since the numerical values output as these pseudo random numbers are extracted from the counter at irregular timings, they can be regarded as random numbers. Further, since the random number generator according to the present invention is configured so that the synthesized signal of the latch clock can be selected via the selector, the irregularity can be further increased. Theoretically, 3.78
× 10 It circulates at the ^13th clock. Claim 3
According to the invention, the pseudo random number value k selected by the latch circuit is stored in the storage means, and the initial value at the time of the next latch is started from k.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. FIG. 1 is a block diagram showing the concept of a first embodiment of a pseudo-random number generator according to the present invention. From a latch clock generating means (not shown), the pulse width is an odd multiple of a reference clock and are relatively prime. latch clock L ₁ a plurality of _{different, L 2, L 3 ... L} n are configured to be input to the gate circuit 1. The gate circuit 1 calculates a logical product or an exclusive OR by using each of the plurality of latch clocks as a set. As a result, m types of synthesized signals are input to the m-bit selector 2 from the gate circuit 1. Is done. The m-bit selector 2 employs a clock having a smaller number of clocks than the ratio of synchronizing the respective composite signals from the selection clocks.
Selects an arbitrary composite signal and outputs a signal to the n-bit latch circuit 3 as a latch signal. Reference numeral 4 denotes an n which receives an input of a counter clock and counts within a range of n bits.
This is a bit counter, and the count value of the counter 4 is output to the n-bit latch circuit 3. The n-bit latch circuit 3 is configured to hold the count value of the n-bit counter 4 based on the latch signal of the bit selector 2 and to output the held count value as a pseudo-random value. The output of the n-bit latch circuit 3 is output to the initial value storage memory 5 at the same time, and the memory 5 stores the inputted pseudo random number value as the initial value. The initial value stored in the memory 5 is input as an initial value at the start of counting of the n-bit counter 4, and the n-bit counter 4 starts counting from the initial value.

FIG. 2 shows the concept of the second embodiment of the present invention. In the case where a single oscillator is used to output a latch clock, a select clock and a counter clock, a simple oscillator is used. FIG. That is, an oscillator 9 that oscillates at a predetermined frequency, a counter clock generator 6 that divides the clock signal output from the oscillator 9 by a positive power, and extends the clock signal output from the oscillator 9. A plurality of latch clock generating means 7 ₁ , 7 ₂ ,... 7 _n whose pulse widths are odd multiples of the reference clock and are relatively prime via the circuit 10;
Means 8 for generating a select clock having a pulse width ratio before a plurality of different latch clocks are synchronized. Each of the clock signals includes a gate circuit 1, an m-bit selector 2, an n-bit latch Circuit 3, n
The pseudorandom number generator of the first embodiment, which includes the bit counter 4 and the memory 5, is connected to the second embodiment of the pseudorandom number generator as a whole.

FIG. 3 shows a specific logic circuit of the first embodiment of the pseudorandom number generator according to the present invention. The pulse width is an odd multiple of the reference clock and is relatively prime to the latch clock. 181 (197/197), 182
(189/189), 183 (187/187), 18
4 (181/181) is selected. The respective latch clocks are input to exclusive OR circuits 11 and 12, respectively, and the output signals thereof are selected clocks (30000).
/ 30000) to be input to the AND circuits 13 and 14. In the present embodiment, the select clock to the AND circuit 13 is NOT
It is input via a circuit 15. Also, each AND circuit 1
The output signals 3 and 14 are input to the OR circuit 16, and as a result, one of the exclusive OR circuit output signals is output as a latch signal.

Reference numeral 17 in FIG. 3 denotes a counting clock signal (10/10) obtained by multiplying the reference clock signal by a positive power, and is input to an n-bit (n = 4) counter circuit 22 as a basic counter clock. . Initially, in the present embodiment, A is input as the count initial value 21 from the memory 5, and the latch circuit 24 latches the count value of the counter circuit 22 at the rising edge of the latch signal output from the OR circuit 16, It consists of outputting as a random value. Reference numerals 23 and 25 denote monitors for performing hexadecimal display, and reference numerals 201 and 202 denote alternate switches for reset signals. 201 has a longer reset period than 202, that is, the inside of the counter circuit 22 and the latch circuit 24 is initialized during the reset period of 202, and the initial value A from the memory 5 is reset by the counter circuit during the reset period of 201. 22 and the reset signal becomes inactive, the counter circuit 22 is not "0",
The count-up starts from “A”.

FIGS. 4 and 5 are time charts showing the relationship between the latch clock, the signal latched by exclusive OR, and the count clock signal. 197/19
7) and (189/189) are used for the latch clock signal, and at the 30000th clock, the selection clocks are switched, so that (187/187) and (181)
/ 181) The latch clock signal will be used. The latch signal (LATCH) synthesized by the exclusive OR circuit 11 of the latch clock signal at each stage is shown in FIG.
In the column, by holding the count value of the counter circuit 22 at the time of the rising edge of the latch signal in the latch circuit 24, a numerical value as shown in FIG. Will be done.

FIG. 6 shows a specific logic circuit of the pulse width modulation circuit (hereinafter, referred to as a PWM circuit, consisting of 6, 71 to 7n, 8) shown in FIG.
FIG. 9 is a logic circuit diagram that can be set up to a range of 2 to 16 times the pulse width of FIG. In order to show the features of the PWM circuit, the logic circuit diagram employs a case where the low level of the pulse width of the desired clock is 3 and the high level is 2. Reference numeral 26 denotes a simple frequency-dividing circuit. When it is desired to use a counter clock of (2/2), a signal output from this circuit may be used as the counter clock. 27 and 28 are counter circuits for counting the reference clock 9. Reference numeral 29 denotes a setting circuit for setting a low-level pulse width ratio of a desired clock, and reference numeral 30 denotes a setting circuit for setting a high-level pulse width ratio. 31 is a counter circuit 27 and a setting circuit 2
The value of the counter circuit 28 is compared with the value of the setting circuit 30, and the value of the counter circuit 28 is compared with the value of the setting circuit 30. If the values match, the function of the comparator 32 is outputted. That is, when the pulse reaches the low-level pulse width 3 of the desired clock, the comparator 31 outputs a coincidence signal, and this signal is input to the circuit 34. The circuit 34 detects the rising of this signal and converts the low level output to the high level output. During this time, the time required to change from L to H is the low-level pulse width. The counter circuit 28 is disabled during the time until this change from L to H, and the circuit 34
Is output to the AND circuit 36, and counting is started only when the level of this signal becomes high. That is, when the pulse reaches the high-level pulse width of 2 of the desired clock, a match signal is output from the comparator 32, and this signal is converted to a low level by the NOT circuit 33 and input to the AND circuit 37. The circuit 34 is initialized by receiving a low level signal from the AND circuit 37, and converts a high level output to a low level output. During this time, the time required to change from H to L is the high-level pulse width. Similarly, the signal output from the NOT circuit 33 is also input to the AND circuit 35, and the counter circuit 27 is initialized by receiving the low level signal from the AND circuit 35, and counts up from 0 again. The above repetitive sequence generates the desired clock. Reference numeral 203 denotes an alternative switch for the reset signal, which is used for initialization when the power is turned on.

FIG. 7 is a time chart of the logic circuit diagram of FIG.

FIG. 9 shows an appearance cycle of a specific random value based on the test data shown in FIG.

FIG. 10 shows a third embodiment according to the present invention. In the apparatus of the embodiment shown in FIG. 1, an edge detecting circuit for detecting a falling (or rising) in a clock for a selector. 38, when the detection circuit 38 detects a change in the select clock, the data (random number value) of the latch circuit 3 at that time is loaded into the counter circuit 4, and the counter circuit 4 counts based on the data value. It is configured to start up.

In the pseudorandom number generator according to the present embodiment having the above-described configuration, first, a plurality of clocks whose pulse widths are odd multiples of the reference clock and which are relatively prime are selected. As odd numbers, 3, 5, 7, 11, 13, 17,
19, 23, 31, 37, 41, 43, 47, 53, 5
9, 61, 67, 71, 73, ..., 181, 187, 1
89, 191, 193, 197,... And an arbitrary odd number is selected. As a criterion for selection, a combination that maximizes the count number until synchronization is obtained. As a result, the odd numbers chosen will be relatively close. As an odd number to be selected, a clock number ratio of about 180 was selected.

Various combinations of odd numbers are conceivable.
In this embodiment, (197, 189), (181, 187)
Was selected. As a result, the theoretical synchronization cycle is 37233 clocks in the former case and 33
This is the 847th clock. It is required that the number f of clocks for the selector be smaller than these two synchronization periods. Therefore, any material that satisfies the requirement of f <33847 may be used. Therefore, in the example, 30,000 was selected. When the exclusive OR of these latch clocks is performed by the gate circuit 1, only the combination of the latch clocks (197, 189) operates since the selector clock is 0 from the 0th to the 30000th clock. , FIG.
The latch signal is as shown in FIG.

Since the latch circuit 3 is configured to detect the clock at the time of the rising of the latch signal, the data of the counter 4 latched by the latch circuit 3 is 0 to 0.
One of the 16 numerical values of F is output irregularly as shown in FIG. On the other hand, when the number of clocks for the select clock reaches 30,000, the exclusive OR of the combination of the latch clocks (181, 187) changes from L to H, which acts as a latch signal. The latch signal shown in FIG. In this embodiment, the pseudo-random number output when latched is input to the memory 5 at the same time as the output, and functions as an initial value when the 4-bit counter circuit 4 starts counting when the power is turned on again.

In the pseudorandom number generator according to the third embodiment shown in FIG. 10, when the logic of the selector clock is switched once every 30,000 clocks, the data (random number value) of the latch circuit 3 at that time is changed. This is input to the counter circuit 4.

In this embodiment, the latch clock is selected from a plurality of combinations and selected based on the clock signal for the selector. However, the present invention is not limited to this. As a simple method, the count value of the counter circuit 4 is output as a pseudo-random value based on a latch signal synthesized by an exclusive OR circuit of a set of different latch clock signals without using the selector circuit 2. It goes without saying that it may be configured.

[0020]

At present, in pachinko gaming machines and the like, generally, random numbers are generated by software, so that the burden on software is large. The pseudo-random number generator according to the present invention plays a role of reducing the load of such software, and even when generating the hardware, it is simpler than a commercially available IC circuit for generating random numbers, that is, without having an arithmetic circuit. It is possible to provide random numbers that can generate random numbers and have better periodicity (the occurrence period of a specific random number value is irregular) than the linear congruential method (multiplicative congruential method / mixed congruential method). it can. For this reason, it becomes virtually impossible for the player to intentionally aim at the prize timing using a machine (such as a bodily sensation device), draw a specific random number value, and aim for a jackpot. That is, it is possible to eliminate a capture method by manipulating the winning timing artificially. Further, as in the second embodiment, since the pseudorandom number generator can be operated with only a single oscillation source, the merit of cost is great.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a second embodiment of the present invention, in which the latch clock, the select clock, and the counter clock in the device according to the first embodiment are synthesized from one reference clock.

FIG. 3 is a specific logic circuit diagram in the device of FIG. 1;

FIG. 4 is a time chart (part 1) showing a relationship between each clock signal and a latch signal.

FIG. 5 is a time chart (part 2) showing a relationship between each clock signal and a latch signal.

FIG. 6 is a specific logic circuit diagram of a portion related to a PWM circuit in a second embodiment.

FIG. 7 is a time chart of the logic circuit diagram of FIG. 6;

FIG. 8 shows random number test data by the pseudorandom number generator according to the first embodiment of FIG. 3;

FIG. 9 is a comparison table of a generation cycle of a specific random number value according to each method.

FIG. 10 is a conceptual block diagram of a third embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 gate circuit 2 m-bit selector circuit 3 n-bit latch circuit 4 n-bit counter circuit 5 memory 6 counter clock generation circuit 7 latch clock generation circuit 8 select clock generation circuit 9 reference clock (oscillator) 10 extension circuit 11, 12 Exclusive OR circuit 13, 14, 34, AND circuit 35, 36, 37 AND circuit 15 33 NOT circuit 16 OR circuit 17 Counter clock 18 Latch clock 19 Select clock 20 Replacement switch for reset signal 21 Count initial value input Circuits 22, 27, 28 Counter circuit 24 Latch circuit 26 Divide-by-2 circuit 29 Low-level pulse width ratio setting circuit 30 High-level pulse width ratio setting circuit 31, 32 Comparator 38 Edge detection circuit

[Procedure amendment]

[Submission date] July 22, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

FIG. 3 shows a specific logic circuit of the first embodiment of the pseudorandom number generator according to the present invention. The pulse width is an odd multiple of the reference clock and is relatively prime to the latch clock. 18 ₁ (197/197), 18
₂ (189/189), 18 ₃ (187/187), 18
₄ (181/181) is selected. The respective latch clocks are input to exclusive OR circuits 11 and 12, respectively, and the output signals thereof are selected clocks (30000).
/ 30000) to be input to the AND circuits 13 and 14. In the present embodiment, the select clock to the AND circuit 13 is NOT
It is input via a circuit 15. Also, each AND circuit 1
The output signals 3 and 14 are input to the OR circuit 16, and as a result, one of the exclusive OR circuit output signals is output as a latch signal.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

Reference numeral 17 in FIG. 3 denotes a counting clock signal (10/10) obtained by multiplying the reference clock signal by a positive power, and is input to an n-bit (n = 4) counter circuit 22 as a basic counter clock. . Initially, in the present embodiment, A is input as the count initial value 21 from the memory 5, and the latch circuit 24 latches the count value of the counter circuit 22 at the rising edge of the latch signal output from the OR circuit 16, It consists of outputting as a random value. Incidentally, 23 and 25 is a monitor for performing hexadecimal, 20 _1, 20 _2, is an alternative switch both reset signals. 20 _1, it is 20 ₂ than the reset period is long, i.e. the internal counter circuit 22 and the latch circuit 24 during the 20 _second reset period initializes the further 20
_When the initial value A from the memory 5 is loaded into the counter circuit 22 during the reset period of ₁ and the reset signal becomes inactive, the counter circuit 22 starts counting up from "A" instead of "0". .

Claims (4)

[Claims] 1. A plurality of latch clock generating means, each having a clock pulse width odd and multiple relative to a reference clock and being mutually prime, and a pulse width equal to or an arbitrary positive multiple of the reference clock. A counter circuit that counts in an n-bit width based on a counter clock composed of: a gate circuit that combines the latch clocks by a predetermined combination; and a counter circuit that is used when a composite signal output from the gate circuit rises or falls. And a latch circuit for latching the output signal of the counter and outputting the value of the counter as a pseudo-random value. 2. A plurality of latch clock generating means each having an odd multiple of a clock pulse width and being relatively prime to a reference clock, and a pulse width of the same or an arbitrary positive multiple of the reference clock. A counter circuit that counts in n bits based on a counter clock consisting of: a gate circuit that combines the latch clocks in a predetermined combination; a selector that selects one of the output signals of the gate circuit; And a latch circuit for latching an output signal of the counter circuit at the time of rising or falling of the synthesized signal and outputting the value of the counter as a pseudo-random value. 3. The pseudo-random number according to claim 1, further comprising storage means for storing a random number value output from said latch circuit and inputting an initial value to an n-bit counter circuit. Generator. 4. A microcomputer for controlling a gaming machine, comprising a pseudo-random number generator according to claim 1.