JPH10340183A - Random number generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a random number generating circuit generating a random number string by simple circuit constitution. SOLUTION: This random number generating circuit is provided with a voltage control oscillating means (VCO) outputting oscillation frequency (CLK) varying depending the fluctuation of controlled voltage (Vcnt) inputted to a control terminal (Vin), a counter means (COUNT) counting and outputting the oscillation frequency of the voltage control oscillator, and a reading means (TSB) enabled to read the output value of the counter means by a random number reading control signal (READ-RND). As the oscillation frequency outputted from a voltage control oscillator is varied large by the delicate fluctuation of the controlled voltage inputted to the control terminal and the increment of a counter is varied large consequently by this constitution, a random number string varying unexpectably and irregularly can be obtained in spite of consecutively reading data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a random number generation circuit, and more particularly to a random number generation circuit capable of generating a random number sequence with a simple circuit configuration.

[0002]

2. Description of the Related Art In recent years, as IC cards and the like have become widespread, it has become necessary to easily create a random number sequence for creating an encryption key for data encryption. Here, conventionally,
As a method of obtaining a random number sequence, there are known a method of creating a random number by a software using a random number creating program and a method of creating a random number by a hardware using a random number creating circuit. However, since the random number sequence creation program has a relatively large structure, it is difficult to incorporate the random number sequence program into an IC card as described above. Therefore, there has been a demand for constructing a random number generating circuit having a relatively simple configuration in hardware and directly mounting it on a one-chip microcomputer or the like used in an IC card.

FIG. 7 shows an example of a conventional random number generation circuit built in a one-chip microcomputer or the like. As shown in the figure, the random number generation circuit 10 includes an oscillation circuit (OS) for generating a frequency clock independent of the operating frequency clock of the microcomputer.
C) 11 and an up-counter 12 which receives a frequency clock CLK from the oscillation circuit (OSC) 11 at an input terminal UP, and outputs from an output terminal Q a frequency clock output obtained by increasing the frequency clock stepwise. Have. Further, the output terminal Q of the up counter 12 is connected to one input terminal of the tristate buffer 13. When a random frequency is required, the read control signal RE is input to the other input terminal G of the tristate buffer 13.
When AD-RND is input, tristate buffer 1
The random frequency from the up-counter 12 is supplied from the output terminal 3 to the data bus 14 of the microcomputer, so that a pseudo-random number sequence can be obtained.

In the circuit configuration shown in FIG. 7, the clock frequency CLK supplied from the clock generation circuit 11 to the up counter 12 is always constant. As a result, a sequence having a fixed increment value is obtained, which may not function as a random number generation circuit, which is a problem.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional random number generation circuit. The present invention provides a new and improved random number generation circuit that can output an unpredictable random number sequence even when a random number is read out by reading a random number or immediately after power-on. .

[0006]

According to a first aspect of the present invention, there is provided a random number generating circuit configured to output a random number sequence that changes at random according to the present invention. (Vcn) and the control voltage (Vcn)
a voltage-controlled oscillating means (VCO) for outputting an oscillation frequency (CLK) that varies depending on the fluctuation of t), and a counter means (COUNT) for counting and outputting the oscillation frequency (CLK) of the voltage-controlled oscillator (VCO) ) And reading means (TSB) which is enabled by a random number reading control signal (READ-RND) and reads the output value (RND) of the counter means (COUNT).

According to this configuration, the control terminal (Vin)
The oscillating frequency (CLK) output from the voltage controlled oscillator (VCO) is greatly changed by a subtle fluctuation of the control voltage (Vcnt) input to the counter (CO).
Since the increment value of (UNT) can be greatly changed, even if data is read continuously, a random number sequence that changes unpredictably and irregularly can be obtained.

The control voltage input to the voltage-controlled oscillator (VCO) may be a power supply voltage (Vs) that constantly fluctuates slightly, as described in claim 2, or a control voltage as described in claim 3. A voltage signal (Sx) that changes independently of the operation of the counter means or a voltage signal (Vx) divided by a plurality of resistors (R1, R2) having different temperature coefficients as described in claim 4 is used. It is possible.

Further, according to another aspect of the present invention, as set forth in claim 5, the counter means (COUNT) comprises:
It is also possible to use a counter with a data load function (DL-COUNT). According to such a configuration, the predetermined data is stored in the counter (DL-COU)
By inputting to the load input terminal (Din) of (NT), the output value (RND) of the counter means (DL-COUNT) can be further changed at random.

Note that the counter means (DL-COUNT)
The load input terminal (Din) of
As described above, according to the control signal (Sy) that changes independently of the operation of the counter means (DL-COUNT),
It can be configured to load data on a data bus (DB).

Also, counter means (DL-COUNT)
The data input to the data bus (DB) according to the control signal (Sy) that changes independently of the operation of the counter means (DL-COUNT). Counter means (DL-COUNT)
If the configuration is such that the result of the logical operation with the output value is loaded, even if a data bus (DB) whose data value tends to have a relatively fixed value when the power is turned on is used, prediction is not possible. It is possible to obtain a possible effective random number sequence. The data of the data bus (DB) and the counter means (DL-COUNT)
By loading the exclusive OR with the output value of, a random number sequence with higher irregularity can be obtained.

The control signal (Sy) for driving the data load function-equipped counter (DL-COUNT) changes in a cycle shorter than the read interval of the random number read means (TSB). With this configuration,
A random number sequence can be obtained more effectively.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a random number generation circuit according to the present invention will be described in detail with reference to the accompanying drawings. In the following explanation,
Members having the same functional configuration will be denoted by the same reference numerals, and redundant description will be omitted.

First, the basic configuration of a random number generating circuit according to the present invention will be described with reference to FIG. 1. The random number generating circuit according to the present invention comprises a control voltage input from a control voltage generating source Vcnt to a control terminal Vin. And a counter COUNT which receives and counts an output clock CLK of the voltage controlled oscillator VCO at an input terminal UP and outputs the same from an output terminal Q.
And a tri-state buffer TSB as reading means enabled by the random number read control signal READ-RND and outputting the output RND of the counter COUNT to the data bus DB of the system as a random number.

In the random number generating circuit according to the present invention, the voltage controlled oscillator VCO is used as the clock generating circuit.
f / ΔVin) is set to be large. Therefore, if a voltage source Vcnt that can generate a control voltage that fluctuates arbitrarily is selected, the oscillation frequency CLK output from the voltage controlled oscillator VCO can be largely changed, and the random number read control signal READ-RND Even if data is continuously read from the counter COUNT whose increase / decrease value is constant according to the above, a random number sequence that changes irregularly and unpredictably can be obtained.

(First Embodiment) FIG. 2 shows a first embodiment of the present invention in which a power supply voltage Vs is used as a voltage generation source Vcnt. In the random number generation circuit shown in FIG. 2, when the power supply voltage Vs is input to the control terminal Vin of the voltage controlled oscillator VCO, the output oscillation frequency CLK fluctuates greatly even with a slight change in the power supply voltage Vs during operation. Therefore, even if the output value of the counter COUNT, which counts and outputs the oscillation frequency CLK output from the voltage controlled oscillator VCO, is read continuously, the increment of the counter COUNT greatly changes due to the fluctuation of the power supply voltage Vs. No, it does not become constant. Therefore, an effective random number sequence can be obtained even when random numbers are read out continuously for a certain period of time.

(Second Embodiment) FIG. 3 shows still another embodiment of the random number generation circuit according to the present invention. The basic configuration of the random number generation circuit according to the second embodiment is substantially the same as the random number generation circuit according to the first embodiment. An arbitrary control signal Sx irrelevant to the counting operation of the counter COUNT is input as a control voltage to be input to the control oscillator VCO, and the output of the voltage controlled oscillator VCO is configured to fluctuate by a change in the control signal Sx. Is characterized by the fact that

As the control signal Sx input to the input terminal Vin of the voltage controlled oscillator VCO, a digital signal having only "H" level or "L" level can be used. Alternatively, if these digital signals are converted into analog signals by an integrating circuit or the like, random numbers can be generated more effectively.

As described above, according to the second embodiment, any control signal Sx which changes to the "H" level or the "L" level regardless of the random number generation block operation.
Is input to the input terminal Vin of the voltage controlled oscillator VCO, so that the oscillation frequency CLK of the voltage controlled oscillator VCO also changes irregularly. Therefore, similarly to the case of the first embodiment, the increment of the counter CONT also changes irregularly, and a valid random number sequence can be obtained even when the random numbers are continuously read out for a certain period of time.

(Third Embodiment) FIG. 4 shows still another embodiment of the random number generating circuit according to the present invention. The basic configuration of the random number generation circuit according to the third embodiment is substantially the same as that of the random number generation circuits according to the first and second embodiments, but the random number generation circuit according to the third embodiment is different from the first embodiment. In the circuit, a control voltage Vx divided by resistors R1 and R2 having different temperature coefficients (ΔR / ΔT) is input as a control voltage to be input to the voltage controlled oscillator VCO, and the voltage control is performed by a change in the control signal Vx. It is characterized in that the output of the oscillator VCO is configured to fluctuate.

As shown in FIG. 4, a voltage controlled oscillator VCO
Power supply voltage input to the two resistors R with different temperature coefficients
Since the voltage divided according to the ratio of R1 and R2 is used as the control signal, as in the first embodiment, in addition to the change in the oscillation frequency due to the fluctuation of the power supply voltage, the temperature change during the operation The random number sequence can be obtained more effectively because the oscillation frequency also changes.

(Fourth Embodiment) FIG. 5 shows a random number generation circuit according to a fourth embodiment of the present invention. The random number generating circuit according to the fourth embodiment includes first to third random numbers.
In place of the counter COUNT used in the random number generation circuit according to the embodiment, an up-counter with a data load function (hereinafter, referred to as a DL counter) DL-C.
It is characterized by using OUNT. This DL
The clock CLK input to the input terminal UP of the counter DL-COUNT may be generated by any of the voltage controlled oscillators VCO of the random number generation circuits according to the first to third embodiments. This DL counter DL-
The load input terminal Din of COUNT is connected to the data bus DB of the microcomputer, and is enabled by a control signal Sy input to the control terminal LOAD to load predetermined data from the data bus DB to the DL counter DL-COUNT. It is configured to be.

Next, the operation of the random number generation circuit according to the fourth embodiment of the present invention will be described. First, the control terminal is connected to the DL counter DL-COUNT, and the DL counter DL-CKCOUNT is By inputting a control signal Sy that changes independently of the operation of
The value of the data bus DB is loaded into the DL counter DL-COUNT at irregular timing. Therefore, an irregular change can be added to the output, rather than simply changing the counter value by the oscillation frequency output from the voltage controlled oscillator VCO, and a random number sequence can be obtained more effectively.

It should be noted that the tristate buffer TSB
If the control signal Sy that changes in a cycle shorter than the interval at which the counter value is read from the L counter DL-COUNT is selected, the data is more frequently loaded into the DL counter DL-COUNT, and a more irregular random number sequence is generated. Generated and effective.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIG. In the fifth embodiment, the DL counter DL-COUNT is used as in the fourth embodiment. The clock CLK input to the input terminal UP of the DL counter DL-COUNT may be generated by any of the voltage controlled oscillators VCO of the random number generation circuits according to the first to third embodiments. In addition, DL counter DL-COUNT
As in the fourth embodiment, a control signal Sy that changes independently of the operation of the DL counter DL-COUNT is input to the control terminal LOAD. However, this fifth
The random number circuit according to the embodiment of the present invention uses the DL counter DL
The exclusive OR (XOR) of the output value of the COUNT itself and the value of the data bus DB is converted to a DL counter DL-COUNT.
XOR gate XOR for inputting to the load input terminal Din.

Next, the operation of the random number circuit according to the fifth embodiment will be described.
-COUNT to the control terminal, this DL counter DL-C
By inputting the control signal Sy that changes independently of the operation of COUNT, the value of the data bus DB is loaded into the DL counter DL-COUNT at irregular timing. At this time, by the XOR gate XOR,
Data bus DB value and DL counter DL-COUNT
The exclusive OR (XOR) of its own output value is taken and D
Loaded into the L counter DL-COUNT.

When the power is turned on, the value of the data bus DB tends to be a specific value. for that reason,
In a method in which the data bus DB is directly taken into the DL counter DL-COUNT as in the random number generation circuit according to the fourth embodiment, there is a possibility that a valid random number cannot be obtained at power-on. In this regard, according to the random number generation circuit according to the fifth embodiment, the data bus DB and the DL counter DL-COU whose value is undefined when the power is turned on.
The configuration is such that a value obtained by XORing the value of NT itself is loaded, so that an effective random number can be obtained even when the power is turned on.

In the above example, the data bus DB and D
It is configured to load the value obtained by XORing the value of the L counter DL-COUNT itself, but this is because the exclusive OR can obtain a result with higher irregularity compared to other logical operations. Therefore, the present invention is not limited to such an example, and may be configured to incorporate logic for executing another logical operation.

Although the preferred embodiment of the random number generation circuit according to the present invention has been described with reference to the accompanying drawings, the present invention is not limited to this example. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and it is obvious that the technical scope of the present invention is not limited thereto. It is understood that it belongs to.

For example, in the description of the above embodiment, all counters or DL counters are treated as up counters. However, the present invention is not limited to such an example, and all counters or DL counters can be configured as down counters. It is.

In the description of the above embodiment, it is assumed that the random number generation circuit is incorporated in a microcomputer or the like. However, the present invention is not limited to such an example, and is incorporated in a system constituted by only a logic circuit. It goes without saying that it is also possible.

[0032]

As described above, according to the present invention,
Even with a relatively simple circuit configuration, it is possible to obtain an unpredictable random number sequence even when it is easy to take a relatively constant value, that is, when reading is performed continuously for a fixed time or immediately after power-on. Therefore, a more effective random number generator can be configured.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a basic configuration of a random number generation circuit configured based on the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a random number generation circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a schematic configuration of a random number generation circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a schematic configuration of a random number generation circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram illustrating a schematic configuration of a random number generation circuit according to a fourth embodiment of the present invention.

FIG. 6 is a block diagram illustrating a schematic configuration of a random number generation circuit according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram showing a schematic configuration of a conventional random number generation circuit.

[Explanation of symbols]

 Vcnt control voltage source VCO voltage controlled oscillator COUNT counter TSB tristate buffer DB data bus CLK oscillation frequency READ-RND random number read control signal RND random number

Claims (9)

[Claims] 1. A random number generation circuit that outputs a random number sequence that changes randomly: a voltage control oscillator that outputs an oscillation frequency that changes depending on a change in a control voltage input to a control terminal; A random number generation circuit, comprising: counter means for counting and outputting the oscillation frequency of the counter; and reading means enabled by a random number read control signal and reading an output value of the counter means. 2. The random number generation circuit according to claim 1, wherein said control voltage is a power supply voltage. 3. The random number generation circuit according to claim 1, wherein said control voltage is a voltage signal which changes independently of the operation of said counter means. 4. The control voltage is divided by a plurality of resistors having different temperature coefficients.
The random number generation circuit according to claim 1. 5. The apparatus according to claim 1, wherein said counter means is a counter with a data load function.
Or the random number generation circuit according to any one of 4. 6. The load input terminal of the counter means is loaded with data on the data bus in response to a control signal which changes independently of the operation of the counter means. The random number generation circuit according to 1. 7. A load input terminal of said counter means receives a result of a logical operation of data on said data bus and an output value of said counter means in response to a control signal which changes independently of the operation of said counter means. The random number generation circuit according to claim 5, wherein is loaded. 8. The random number generation circuit according to claim 7, wherein said logical operation is an exclusive OR. 9. The random number generating circuit according to claim 6, wherein the control signal changes in a cycle shorter than a reading interval of the random number reading means.