JPH10313095A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a capacitive element of large capacity to be added inside a chip without occupying an additional space by a method wherein a first polycrystalline silicon layer is formed and connected under a bonding pad, and the capacitive element is formed by the use of a single crystal silicon substrate through the intermediary of a thin silicon oxide film. SOLUTION: A well 14 is built in a single crystal silicon substrate 1, a field oxide film (LOCOS) 2 is formed through thermal oxidation, and a silicon oxide film 3 is formed thereon through thermal oxidation. Furthermore, a first polycrystalline silicon wiring 4 is formed through a CVD method to serve as a counter substrate potential electrode. Thereafter, a diffusion layer 5 is formed through a self-aligned method, a silicon oxide film 6 is grown through thermal oxidation, and a contact hole 7 is bored in the silicon oxide film 6. Moreover, a first aluminum wiring layer 8 is formed thereon, and a second aluminum wiring layer 9 is formed through the intermediary of a contact hole 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure of a capacitive element immediately below a bonding pad.

[0002]

2. Description of the Related Art A power supply potential (VC) for noise is described below.
C) A conventional example of a capacitive element used to suppress the fluctuation of the wiring and the GND wiring is shown.

In FIG. 3, 1 is a single crystal silicon substrate,
14 is a well region, 2 is a field oxide film (LOCOS) for separating a cell region, 3 is a (gate) silicon oxide film, 4 is a gate electrode made of first polycrystalline silicon, 5 is a diffusion layer, and 8 is a first layer. It is a metal (aluminum) wiring layer and is connected to the polycrystalline silicon layer 4 through a contact hole 7. Further, a second metal (aluminum) wiring layer 9 is present on the upper portion, and a contact hole (through hole) 1 is formed.
1 has a structure connected to the first metal (aluminum) wiring layer 8. The second metal (aluminum) wiring layer 9 is a power supply potential (VCC) wiring, and a capacitance element is formed by the polysilicon wiring layer 4 and the P-type silicon substrate 1.

FIG. 4 is a cross-sectional view of a conventional bonding PAD portion, in which a first or second metal wiring layer is present, and a gold (aluminum) wire is bonded thereon. The first or second metal wiring layer is connected to an internal power supply wiring.

As described above, the conventional PAD has a structure merely for bonding a gold (aluminum) wire.

As described above, there has been a structure in which a capacitance element is connected to a general power supply wiring layer to suppress fluctuations in power supply noise. However, this structure is limited by the chip size, so that the structure on the chip is limited. However, it was difficult to obtain more on-chip capacitance.

[0007]

SUMMARY OF THE INVENTION Semiconductor devices will be
As miniaturization and miniaturization (such as chip size) have been further advanced, the capacitance of the memory cell section and the peripheral capacity block has been reduced. Therefore, fluctuation of power supply voltage (noise)
It is necessary to pay sufficient attention to the fluctuation of the potential at the time of incidence of α-ray particles.

In order to cope with this, it is necessary to add a large capacitance element without taking extra space in the chip.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which a large capacitance element can be added without taking extra space in a chip.

[0010]

The above object is achieved by the following means.

That is, the present invention relates to a bonding PAD
A semiconductor device comprising: a first polycrystalline silicon layer connected and formed immediately below; and a capacitive element formed by a single crystal silicon substrate immediately below through a thin silicon oxide film. The present invention proposes a structure in which the first polycrystalline silicon layer is replaced with a second polycrystalline silicon layer.

Further, according to the present invention, there is provided a capacitor formed by a second polycrystalline silicon layer connected and formed immediately below a bonding PAD and a first polycrystalline silicon layer present immediately below via a thin silicon oxide film. The present invention proposes a semiconductor device characterized by having an element, and further has a third and fourth polycrystalline silicon layers with respect to the semiconductor device, each of which has a capacitance as described above. A semiconductor device having a structure is proposed.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1A shows the power supply or GN of Embodiment 1.
FIG. 1B is a cross-sectional view of a PAD portion for D, and FIG.

FIG. 1A, here, first, a well 14 is formed in a single-crystal silicon substrate 1, and the LO 14 is formed by thermal oxidation.
COS 2 is formed, and a silicon oxide film 3 (about 12 nm thick) is formed thereon by thermal oxidation. Further, CVD
The first polysilicon wiring 4 (having a thickness of about 200 n
m). This is used as a potential electrode with respect to the substrate of the capacitor. Thereafter, the diffusion layer 5 is formed in a self-aligned manner by an ion implantation method. Then, a silicon oxide film 6 is grown to about 100 nm by thermal oxidation.

Further, the first polysilicon wiring 4
A contact hole 7 is formed in the upper silicon oxide film 6. Then, a first aluminum (metal) wiring layer 8 is formed thereon.
To form If the semiconductor device does not have the second aluminum (metal) wiring layer 9, the first aluminum (metal) wiring layer 8 is used as a PAD bonding connection surface.

When the semiconductor device has the second aluminum (metal) wiring layer 9, a BPSG interlayer film 10 (about 300 nm) is formed on the first aluminum (metal) wiring layer 8. Thereafter, a contact hole (through hole) 11 is formed thereon, and a second aluminum (metal) wiring layer 9 serving as a PAD bonding connection surface is formed.

When the bonding PAD has the above-described structure and is used for a power supply (Vcc), the well 14 is
ND potential, and has a capacity for the first polycrystalline silicon wiring 4. If this bonding PAD is for GND potential, the single crystal silicon substrate 1 is set to the Vcc potential, The wiring 4 has a capacitance.

As a result, the area of the PAD portion is reduced to about 100 ×
Assuming 100 μm, if one PAD has about 50 pF and one CHIP has 20 power supply PADs,
A capacity of about 1000 pF is obtained.

As described above, in the first embodiment, by using only the normal process necessary for forming a general semiconductor integrated circuit, it is possible to form a capacitive element immediately below the power supply / GND bonding PAD portion. it can. As a result, a larger capacitance value of the on-chip capacitor can be obtained for the entire chip, and fluctuation of noise or the like between the power supply and GND can be prevented. (Embodiment 2) Next, Embodiment 2 will be described below in which the impact at the time of bonding in Embodiment 1 is taken into consideration. (See FIG. 2A.) First, similarly to the first embodiment, a well 14 is formed in a single-crystal silicon substrate 1, a LOCOS 2 is formed by thermal oxidation, and a silicon oxide film 3 (having a thickness of about 12 nm)
Is formed by thermal oxidation. Further, the first method is performed by the CVD method.
A polycrystalline silicon wiring 4 (about 200 nm thick) is formed. Thereafter, the diffusion layer 5 is formed in a self-aligned manner by an ion implantation method. Then, a silicon oxide film 6 is grown to about 100 nm by thermal oxidation.

From the above, unlike the first embodiment, a second polycrystalline silicon layer 12 (about 100 nm thick) is formed on the silicon oxide film 6 and the silicon oxide film 13 is formed to a thickness of about 100 nm by thermal oxidation. Let it grow.

Thereafter, as in the first embodiment, the second
A contact hole 7 is formed in a silicon oxide film 13 above the polycrystalline silicon wiring 12. And on top of that,
The aluminum (metal) wiring layer 8 is formed. If the semiconductor device does not have the second aluminum (metal) wiring layer 9, the first aluminum (metal) wiring layer 8 is used as a PAD bonding connection surface.

When the semiconductor device has the second aluminum (metal) wiring layer 9, a BPSG interlayer film 10 (about 300 nm) is formed on the first aluminum (metal) wiring layer 8. Thereafter, a contact hole (through hole) 11 is formed thereon, and a second aluminum (metal) wiring layer 9 serving as a PAD bonding connection surface is formed.

When the bonding PAD has the above structure and is used for a power supply (Vcc), the well 14 is set to the power supply (Vcc) potential, and the first polysilicon wiring 4 is set to GN.
By setting the potential to D, the well 14 has a capacity with respect to the first polysilicon wiring 4, and the first polysilicon wiring 4 has a capacity with respect to the second polysilicon wiring 12. (The first polysilicon wire 4 (GND potential) has a capacitance structure sandwiched between the well 14 and the second polysilicon wire 12 (Vcc potential).) If this bonding PAD is for the GND potential, 14
To the GND potential and the first polysilicon wiring 4 to the power supply (V
By setting the potential to cc), the well 14 has a capacity with respect to the first polysilicon wiring 4, and the first polysilicon wiring 4 has a capacity with respect to the second polysilicon wiring 12. (The first polysilicon wire 4 (Vcc potential) has a capacitance structure sandwiched between the well 14 and the second polysilicon wire 12 (GND potential).) As a result, if the area of the PAD portion is about 100 × 100 μm Approximately 60pF per PAD. If one CHIP has 20 power supply PADs, about 1200pF
The capacity of F is obtained.

As described above, also in the second embodiment, by using only a normal process necessary for forming a general semiconductor integrated circuit, a capacitor can be formed immediately below a power supply or a bonding PAD portion for GND. Can be.
Further, by improving the first embodiment as in the second embodiment,
It is resistant to the shock at the time of bonding and can obtain a large capacitance value.

[0025]

As described above, the present invention can be realized only by ordinary steps necessary for forming a general semiconductor integrated circuit, and can be realized by a power supply or a GND bonding P.
By forming a contact hole directly under AD (AL layer), it is possible to connect to the first polycrystalline silicon layer and form a capacitive element between the polycrystalline silicon layer and the single crystal silicon substrate via a thin silicon oxide film. Become.

In recent years, with the reduction in chip area, on-chip capacitors for suppressing fluctuations in power supply wiring have been reduced.
Since it is formed immediately below AD, there is no restriction due to the chip area. Further, in recent semiconductor integrated devices, since many power supply / GND PADs are provided, it is possible to form many capacitance elements.

Further, in the semiconductor device, the third,
It has a fourth polycrystalline silicon layer, and the respective (first to fourth polycrystalline silicon wiring layers) overlap as described above to form a capacitance structure and form a capacitance element having a larger capacitance value. It is also possible.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a bonding PAD unit chip according to a first embodiment of the present invention, and FIG.
3 is a plan view of a bonding PAD section of FIG.

FIG. 2A is a cross-sectional view of a bonding PAD unit chip according to a second embodiment of the present invention, and FIG.
3 is a plan view of a bonding PAD section of FIG.

FIG. 3 is a cross-sectional view of a conventional capacitive element.

FIG. 4 is a cross-sectional view of a conventional bonding PAD portion.

[Explanation of symbols]

 Reference Signs List 1 single-crystal silicon substrate 2 LOCOS 14 well region 3, 6, 10, 13 silicon oxide film 4 first polycrystalline silicon wiring 12 second polycrystalline silicon wiring 5 diffusion layer 7, 11 contact hole 8 first metal (aluminum) wiring 9 Second metal (aluminum) wiring

Claims (4)

[Claims] A capacitor element formed by a first polycrystalline silicon layer connected and formed directly below a bonding pad and a single crystal silicon substrate immediately below the first polycrystalline silicon layer via a thin silicon oxide film. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein said first polycrystalline silicon layer is replaced with a second polycrystalline silicon layer. 3. A capacitor formed by a second polycrystalline silicon layer connected and formed immediately below a bonding PAD and a first polycrystalline silicon layer immediately below the second polycrystalline silicon layer via a thin silicon oxide film. A semiconductor device characterized by the above-mentioned. 4. The semiconductor device according to claim 1, further comprising third and fourth polycrystalline silicon layers, each of which has the above-described capacitance structure.