JPH10312412A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of a semiconductor IC without increasing the delay time of a critical path by using a 1st combinational circuit having a 2nd logical gate which suppresses the signal transmission delay time less than its upper limit value for a signal transmission line serving as the critical path. SOLUTION: A combinational circuit having the signal transmission delay time less than its upper limit value is synthesized with a 1st combinational circuit using a low voltage source 16 of 2V, and a combinational circuit having the signal transmission delay time more than its upper limit value is synthesized with a 2nd combinational circuit having a high voltage source 15 of 3V respectively. If the estimation result of the signal transmission delay time is less than the designed upper limit delay value, a combinational circuit, i.e., an aggregate of logical gates provided on a signal transmission line is mapped onto a combinational circuit of logical cell libraries of low voltage (2V). If the estimation result is more than the designed upper limit delay value, the combinational circuit, i.e., the aggregate is mapped onto a combinational circuit of high voltage (3Vlib).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an improved logic synthesis method for generating a semiconductor integrated circuit from a register transfer level, and more particularly to a logic synthesis method for generating a low power consumption semiconductor integrated circuit. The present invention relates to a low power consumption semiconductor integrated circuit obtained by the above method.

[0002]

2. Description of the Related Art Today, in the design of a semiconductor integrated circuit, a semiconductor integrated circuit to be developed is represented by a function description at a register transfer level (hereinafter, referred to as RTL), and the logic is synthesized using the RTL description. ,
A top-down design for generating a semiconductor integrated circuit to be developed is employed.

FIG. 24 shows a conventional RTL description, and FIG. 25 shows a logic circuit (semiconductor integrated circuit) generated by logic synthesis using the RTL description.

[0004] The RTL description in FIG. 24 is a description clearly defining data transfer between a plurality of registers at a functional level. In the RTL description shown in the figure, r1, r2, r3, and r4 are registers, func1, func2, func3, and func4 are descriptions of the function of a combinational circuit between the registers. It describes the connection relationship.

When synthesizing logic from the RTL description of FIG. 24, a circuit is determined on a trade-off curve of area and speed by giving constraints on area or speed.

In the logic circuit shown in FIG. 25 generated from the RTL description, 101, 103, 105, and 107 are flip-flops in which registers r1, r2, r3, and r4 specified in the RTL description are mapped by logic synthesis. 24, the registers r1 and r specified in the RTL description of FIG.
Corresponds directly to 2, r3, r4. 108 is the clock buffer, 10
0, 102, 104, and 106 are func1, func1, of the RTL description in FIG.
This is a combinational circuit corresponding to func2, func3, and func4. The combinational circuits 100, 102, 104 and 106 correspond to the RT shown in FIG.
It is mapped from the function description of L as one circuit on the curve of trade-off between area and speed.

[0007]

By the way, the power consumption P of the semiconductor integrated circuit can be expressed as follows: operating frequency f, load capacitance C,
As the voltage and V [Equation 1], represented by [Equation 1] P = f x C x V 2. Therefore, there are three methods for reducing the power consumption of the semiconductor integrated circuit: lowering the operating frequency, lowering the load capacity, or lowering the power supply voltage. The reduction effect due to the reduction in the power supply voltage is the largest.

However, when the power supply voltage is set low, the delay time of the critical path having the maximum delay time among many paths constituting the logic circuit also increases.

In view of the above, for example, a technique disclosed in Japanese Patent Laid-Open Publication No. Hei 5-299624, that is, a logic gate which operates at a low speed among a large number of logic gates is driven by a low voltage source,
Utilizing technology for driving other logic gates requiring high-speed operation by a high voltage source, only the logic gates constituting the critical path are driven by a high voltage source, and the other logic gates are driven by a low voltage source. Thus, it is conceivable to reduce the current consumption of the entire semiconductor integrated circuit by using a low-voltage power supply without increasing the maximum delay time of the critical path, thereby achieving low power consumption. However, this idea has the following disadvantages.

The details of the above disadvantages are as follows. As described above, when data is transmitted from a low-speed logic gate driven by a low voltage source to a high-speed logic gate driven by a high voltage source, for example, Japanese Patent Laid-Open No. 5-67963
As disclosed in Japanese Patent Application Laid-Open Publication No. H10-115, it is necessary to arrange a level conversion circuit between the two logic gates for converting the output level of the logic gate driven by the low voltage source to a high level. However, each of the combinational circuits shown in FIG.
6 or a circuit composed of a large number of logic gates as shown in FIG. 27, if it is assumed that the critical path is a path shown by a bold line in the combination circuit of each figure, this critical path is connected to a high voltage source. In order to drive with a plurality of positions indicated by the symbol 位置 in each figure (the number of positions is
It is determined that a level conversion circuit is required at eight locations and at twelve locations in FIG. In a highly integrated semiconductor integrated circuit, the number of combination circuits is extremely large, and the number of logic gates constituting each combination circuit is also extremely large. Therefore, in such a highly integrated semiconductor integrated circuit, the number of positions requiring a level conversion circuit in one combinational circuit having a critical path is large, and the number of combinational circuits having a critical path is large. The number of positions requiring a level conversion circuit in the entire circuit is enormous. As a result, in the design of a highly integrated semiconductor integrated circuit, it is possible to determine and arrange the position where the level conversion circuit is required as described above using a combination circuit that is only partially limited. However, there are drawbacks in that the determination of the arrangement position of the level conversion circuit is complicated and troublesome, takes a long time, and makes the design difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a logic synthesis method for generating a semiconductor integrated circuit from an RTL description, the criticality of each combinational circuit of the semiconductor integrated circuit to be developed. Provided is a logic synthesis method capable of easily generating a low power consumption semiconductor integrated circuit without causing an increase in path delay time, and a low power consumption semiconductor integrated circuit without such an increase in critical path delay time. Is to do.

[0012]

In order to achieve the above object, the present invention focuses on the following points. That is, first, as shown in FIG. 25, the semiconductor integrated circuit includes a large number of registers and a large number of combinational circuits located between the registers. It is not necessary to arrange the level conversion circuits at various places, that is, at a plurality of positions where the level conversion circuits are required when the critical path is driven by a high power supply.
That the number of level conversion circuits can be reduced
Second, if a level conversion circuit is arranged in a register as described above, in a combinational circuit to which data is transmitted from this level conversion circuit, it is necessary to drive the entire combinational circuit with a high power supply. According to statistics that the number of logic gates present on the critical path is about 5% of the number of logic gates constituting the entire integrated circuit, the ratio of the combinational circuit having the critical path to the whole combinational circuit is small, and We focused on the fact that even if the entire combinational circuit having a critical path is driven by a high power supply, the power consumption does not increase much.

That is, according to the logic synthesis method of the present invention, a semiconductor integrated circuit composed of a plurality of registers and a plurality of combinational circuits located between the plurality of registers is synthesized based on connection information of logic cells. Logic synthesis method,
If the signal propagation delay time of any one of the combinational circuits is equal to or less than the designed delay upper limit, this combinational circuit is combined with a first combinational circuit using a low voltage source as a voltage source, and A first step of combining the combinational circuit with a second combinational circuit using a high voltage source as a voltage source if the signal propagation delay time of the circuit exceeds a design delay upper limit;
It is determined whether or not the output of any one of the combined first combinational circuits is mixed in the form of the input to the combined second combinational circuit. In the second combinational circuit, and determining whether each of the registers is a register for outputting a signal to the combined or recombined second combinational circuit. A third step of combining this register with a register using a high voltage source as a voltage source if the register is used, and combining this register with a register using a low voltage source as a voltage source otherwise. According to a second aspect of the present invention, in the logic synthesis method according to the first aspect, the first step is performed by first registering the register driven by the first combinational circuit and the low voltage source. Using the low power A signal propagation delay time obtained by combining the register driven by the power supply and the first combinational circuit is estimated. Then, if there is a first combinational circuit in which the estimation result is equal to or less than the designed delay upper limit value, One combinational circuit is combined with a first combinational circuit, and if there is a first combinational circuit whose estimation result exceeds the designed delay upper limit, the first combinational circuit is combined with a second combinational circuit. The process is characterized in that

Further, according to the third aspect of the present invention, there is provided the first aspect of the present invention.
In the described logic synthesis method, the first step comprises:
All the combinational circuits are synthesized using the first combinational circuit,
Next, it is determined whether or not the signal propagation delay time of the combinational circuit exceeds the design delay upper limit value. If there is a first combinational circuit exceeding the design delay upper limit value, the first combinational circuit is determined. Is recombined into a second combinational circuit.

In addition, in the invention according to claim 4, in the logic synthesis method according to claim 1, the second step is a step of re-synthesizing the first combinational circuit into the second combinational circuit.
It is determined whether the output of any one of the first combinational circuits is mixed in the form of being input to the synthesized second combinational circuit or not. Characterized by a step of repeating re-combining the combinational circuit into the second combinational circuit.

According to a fifth aspect of the present invention, in the logic synthesis method of the first aspect, the register transfer level design data describing a plurality of registers and a plurality of combinational circuits located between the registers. And the logic cell connection information in the first step is generated from the input register transfer level design data.

According to a sixth aspect of the present invention, in the logic synthesis method of the first aspect, a netlist describing connection information of the logic cells is input, and the connection information of the logic cells in the first step is: It is generated from the connection information of the logic cells described in the input netlist.

According to a seventh aspect of the present invention, in the logic synthesizing method according to the first aspect, a schematic representing connection information of the logic cell is input, and the connection information of the logic cell in the first step is set as the logic information. It is characterized by being generated from the input connection information of the logic cells represented in the inputted schematic.

In addition, in the invention according to claim 8, in the logic synthesis method according to claim 5, 6, or 7, the input register transfer level, the input netlist, or the input It is characterized in that the connection information of the logic cells based on the schematic is optimized, and the connection information of the optimized logic cells is used as the connection information of the logic cells in the first step.

According to a ninth aspect of the present invention, in the logic synthesis method of the first, second, third or fourth aspect, after the third step, the timing of each register is adjusted. It is characterized by having a step of verifying.

According to a tenth aspect of the present invention, there is provided a semiconductor integrated circuit having a plurality of registers and a plurality of combinational circuits located between the registers, wherein a part of the plurality of combinational circuits is provided. The combinational circuit includes a first combinational circuit using a low voltage source as a voltage source, and the other combinational circuit among the plurality of combinational circuits includes a second combinational circuit using a high voltage source as a voltage source. Among the plurality of registers, the register in which the first combinational circuit is located on the input side and the second combinational circuit is located on the output side includes a data temporary storage unit using a low voltage source as a voltage source, and a high voltage source. It is characterized by comprising a register having, as a voltage source, a level conversion circuit for level-converting a low-voltage output signal of the data temporary storage section into a high-voltage output signal.

Further, in the semiconductor integrated circuit according to the present invention, the register in which the first combinational circuit is located on the input side and the output side among the plurality of registers, and the input side. The second combinational circuit is located at the output side and the first combinational circuit is located at the output side. Each of the registers includes a low-voltage source as a voltage source and does not have a level conversion circuit. , A register in which the second combinational circuit is located on each of the input side and the output side is a data temporary storage unit using a low voltage source as a voltage source, and a low voltage output of the data temporary storage unit using a high voltage source as a voltage source. And a level conversion circuit for level-converting the signal into a high-voltage output signal.

According to a twelfth aspect of the present invention, in the semiconductor integrated circuit according to the tenth or eleventh aspect, the semiconductor integrated circuit includes a clock supply unit that uses a low voltage source as a voltage source and supplies a clock to each register. It is characterized by.

[0024] In addition, according to the invention of claim 13,
13. The semiconductor integrated circuit according to claim 10, wherein the register having the level conversion circuit comprises a flip-flop circuit, and the flip-flop circuit is a master connected in series with a low voltage source as a voltage source. A latch and a slave latch, an output buffer using a high voltage source as a voltage source, and a level conversion of a low voltage signal input from the slave latch interposed between the slave latch and the output buffer to a high voltage signal. And a level conversion circuit for outputting to the output buffer.

According to a fourteenth aspect of the present invention, in the semiconductor integrated circuit according to the eleventh or twelfth aspect, the register having no level conversion circuit comprises a flip-flop circuit, and the flip-flop circuit operates at a low voltage. It has a master latch and a slave latch connected in series using a source as a voltage source, and an output buffer that uses a low voltage source as a voltage source and inputs an output signal from the slave latch.

Further, in the invention according to claim 15, in the semiconductor integrated circuit according to claim 10, 11, or 12, the register having the level conversion circuit comprises a latch circuit, and the latch circuit comprises A latch unit using a voltage source as a voltage source, an output buffer using a high voltage source as a voltage source, and a low voltage signal interposed between the latch unit and the output buffer and inputted from the latch unit to a high voltage. And a level conversion circuit for performing level conversion and outputting the result to the output buffer.

In addition, according to the invention of claim 16, in the semiconductor integrated circuit of claim 11 or 12, the register having no level conversion circuit comprises a latch circuit, and the latch circuit comprises a low voltage source. And a output buffer for inputting an output signal from the latch unit using a low voltage source as a voltage source.

[0028] In addition, in the invention of claim 17,
The semiconductor integrated circuit according to claim 10, 11 or 12, wherein each register is constituted by a flip-flop circuit for scan test.

In the invention according to claim 18, in the semiconductor integrated circuit according to claim 17, the scan test flip-flop circuit having a level conversion circuit among the scan test flip-flop circuits includes a low voltage source. A multiplexer for selecting any one of a plurality of input data in accordance with a control signal externally input as a voltage source, and a serially connected master latch for inputting a signal from the multiplexer using a low voltage source as a voltage source And a slave latch, an output buffer using a high voltage source as a voltage source, and a level conversion of a low voltage signal input from the slave latch interposed between the slave latch and the output buffer to a high voltage signal. A level conversion circuit for outputting to the output buffer.

According to a nineteenth aspect of the present invention, in the semiconductor integrated circuit according to the seventeenth aspect, the scan test flip-flop circuit having the level conversion circuit among the scan test flip-flop circuits includes a low voltage source. A data input selection circuit for selecting any one of a plurality of input data by a clock as a voltage source;
A low voltage source as a voltage source, a series-connected master latch and a slave latch for inputting a signal from the data input selection circuit, an output buffer using a high voltage source as a voltage source, and the slave latch and the output buffer. A level conversion circuit interposed therebetween for converting a low-voltage signal input from the slave latch into a high-voltage signal and outputting the converted signal to the output buffer.

According to a twentieth aspect of the present invention, in the semiconductor integrated circuit of the thirteenth, fifteenth, eighteenth, or nineteenth aspect, the level conversion circuit includes two PMOS transistors, The gate of one of the PMOS transistors is connected to the drain of the other PMOS transistor, and the drain of the one PMOS transistor is connected to the gate of the other PMOS transistor. The sources of the two PMOS transistors are connected to a high-voltage source, and the two NMOS transistors receive, at their gates, the complementary signal of a slave latch that outputs a complementary signal. Each drain is connected to each drain of the two PMOS transistors, and the two NMOS transistors are connected. Each source of the NMOS transistor is grounded, and outputs the potential of each drain of the two NMOS transistors as a signal.

[0032] In addition, in the invention according to claim 21,
Claim 13, Claim 15, Claim 18, or Claim 1
9. The semiconductor integrated circuit according to item 9, wherein the level conversion circuit comprises:
It comprises two PMOS transistors and two PMOS inverters. Each of the PMOS inverters comprises one PMOS transistor and one NMOS transistor connected in series. NMOS
The two gates of both transistors are used as input terminals, and the serial connection of the PMOS and NMOS transistors is used as an output terminal. Complementary signal is input to the input terminals of the two PMOS inverters. The complementary signal of the slave latch that outputs
The type transistor has its two drains connected to the sources of the PMOS transistors of the two CMOS type inverters, the respective sources connected to a high voltage source, and the two C type transistors.
The source of the NMOS transistor of the MOS inverter is grounded, the output terminal of each of the PMOS transistors is connected to the gate of the PMOS transistor on the side not connected in series, and the output terminal of each of the two PMOS inverters is It is characterized by outputting a potential as a signal.

According to a twenty-second aspect of the present invention, in the semiconductor integrated circuit of the tenth, eleventh or twelfth aspect, the low voltage source and the high voltage source are each input from outside. I do.

According to a twenty-third aspect of the present invention, in the semiconductor integrated circuit according to the tenth, eleventh or twelfth aspect, the semiconductor integrated circuit further includes an input / output pad arrangement region and an internal core. A plurality of registers and a plurality of combinational circuits are arranged in the core section, and a cell section of the memory is arranged.

With the above configuration, the logic synthesizing method and the semiconductor integrated circuit according to claims 1 to 23 have the following operations. That is, the semiconductor integrated circuit includes a large number of registers and a large number of combinational circuits located between the registers, and some of the combinational circuits have a critical path. A level conversion circuit is arranged in a register located before the combinational circuit having the critical path, that is, a register for transmitting data to the combinational circuit, and the combinational circuit having the critical path is driven by a high voltage source. Other combinational circuits having no critical path are driven by a low voltage source.

Here, since the entire combinational circuit having a critical path is driven by a high power supply, the time delay of the critical path can be suppressed to a value less than the delay upper limit allowable in design. Also, since one level conversion circuit is arranged in a register located in the preceding stage of the combinational circuit having a critical path, the number of required level conversion circuits is smaller than in the case where only the critical path is driven by a high voltage source. And the design of the semiconductor integrated circuit becomes extremely easy. Moreover, even if the entire combinational circuit having a critical path is driven by a high voltage source, the number of combinational circuits having the critical path is extremely small when viewed from the entire combinational circuit. You.
On the other hand, since many combinational circuits having no critical path are driven by a low power supply, power consumption is significantly reduced. As a result, low power consumption is achieved in the entire semiconductor integrated circuit.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of an image processing apparatus A having a semiconductor integrated circuit according to the present invention. In FIG. 1, reference numeral 10 denotes an A / D converter for converting an external signal from analog to digital, 11 denotes a general-purpose DRAM, and 12 denotes a semiconductor integrated circuit of the present invention, which takes out data from the DRAM 11 or stores data. A first semiconductor integrated circuit 13 for performing image processing, 13 is a general-purpose control microcomputer for controlling the first semiconductor integrated circuit 12, and 14 receives a signal from the first semiconductor integrated circuit 12 to further perform image processing. This is a second semiconductor integrated circuit to be performed.

Reference numeral 15 designates, for example, 3 V
The high-voltage source 16 is also a low-voltage source, for example 2 V, externally arranged. The image processing apparatus A shown in FIG. 1 includes a high-voltage line 17 connected to the high-voltage source 15 and the low-voltage source 1.
6 connected to the low-voltage wiring 18. In order to reduce the power consumption of the image processing apparatus A, the low voltage source 16 is used as a voltage source for the first and second semiconductor integrated circuits 12 and 14 for image processing. It is supplied only to the first and second semiconductor integrated circuits 12 and 14. On the other hand, the high voltage of the high-voltage wiring 17 is applied to other general-purpose circuits 10, 1
1, 13 are supplied. Since the interface voltage between the circuits 10 to 14 needs to be high, the high voltage wiring 17
High voltage is applied to two semiconductor integrated circuits 12, 1 for image processing.
4 as well.

The low voltage source 16 may be an internal low voltage source in which the voltage of the high voltage wiring 17 is reduced by an internal transistor by the threshold voltage. The configuration is described in, for example,
96369, the details of which are omitted. In this case, the low voltage source 16 arranged outside is unnecessary.

The first semiconductor integrated circuit 1 for image processing
FIG. 2 shows the internal configuration of No. 2. In the figure, reference numeral 20 denotes a chip, 21... Are a plurality of input / output pads arranged on the outer periphery of the chip 20, and 22 is the plurality of input / output pads 2.
The internal core portion 22 is provided with five functional blocks A to E except for the arrangement region of 1. The functional blocks A to D are arithmetic processing circuits that perform different arithmetic processing, and the functional block E is, for example, a ROM.
, A small-capacity memory cell such as a RAM.

The present invention is applied to the functional blocks A to D other than the functional block E including the memory cell section in the internal core section 22 in the first semiconductor integrated circuit 12 for image processing. .

FIG. 3 shows a logic circuit diagram of any one of the functional blocks (for example, A) of the first semiconductor integrated circuit 12.

The functional blocks (part of the semiconductor integrated circuit) shown in FIG. 14 show a logic circuit obtained by performing logic synthesis from the RTL description shown in FIG. In the figure, reference numerals 2, 4, 6, and 8 denote flip-flop circuits constituting registers r1, r2, r3, r4 described in the RTL of FIG. 24, respectively. Reference numerals 1, 3, 5 and 7 denote combination circuits func1, func2,
It is a combinational circuit that constitutes func3 and func4 and is located between the registers r1 to r4 or at the preceding stage. In FIG. 3, for the sake of simplicity, the output of each combinational circuit is input only to the flip-flop circuit at the next stage, but the signal may be transferred to another combinational circuit.

The flip-flop circuits 2, 6 and 8 are 2V systems using the 2V low voltage source 16 as a voltage source.
The remaining flip-flop circuit 4 has a voltage source of 2V / 3 using both power sources of a low voltage source 16 of 2V and a high voltage source 15 of 3V.
It is a V system. The 2V / 3V flip-flop circuit 4 has a level conversion circuit as described later, and the 2V flip-flop circuits 2, 6 and 8 do not have a level conversion circuit. Further, the combination circuits 1, 3 and 7 are 2V combination circuits (first circuit) using a 2V low voltage source 16 as a voltage source.
The remaining combinational circuit 5 has a 3V high-voltage power supply 15 and a 3V
This is a system combination circuit (second combination circuit).

In addition, 9 is a 2V clock buffer (clock supply means) using the 2V low voltage source 16 as a voltage source.
Wherein the four flip-flop circuits 2, 4,.
Clock is supplied to 6 and 8.

FIG. 4 shows the configuration of the flip-flop circuits 2, 6, and 8 having no 2V level conversion circuit. In the figure, reference numeral 30 denotes a master latch for receiving one external signal D, and 31 denotes a slave latch which is connected in series to the output side of the master latch 30 and outputs two complementary signals. The slave latch 31 forms a temporary data storage unit 36. 32 is an output buffer connected to the output side of the slave latch 31, and 33 is an internal clock generation circuit (clock supply means) for generating complementary internal clocks CK and NCK from a clock CLK input from the outside. The circuits 30 to 33 are a 2V system using the 2V low voltage source 16 as a voltage source.

FIG. 5 shows a configuration of the flip-flop circuit 4 having the 2V / 3V system level conversion circuit. The flip-flop circuit 4 shown in FIG.
A master latch 30 and a slave latch 31 connected in series with the same configuration as the flip-flop circuit 2 of the system, an internal clock generation circuit 33, an output buffer 34 using the 3V high voltage source 15 as a voltage source, A level conversion circuit 35 is provided between the latch 31 and the output buffer 34. The level conversion circuit 3
Reference numeral 5 denotes a 2V / 3V system, in which the potential difference between complementary signals of the 2V system slave latch 31 is a low voltage (2V). Has a function of converting the level into a high voltage signal in which the potential difference between the signals is high voltage (3 V) and outputting the high voltage signal.

FIGS. 6A and 6B show a specific configuration of the level conversion circuit 35. FIG. In the level conversion circuit 35 of FIG. 3A, reference numerals 40 and 41 denote PMOS transistors, and reference numerals 42 and 43 denote NMOS transistors. One PMOS transistor 40 and one NMOS transistor 42 are connected in series. The other PMOS transistor 41 and the other NMOS transistor 43 are connected in series, and both series circuits are arranged between the high voltage source 15 of 3V and the ground. The gate of the one PMOS transistor 40 is connected to the NMO on the side not connected in series.
The drain of the S-type transistor 43 is connected to the drain of the NMOS transistor 42, and the gate of the other PMOS transistor 41 is connected to the drain of the NMOS transistor 42. The complementary output is taken from the drains of the NMOS transistors 42 and 43. With the above configuration, the PMOS transistor 40 and the NMOS transistor 42, and the PMOS transistor 41 and the NMOS transistor 43 each perform the function of an inverter. That is, when a low voltage of 2 V is supplied to the gate of one NMOS transistor 43 and 0 V is supplied to the gate of the other NMOS transistor 42 by the complementary output of the slave latch 31 in FIG. The NMOS transistor 43 is turned on and the other NMOS transistor 42 is turned off, and accordingly, one PMOS transistor 40 is turned on and the other PMOS transistor 41 is turned off. Is connected to the 3V high voltage source 15 and the drain of the other NMOS transistor 43 is grounded, so that a complementary output having a high potential difference of 3V is obtained. In the configuration of FIG. 6A, the through current from the 3V high voltage source 15 to the 2V low voltage source 16 and the through current from the 3V high voltage source 15 to 0V (ground) do not flow. Can be level-converted from a low voltage of 2V to a high voltage of 3V.

FIG. 6B shows a level conversion circuit 35 'having another specific configuration different from the above. The level conversion circuit 35 'shown in FIG.
Instead of the NMOS transistors 42 and 43, two NMOS inverters 45 and 46 are arranged. The two PMOS inverters 45 and 46 each have one
PMOS transistors 47 and 49 and one NMOS
It is formed by connecting the type transistors 48 and 50 in series. The input terminals of both the PMOS inverters 45 and 46, that is, both PMOS and NMOS transistors 47 and 4 connected in series.
The gates 8, 49 and 50 have the slave latch 31 of FIG.
Are output. An output terminal of one of the PMOS inverters 45, that is, a PMOS transistor 47
Is connected to the gate of the PMOS transistor 41 not connected in series with the PMOS inverter 45, and the output terminal of the other PMOS inverter 46 is connected to the PMOS transistor 40 not connected in series with the PMOS inverter 46. Are connected to the respective gates.
The outputs of the two PMOS inverters 45 and 46 are complementary outputs of the level conversion circuit 35 '. With the above configuration, 3V
The complementary output of the slave latch 31 shown in FIG. 5 is supplied from the low voltage of 2V without flowing a through current from the high voltage source 15 to the low voltage source 16 of 2V and a through current from the high voltage source 15 of 3V to the ground. The level can be converted to a high voltage of 3V. Further, P which constitutes the CMOS inverters 45 and 46
The MOS transistor is a 3V high voltage source 1 in a transient state.
5 to suppress the through current from flowing to ground.

As can be seen from the above description, the semiconductor integrated circuit shown in FIG.
3 is a low-voltage 2V system, has a 2V combination circuit 3 at its input, and has a 3V combination circuit 5 at its output.
Is a low-voltage / high-voltage system (2 V / 3 V system), and a flip-flop circuit 6 having a 3 V system combination circuit 5 at the input and a 2 V system combination circuit 7 at the output is a low voltage 2 V system. It is composed of a system.

In the above description, the registers r1, r2, r3, r4 are constituted by flip-flop circuits, but may be constituted by latch circuits instead of the flip-flop circuits. FIGS. 7 and 8 show a specific configuration of the latch circuit. FIG. 7 shows a low-voltage 2V-system latch circuit 51. A latch circuit 51 shown in FIG. 7 is a latch unit (temporary data storage unit) that receives and latches one signal D and obtains a complementary output.
52, an output buffer 53 connected to the output side of the latch unit 52, and an internal clock generation circuit 54 that generates an internal clock NG from the external clock G and outputs the internal clock NG to the latch unit 52. , An external clock G are also supplied to the latch unit 52. The above circuits 52 to 54 are 2V using the 2V low voltage source 16 as a voltage source.
System. FIG. 8 shows a low-voltage / high-voltage (2 V / 3 V) latch circuit 51 ′. The latch circuit 51 'in FIG.
Similarly to the configuration of the low-voltage 2V-system latch circuit, the latch unit 52 and the internal clock generation circuit 54 using the 2V low-voltage source 16 as a voltage source, and the output buffer 55 using the 3V high-voltage source 15 as a voltage source And an input signal interposed between the latch section 52 and the output buffer 55 to reduce the input signal to a low voltage (2 V).
Level conversion circuit 5 for converting the level from the high voltage (3V) to
6 is provided. The specific configuration of the level conversion circuit 56 is the same as the specific configuration shown in FIG. 6A or 6B.

Next, an algorithm of a logic synthesis method for logic-synthesizing the semiconductor integrated circuit shown in FIG. 3 based on connection information of logic cells will be described with reference to the logic synthesis apparatus of FIG. 9 and the flowcharts of FIGS. Will be explained.

FIG. 9 shows the overall schematic configuration of the logic synthesis device 60. In the figure, 61 is a reading unit, 62 is a translation unit, 63 is an optimization processing unit, 64 is a cell allocation unit, 65 is a timing verification unit, 66 is a circuit diagram generation unit, and 67 is an output unit. The reading unit 61 is the same as that shown in FIG.
RTL description (hardware description language) shown in
A netlist shown in FIG. 11 in which the signal transmission relationship between registers is clearly defined based on the connection information level of the logic cell based on the L description, or a schematic shown in FIG. The translation unit 62 converts the RTL description read from the reading unit 61 into a state transition diagram, a Boolean expression, a timing diagram, and memory specifications such as a memory type, the number of bits and the number of words.

The optimization processing unit 63 includes a state transition diagram optimization processing unit 63a for optimizing the obtained state transition diagram and a state for generating a circuit (state machine) corresponding to the optimized state transition diagram. A machine generator 63b, a compiler 63c for compiling a timing diagram obtained for compiling the obtained timing diagram, a composing unit 63d for composing a memory based on the specification of the obtained memory, Combining unit 63 for combining the interface unit based on the stored memory
e. Further, the optimization processing unit 63 includes the reading unit 6
If the input to 1 is an RTL description, the logic is optimized based on the obtained state machine, the obtained Boolean expression and the synthesized interface unit, and the connection information of the optimized logic cell is obtained. While generating, the reading unit 61
In the case where the input to is a netlist or schematic, there is a logic optimization unit 63f that optimizes the logic of the input netlist or schematic and generates connection information of the optimized logic.

The output section 67 externally outputs a netlist indicating the logic circuit of FIG. 3 or a logic circuit diagram (schematic) obtained by schematizing the netlist.

The present invention exists in the cell allocating section 64 shown in FIG. Next, based on the cell allocation (cell mapping) processing by the cell allocation section 64, ie, the cell connection information obtained by the logic optimization section 63f, FIG.
The algorithm for logically synthesizing the semiconductor integrated circuit shown in FIG. 1 will be described with reference to the flowchart of FIG. Note that FIG. 13 mainly illustrates features of the present invention.

In the figure, starting and step S
In 1 to S4 (first step), the combinational circuit whose signal propagation delay time is equal to or less than the designed delay upper limit value is combined with the first combinational circuit using the 2V low voltage source 16 as a voltage source, and vice versa. The combinational circuit whose signal propagation delay time exceeds the designed delay upper limit value is combined with the second combinational circuit using the 3V high voltage source 15 as a voltage source.

The first step is performed as follows in the present embodiment. That is, first, after reading the cell connection information from the logic optimizing unit 63f, an arbitrary flip-flop is used in step S1 by using each signal propagation delay time of the low-voltage (2V) flip-flop circuit and the combinational circuit. The signal propagation delay time in the signal propagation path from the clock input of the flip-flop circuit to the data input of the next flip-flop circuit is estimated for each signal propagation path. The estimation of the signal propagation delay time is performed, for example, by using a logic (AND circuit, NO
(R circuit or NOT circuit, etc.), for example, the type of logic, the number of inputs, and the number of logic stages are extracted, and based on the logic-related information and the cell technology, signal propagation when each logic is mapped to a cell. This is performed by calculating and estimating the delay time. Next, in step S2, it is determined whether or not the estimation result of the signal propagation delay time is equal to or less than the upper limit value of the design delay. If the result is equal to or less than the upper limit value, the combinational circuit is switched in step S3 to the low voltage (2V) logic cell. Mapping to a combinational circuit (first combinational circuit) of a library (hereinafter, referred to as lib), and when the estimation result exceeds the upper limit of the delay in design, the combinational circuit is switched to a high voltage (3
V) This is performed by mapping to a combinational circuit of lib (a second combinational circuit).

Subsequently, the following processing is performed in steps S5 and S6 (second step). That is, in step S5, the combination circuit of the 2V system and the combination circuit of the 3V system are mixed so that the output of the combination circuit of the low voltage system (2V system) becomes the input of the combination circuit of the high voltage system (3V system). It is checked whether or not there is a mixture of the above shapes. In step S6, the 2V combination circuit (first combination circuit) is set to 3V
The mapping is performed again so as to be replaced by the combination circuit of ib (the second combination circuit).

Thereafter, in the register, since the voltage systems of the combinational circuits located on the input side and the output side thereof have already been determined by the above-described logic synthesis, steps S7 to S9 (third step) are performed.
In step (3), the following processing is performed. That is, it is checked whether or not each register converts the level of the potential from the input of the low voltage (2 V) to the output of the high voltage (3 V). If the level is to be converted, the register (the flip-flop circuit) that performs the level conversion in step S8. 4 is mapped to the 2V / 3V-system flip-flop circuit of FIG. 5 or the 2V / 3V-system latch circuit of FIG. 8, and if the level is not to be converted, the register whose level is not converted is replaced with the 2V / 3V of FIG. 7 is mapped to the flip-flop circuit of the system or the latch circuit of the 2V system in FIG.

FIG. 14 shows a modification of the logic synthesis method shown in FIG. In the logic synthesis method of FIG. 13, the signal propagation delay time is estimated in the first step, and the combinational circuit is mapped to a low-voltage (2V) combinational circuit or a high-voltage (3V) combinational circuit according to the estimation result. Instead of
In the present modified example, first, in step S10, mapping is performed on a 2V lib combinational circuit (first combinational circuit), and then, in step S11, it is determined whether or not the result of the combination is equal to or less than a design delay upper limit value. Only when the delay exceeds the upper limit value, mapping is performed again in step S12 so that the combined circuit of 2Vlib (first combined circuit) is replaced with a combined circuit of 3Vlib (second combined circuit). The second and third steps of this modified example are the same as the logic synthesis method of FIG. 13 described above, and a description thereof will be omitted.

FIG. 15 shows a modification in which a part of the logic synthesis algorithm shown in FIG. Hereinafter, the logic synthesis algorithm of FIG. 15 will be described with respect to portions different from FIG. In the first step, step S1
3 is added. This step S13 is equivalent to step S2
In the case where the estimation result of the signal propagation delay time exceeds the upper limit value, all the low voltages (2 V) li exceeding the upper limit value are set in advance.
b), and after this step S13, the extracted first combinational circuit is combined in step S4 with a high-voltage (3V) lib combinational circuit (the second combinational circuit). Circuit). In the second step, step S14 is added. This step S14 is a step of, in the case where the combination circuit of the 2V system and the combination circuit of the 3V system are mixed in step S5, extracting all of the mixed circuit (first combination circuit) of the 2V system in advance. After step S14, the extracted first combinational circuit is mapped again to the high-voltage (3V) lib combinational circuit (second combinational circuit) in step 6. Further, in the second step, after re-mapping to the second combinational circuit in the step 6,
An algorithm returning to step 5 is added. This algorithm takes into consideration that the combination of the 2V system combination circuit and the 3V system combination circuit may newly occur due to the mapping to the 3V system combination circuit in step 6 described above. This mixture is determined in step 5, and if there is this mixture, again in steps S14 and S6,
This is for repeating the extraction of the mixed circuit of the mixed 2V system and the re-mapping of the extracted first combination circuit to the combination circuit of the high voltage (3V) lib (the second combination circuit).

FIG. 16 shows a modification in which a part of the logic synthesis algorithm shown in FIG. As in the case of FIG. 15, in this modification, when the signal propagation delay time exceeds the upper limit (step S11), the combination circuit (the first combination) of all low-voltage (2V) libs exceeding the upper limit is used in advance. Step 15 for extracting the circuit
If the combination circuit of the 2V system and the combination circuit of the 3V system are mixed together (step S5), all of the mixed 2V system combination circuits (first combination circuits) are extracted in advance. Step 16 is added to the second step. In this second step, the 2V-system combination circuit and the 3V-system combination circuit are added due to the remapping to the 3V-system combination circuit (step 6). In consideration of the fact that a mixture of
An algorithm is added to return to step 5 for determining the presence or absence of the coexistence after the processing of.

Therefore, in each algorithm of the logic synthesis method shown in FIGS. 15 and 16, for example, as shown in FIG. 17A, when the signal propagation delay time or the estimation result exceeds the upper limit value, the first After mapping the combinational circuit to the second combinational circuit indicated by hatching in the figure, when the combination circuit of the 2V system and the combination circuit of the 3V system coexist,
As shown in FIG. 4B, the mixed first combinational circuit is remapped to a second combinational circuit indicated by hatching in the figure, and then the 2V-system combination circuit and the 3V-system combination circuit are re-mapped by the remapping. In the case where a new combination is generated, the first combinational circuit is re-mapped to a second combinational circuit indicated by hatching in the figure as shown in FIG. When the combination of the 2V-system combination circuit and the 3V-system combination circuit, in which the output of the flip-flop circuit becomes the input of the 3V-system combination circuit, is eliminated, then each flip-flop circuit receives the low voltage (2V) input from the high voltage 3V)
When the potential is level-converted to the output of (1), the flip-flop circuit for level conversion is mapped to a 2V / 3V-system flip-flop circuit indicated by hatching in the figure, as shown in FIG.

FIG. 18 shows an embodiment in which the logic synthesis method of FIG. 13 is applied to a semiconductor integrated circuit having another configuration different from the semiconductor integrated circuit of FIG.

FIG. 11 shows a semiconductor integrated circuit using a scan test flip-flop circuit as a register.
Scan flip-flop circuits 80, 81, 82, 83
And 84 are 2V / 3V scan flip-flop circuits, and the other scan flip-flop circuits are 2V scan flip-flop circuits.

FIG. 19 shows a configuration of a 2V-system scan flip-flop circuit. The scan flip-flop circuit shown in the figure includes a multiplexer 90 in addition to the configuration of the low-voltage (2 V) flip-flop circuit shown in FIG. The multiplexer 90 uses the low voltage source 16 of 2V as a voltage source, and receives two data D and DT by a control signal SE.
Is selected and output. The data selected by the multiplexer 90 is input to the master latch 30. About the other structure, the same code | symbol is attached | subjected to the same part as the structure of the flip-flop circuit shown in FIG. 4, and the description is abbreviate | omitted.

FIG. 21 shows a 2V-system scan flip-flop circuit having another configuration. The 2V-system scan flip-flop circuit shown in FIG. 9 includes a data input selection circuit 91 in addition to the configuration of the flip-flop circuit shown in FIG. The data input selection circuit 91 is connected to the master latch 30
When the data D is input by the external clock CLK, the input of the other data DT is inhibited. When the master latch 30 inhibits the input of the data D, the other data DT is input by the other clock CLKT. Output to the master latch 30. In the figure, reference numeral 92 denotes an internal clock generation circuit which receives the two types of external clocks CLK and CLKT to generate two types of internal clocks CK and NCK, and applies the internal clocks CK and NCK to a master latch 30 and a slave. Latch 31
Output to

FIG. 20 shows a scan flip-flop circuit of the 2V / 3V system. 19 includes the same circuits as the master latch 30, slave latch 31, internal clock generation circuit 33, and multiplexer 90 of the 2V-system scan flip-flop circuit in FIG. It has an output buffer 95 as a source and a level conversion circuit 96 of a 2V / 3V system. The 2V / 3V system level conversion circuit 96 is interposed between the slave latch 31 and the output buffer 95. The specific configuration of the 2V / 3V system level conversion circuit 96 is the same as that shown in FIG. 6A or 6B.

FIG. 22 shows another 2V / 3V scan flip-flop circuit. The scan flip-flop circuit shown in FIG. 21 includes the master latch 30, the slave latch 31, and the scan flip-flop circuit of the 2V system shown in FIG.
Internal clock generation circuit 92 and data input selection circuit 91
And an output buffer 97 using a 3V high voltage source as a voltage source, and a 2V / 3V system level conversion circuit 98. The 2V / 3V level conversion circuit 98 is interposed between the slave latch 31 and the output buffer 97. The specific configuration of the 2V / 3V level conversion circuit 98 is the same as that shown in FIG. 6A or 6B.

A method of logically synthesizing the semiconductor integrated circuit of FIG. 18 will be described. Assume that combinational circuits 86, 87 and 88 have a critical path. According to the algorithm of the logic synthesis method shown in FIG. 13, the combination circuits 86 and 8 are mapped in the first mapping stage (first step) of the combination circuit.
7 and 88 are mapped to a 3V lib combinational circuit (second combinational circuit), and the other combinational circuits are mapped to a 2V lib combinational circuit (first combination circuit).

Next, in the remapping stage of the combinational circuit (second step), the combinational circuit 89 is remapped to the combinational circuit of 3 Vlib. Then, at the stage of register (flip-flop circuit) mapping (third step), the flip-flop circuits 80, 81, 82, 83 and 84 are formed.
Is mapped to a 2V / 3V flip-flop circuit,
Another flip-flop circuit is mapped to a 2V-system flip-flop circuit.

In the semiconductor integrated circuit of FIG. 18 generated as described above, a 2V low-voltage logic lib and a 3V high-voltage logic lib are mixed, but the voltage source of each combinational circuit is 2V. Of the low voltage source 16 or the high voltage source 15 of 3V, and the level conversion of the voltage from the low voltage of 2V to the high voltage of 3V is performed by a level conversion circuit in a scan flip-flop circuit of a 2V / 3V system. Done.

The semiconductor integrated circuit of FIG. 18 has eight scan chains indicated by broken lines in the figure, in which signals are transmitted only through a plurality of scan flip-flop circuits without passing through combinational circuits in the scan test mode. For example, input
In the scan chain connected to Si3, the scan flip-flop circuit 81 of the 2V / 3V system performs level conversion from a low voltage of 2V to a high voltage of 3V, as in the normal mode, and the next stage scan flip-flop circuit of the scan flip-flop circuit 81 Circuit 99 from 3V high voltage to 2
Level conversion is performed to a low voltage of V. Therefore, even when the scan flip-flop circuit shown in FIG. 20 or FIG. 22 is used, even in the scan test mode in which the signal transmission path is different from the normal path (that is, the path passing through the combinational circuit), 2V
The scan test of the semiconductor integrated circuit of the present invention in which the low-voltage system and the 3V high-voltage system coexist is possible.

In the above description, the present invention has been applied to the functional block A constituting the memory cell unit E other than the memory cell unit E formed in the internal core unit 22 of the chip 20, but to the other functional blocks BD. It goes without saying that a plurality of functional blocks A to
Needless to say, the present invention can be similarly applied between D.

Therefore, according to the logic synthesis method of the present embodiment, the entire combinational circuit having a critical path is a 3V high voltage system, and the level conversion circuit is arranged in the register at the preceding stage. Unlike the case where only the critical path is driven by the high voltage source in the combinational circuit having the critical path, it is not necessary and necessary to individually determine the positions of the plurality of level conversion circuits in the combinational circuit having the critical path. Since the number of level conversion circuits can be reduced, the design of a semiconductor integrated circuit becomes extremely easy. Moreover, although the entire combinational circuit having a critical path is driven by the high voltage source 15 of 3 V, the number of the combinational circuits having the critical path is extremely small compared to the number of the combinational circuits provided in the semiconductor integrated circuit. Therefore, while the increase in current consumption can be suppressed to a small level, all the combinational circuits having no critical path are driven by the low voltage source 16 of 2 V, so that the current consumption of the semiconductor integrated circuit as a whole can be reduced, and low power consumption can be achieved. Is possible.

The semiconductor integrated circuit according to the present embodiment shown in FIG.
A comparison is made with the conventional semiconductor integrated circuit of FIG. In the conventional semiconductor integrated circuit shown in FIG.
2, 104 and 106 have a signal propagation delay time of 6n
s, 12 ns, 18 ns, 8 ns, and the delay time from the clock input of the flip-flop circuit to the data output is
Assuming 2 ns, the maximum delay of the combinational circuit is 104
25, the maximum operating frequency of the circuit of FIG. 25 is 1000 / (2 + 18) = 50 MHz.

On the other hand, in the semiconductor integrated circuit of the present embodiment shown in FIG. 3, the delay time of the combinational circuit 5 having a critical path is the same as that of the conventional voltage system (3 V).
The same delay time is 18 ns. The delay time of the combinational circuits 1, 3 and 7 without a critical path reduced the power supply voltage from a high voltage of 3V to a low voltage of 2V,
It increases as the delay of the logic cell increases. still,
In the semiconductor integrated circuit shown in FIG.
It is assumed that the delay time of the cell is 1.5 times as large as that of the high voltage source of 3V with respect to the high voltage source of 3V. The maximum of the delay times of the combination circuits 1, 3 and 7 having no critical path is 18 ns of the combination circuit 3.

The low voltage source 16 of 2V and the high voltage source 15 of 3V
As a result, the maximum delay of the combinational circuit is 18 ns for the combinational circuit 3 having no critical path and the combinational circuit 5 having the critical path. Since each signal propagation delay time from the clock input to the data output of the flip-flop circuits 2 and 4 is 2 ns, and the delay time of each of the combinational circuits 3 and 5 is 18 ns, the maximum operation of the semiconductor integrated circuit of this embodiment is The frequency is 1000 / (2 + 18) = 50 MHz, and the combinational circuits 1 and 3 without a critical path
And 7 are driven by the low voltage source 16 of 2 V, the same maximum operating frequency as that of the conventional semiconductor integrated circuit can be obtained.

FIG. 23 shows the delay between the clock input of the flip-flop circuit and the data input of the next-stage flip-flop circuit in the semiconductor integrated circuit of this embodiment of FIG. 3 and the conventional semiconductor integrated circuit of FIG. That is, the distribution of the signal propagation delay time obtained by adding the delay times of the register and the combinational circuit is shown. FIG. 2A shows a delay distribution of a conventional 3 V voltage semiconductor integrated circuit, and FIG.
6 is a delay distribution of a V-type and 3V-type mixed semiconductor integrated circuit. In a conventional semiconductor integrated circuit, only the power supply voltage is 3 V
When the high voltage system is changed from a high voltage system to a low voltage system of 2 V, the maximum delay time is changed from 20 ns to 30 ns, and the delay time of the critical path exceeds the upper limit of the designed delay of 20 ns.
In the semiconductor integrated circuit of the present embodiment, the delay time is 20 ns
Only the combinational circuits with critical paths exceeding
Since the combinational circuit that is changed to the high voltage system of V and has no other critical path is a low power system of 2 V, the upper limit of the design delay of 20 ns can be satisfied. FIG. 11B shows the delay distribution at this time.

Next, the power consumption of the conventional semiconductor integrated circuit is compared with that of the semiconductor integrated circuit of the present invention. The power consumption of the conventional semiconductor integrated circuit is P, the power supply is a dual power supply of a high voltage source of 3 V and a low voltage source of 2 V, the ratio of the critical path in the entire circuit is 10%, and the 2V / 3V flip-flop of the present invention. Assuming that the power consumption of the flip-flop circuit is different from that of the conventional flip-flop circuit by 10%,
As shown in the following equation, the power consumption of the semiconductor integrated circuit of the present invention is [Px (2/3)] ² x 0.9 + Px 1.1 x 0.1 = Px 0.51, and the power consumption is reduced by 49%.

Further, assuming that the ratio of the critical path to the entire circuit is 5% under the above conditions, the power consumption of the semiconductor integrated circuit of the present invention is expressed by the following equation: [Px (2/3)] ² x 0.95 + Px 1.1 x 0.05 = P x 0.48, and the power consumption is reduced by 52%.

Next, the circuit scale of the conventional semiconductor integrated circuit is compared with that of the semiconductor integrated circuit of the present invention.

The circuit scale of the conventional semiconductor integrated circuit is S, the proportion of the flip-flop circuit in the semiconductor integrated circuit is 20%, and the proportion of the flip-flop circuit having the level conversion circuit in the whole flip-flop circuit is 10
%, And if the 2V / 3V flip-flop circuit of the present invention has an area increase of 10% due to a difference in circuit configuration from the conventional flip-flop circuit, the circuit scale of the semiconductor integrated circuit of the present invention is expressed by the following equation. Then, S x 0.8 + S x 0.18 + S x 1.1 x 0.02 = S x 1.002, and the increase in the circuit scale is limited to 0.2%.

Further, assuming that the ratio of the flip-flop circuit having the level conversion circuit in the whole flip-flop circuit is 5% under the above-mentioned conditions, the circuit scale of the semiconductor integrated circuit of the present invention is expressed by the following equation. , S x 0.8 + S x 0.19 + S x 1.1 x 0.01 = S x 1.001, and the increase in the circuit scale remains at 0.1%.

[0087]

As described above, according to the logic synthesizing method according to the first to ninth aspects of the present invention, logic synthesis is performed so that the entire combinational circuit having a critical path is driven by a high power supply. Logic synthesis is performed so that the signal propagation delay time of the critical path can be suppressed to less than the upper limit of the delay allowed by the design, and one level conversion circuit is arranged in a register located in front of the combinational circuit having the critical path. Therefore, compared with the case where only the critical path is driven by a high voltage source, the number of level conversion circuits required is reduced and the top-down design and the scan test from the function description are possible. The design of the integrated circuit can be made extremely easy.

According to the semiconductor integrated circuit according to the tenth to twenty-third aspects, in this semiconductor integrated circuit, only a part of the combinational circuits having a critical path is entirely driven by a high voltage source. Therefore, the signal propagation delay time of the critical path can be suppressed to less than the delay upper limit allowed by design, and even if the entire combinational circuit having the critical path is driven by a high voltage source,
The number of combinational circuits having the critical path is extremely small in view of the entire combinational circuit, and the increase in power consumption is suppressed to a small extent. On the other hand, many other combinational circuits having no critical path are driven by a low voltage source. Therefore, power consumption of the entire semiconductor integrated circuit is significantly reduced, and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is an overall schematic configuration diagram of an image processing system.

FIG. 2 is an overall schematic configuration diagram of a semiconductor chip.

FIG. 3 is a diagram illustrating a connection relationship between a plurality of registers and a plurality of combinational circuits of the semiconductor integrated circuit according to the embodiment of the present invention;

FIG. 4 is a configuration diagram of a flip-flop circuit having no level conversion circuit.

FIG. 5 is a configuration diagram of a flip-flop circuit having a level conversion circuit.

FIG. 6 is a diagram showing a specific configuration of a level conversion circuit.

FIG. 7 is a configuration diagram of a latch circuit having no level conversion circuit.

FIG. 8 is a configuration diagram of a latch circuit having a level conversion circuit.

FIG. 9 is a diagram showing an overall schematic configuration of a logic synthesis device.

FIG. 10 is a diagram illustrating a hardware description language.

FIG. 11 is a diagram showing a net list.

FIG. 12 is a diagram showing a schematic.

FIG. 13 is a diagram illustrating a logic synthesis method of a semiconductor integrated circuit.

FIG. 14 is a diagram illustrating another logic synthesis method of the semiconductor integrated circuit.

FIG. 15 is a diagram showing a modification of the logic synthesis method of FIG.

FIG. 16 is a diagram illustrating a modification of the other logic synthesis method in FIG. 14;

FIG. 17 is an explanatory diagram of mapping to a flip-flop circuit having a second combinational circuit and a level conversion circuit.

FIG. 18 is a diagram showing another semiconductor integrated circuit to be developed.

FIG. 19 is a configuration diagram of a scan flip-flop circuit having no level conversion circuit.

FIG. 20 is a configuration diagram of a scan flip-flop circuit having a level conversion circuit.

FIG. 21 is a configuration diagram of another scan flip-flop circuit having no level conversion circuit.

FIG. 22 is a configuration diagram of another scan flip-flop circuit having a level conversion circuit.

FIG. 23 is a diagram showing a signal propagation delay time of a semiconductor integrated circuit according to a conventional example and an example of the present invention and a distribution of the number of combinational circuits having the delay time.

FIG. 24 is a diagram showing a description of a register transfer level.

FIG. 25 is a diagram showing a logic circuit of a conventional semiconductor integrated circuit.

FIG. 26 is a diagram showing an arrangement position of a level conversion circuit when only a critical path is driven by a high voltage source in an arbitrary semiconductor integrated circuit.

FIG. 27 is a diagram showing an arrangement position of a level conversion circuit in a case where only a critical path is driven by a high voltage source in another arbitrary semiconductor integrated circuit.

[Explanation of symbols]

1, 3, 7 First combination circuit 5 Second combination circuit 2, 4, 6, 8 Flip-flop circuit (register) 9 Clock buffer (clock supply means) 15 High voltage source 16 Low voltage source 22 Internal core unit 30 Master latch 31 Slave latch 33, 3354, 92 Internal clock generation circuit 35, 3556, 96, 98 Level conversion circuit 36 Data temporary storage unit 40, 41 PMOS transistor 42, 43 NMOS transistor 45, 46 CMOS inverter 47, 49 PMOS Type transistors 48, 50 NMOS type transistors 51, 51 'Latch circuit (register) 52 Latch section 65 Timing verification section 80-84 Scan test flip-flop circuit (register) 90 Multiplexer 91 Data input selection circuit

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[Procedure amendment]

[Submission date] July 9, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention Semi-conductor integrated circuit

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a modified <br/> good semi conductor integrated circuits, in particular, about the semiconductor integrated circuits that operate with low power consumption
You.

[0002]

2. Description of the Related Art Today, in the design of a semiconductor integrated circuit, a semiconductor integrated circuit to be developed is represented by a function description at a register transfer level (hereinafter, referred to as RTL), and the logic is synthesized using the RTL description. ,
A top-down design for generating a semiconductor integrated circuit to be developed is employed.

FIG. 24 shows a conventional RTL description, and FIG. 25 shows a logic circuit (semiconductor integrated circuit) generated by logic synthesis using the RTL description.

[0004] The RTL description in FIG. 24 is a description clearly defining data transfer between a plurality of registers at a functional level. In the RTL description shown in the figure, r1, r2, r3, and r4 are registers, func1, func2, func3, and func4 are descriptions of the function of a combinational circuit between the registers. It describes the connection relationship.

When synthesizing logic from the RTL description of FIG. 24, a circuit is determined on a trade-off curve of area and speed by giving constraints on area or speed.

In the logic circuit shown in FIG. 25 generated from the RTL description, 101, 103, 105, and 107 are flip-flops in which registers r1, r2, r3, and r4 specified in the RTL description are mapped by logic synthesis. 24, the registers r1 and r specified in the RTL description of FIG.
Corresponds directly to 2, r3, r4. 108 is the clock buffer, 10
0, 102, 104, and 106 are func1, func1, of the RTL description in FIG.
This is a combinational circuit corresponding to func2, func3, and func4. The combinational circuits 100, 102, 104 and 106 correspond to the RT shown in FIG.
It is mapped from the function description of L as one circuit on the curve of trade-off between area and speed.

[0007]

By the way, the power consumption P of the semiconductor integrated circuit can be expressed as follows: operating frequency f, load capacitance C,
As the voltage and V [Equation 1], represented by [Equation 1] P = f x C x V 2. Therefore, there are three methods for reducing the power consumption of the semiconductor integrated circuit: lowering the operating frequency, lowering the load capacity, or lowering the power supply voltage. The reduction effect due to the reduction in the power supply voltage is the largest.

However, when the power supply voltage is set low, the delay time of the critical path having the maximum delay time among many paths constituting the logic circuit also increases.

[0009] Therefore, for example, JP-A-5-299624, a logic gate sufficient in the slow operation of a number of logic gates driven by a low voltage source, the other high-speed operation of the logic gates required by the high-voltage source The driving technology is disclosed
Low voltage and high voltage
The use of dual power sources with a pressure source is not disclosed.

An object of the present invention is to provide a semiconductor to be developed.
Critical path delay time of each combinational circuit of integrated circuit
Semiconductor integrated circuits that operate with low power consumption without increasing
To provide a road.

[0011]

That is, the present invention relates to a method disclosed in
Utilizing the technology disclosed in JP-A-5-299624,
Only the logic gates that make up the critical path
Driven by a voltage source and other logic gates driven by a low voltage source.
Causes the maximum delay time of the critical path to increase.
Uses a low-voltage power supply without increasing the current consumption of the entire semiconductor integrated circuit
To reduce power consumption. However, the present invention has room for further improvement.

The details of the improvements are as follows. As described above, when data is transmitted from a low-speed operation type logic gate driven by a low voltage source to a high-speed operation type logic gate driven by a high voltage source, for example, see Japanese Patent Application Laid-Open No. Hei 5-6796.
As disclosed in Japanese Unexamined Patent Application Publication No. 2003-163, a level conversion circuit for converting the output level of a logic gate driven by a low voltage source into a high level needs to be disposed between the two logic gates. However, since each of the combinational circuits shown in FIG. 25 is a circuit composed of a large number of logic gates as shown in, for example, FIG. 26 or FIG. Assuming that the path shown in FIG. 2 is driven by a high voltage source, the critical path is driven by a plurality of positions (in FIG.
It is determined that a level conversion circuit is required at eight locations in FIG. 6 and at twelve locations in FIG. In a highly integrated semiconductor integrated circuit, the number of combination circuits is extremely large, and the number of logic gates constituting each combination circuit is also extremely large. Therefore, in such a highly integrated semiconductor integrated circuit, the number of positions requiring a level conversion circuit in one combinational circuit having a critical path is large, and the number of combinational circuits having a critical path is large. The number of positions requiring a level conversion circuit in the entire circuit is enormous. As a result, in the design of a highly integrated semiconductor integrated circuit, it is possible to determine and arrange the position where the level conversion circuit is required as described above using a combination circuit that is only partially limited. In the whole, the determination of the arrangement position of the level conversion circuit is complicated and troublesome, and it takes a long time, and the design becomes complicated .

[0013] In order to achieve the previous Symbol purpose of, in the present invention,
We focused on the following points. That is, first, the semiconductor integrated circuit is
As shown in FIG. 25, it is composed of a large number of registers and a large number of combinational circuits located between the respective registers. Therefore, if a level conversion circuit is arranged in the register, the plurality of combinational circuits have various locations, that is, critical paths. When driving with a high power supply, there is no need to arrange a level conversion circuit at each of a plurality of positions where the level conversion circuit is required, and the number of arrangement positions of the level conversion circuit can be reduced and reduced. by arranging a conversion circuit, a combination circuit which data is transmitted from the level converting circuit, although necessary to drive the combination circuits at high power is generated, in the semiconductor integrated circuit, the number of logic gates that are present in the critical path According to statistics that are about 5% of the number of logic gates constituting the entire integrated circuit, a combination of combinational circuits having a critical path Ratio less for the entire circuit causes,
Thus by noting not significantly incurring an increase in power consumption even when the combination circuits with a critical path is driven at a high power.

That is, the semiconductor integrated circuit according to the first aspect of the present invention.
The circuit includes a first logic gate driven by a low voltage source and a high voltage circuit.
A second logic gate driven by a pressure source.
Having a combinational circuit provided on each signal propagation path
Body integrated circuit, wherein the semiconductor integrated circuit is
Signal propagation delay time of a specific signal propagation path that becomes a calpus
Is provided to be less than the design delay upper limit value
A first combinational circuit having a second logic gate;
And features.

[0015] The invention according to claim 2 is the same as the above claim.
2. The semiconductor integrated circuit according to claim 1 , wherein
Are all composed of the first logic gates, and
Having a second combinational circuit that satisfies the delay upper limit of
Features.

[0016] Further, the invention according to claim 3 is the above-mentioned claim.
2. The semiconductor integrated circuit according to claim 1 , wherein the first combination
The logic gate on the signal propagation path of the path is the first logic gate.
And a second logic gate.
You.

[0017] In addition, the invention according to claim 4 is the above-mentioned claim.
Item 4. The semiconductor integrated circuit according to Item 3 , wherein the first combination
In the circuit, the output of the second logic gate is connected to the first logic gate.
The input of the port is connected.

[0018] In addition, the invention according to claim 5 is characterized in that:
2. The semiconductor integrated circuit according to claim 1 , wherein the first set
The input of the second logic gate in the matching circuit
The output of the logic gate is connected to the first combinational circuit.
Input of the first logic gate to the output of the second logic gate
The power is connected.

Further, the invention according to claim 6 is the same as the above claim.
2. The semiconductor integrated circuit according to claim 1 , wherein the first combination
All logic gates on the signal propagation path of the
It is characterized in that

Further, the invention according to claim 7 is the same as the above claim.
6. The semiconductor integrated circuit as set forth in claim 6 , wherein:
To the inputs of all the second logic gates on the signal propagation path
The output of the second logic gate is connected.
I do.

[0021] In addition, the invention according to claim 8 is the above-mentioned claim.
Item 2. The semiconductor integrated circuit according to Item 1 , wherein the first logic gate
Input a low-voltage output signal of the
Level-converted to a high-voltage signal and
It has a level conversion circuit for outputting.

[0022] In addition, the invention according to claim 9 provides the above-mentioned invention.
9. The semiconductor integrated circuit according to claim 8 , wherein the level change is performed.
The conversion circuit outputs a low-voltage output signal of the first logic gate.
While inputting and holding, the held low-voltage signal is
Level-converted to a high-voltage signal and
Features a register with a level conversion function to output
And

[0023] The invention according to claim 10 is the same as the above claim.
Item 10. The level converter according to Item 9,
Active registers are used for data from low voltage sources.
A storage unit, and storing the data at the time of using the high voltage source as a voltage source
Level conversion from low-voltage output signal to high-voltage output signal
And a level conversion circuit.

[0024]

According to the above construction, claims 1 to 10 are provided.
Semiconductors integrated circuit serial mounting exhibits the following effects. That is, in the combinational circuit having a click re <br/> Pharmaceuticals path, the critical
The logic gate on the signal propagation path that becomes the path is driven by high voltage
Therefore, the time delay of the critical path can be suppressed to less than the delay upper limit value allowable in design. In addition, the logic gate driven by the high voltage system passes through a signal propagation path.
In other combinational circuits including on the road, driven by low voltage system
Logic gates or logic gates driven by other high voltage systems
Includes, but the number of such combinational circuits is a semiconductor integrated circuit
Is extremely small as a whole from the viewpoint of the combination circuit provided in the above , the increase in power consumption is suppressed to a small extent. On the other hand, the remaining combinational circuits are driven by a low power supply, so that power consumption is significantly reduced. As a result, low power consumption is achieved in the entire semiconductor integrated circuit.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of an image processing apparatus A having a semiconductor integrated circuit according to the present invention. In FIG. 1, reference numeral 10 denotes an A / D converter for converting an external signal from analog to digital, 11 denotes a general-purpose DRAM, and 12 denotes a semiconductor integrated circuit of the present invention, which takes out data from the DRAM 11 or stores data. A first semiconductor integrated circuit 13 for performing image processing, 13 is a general-purpose control microcomputer for controlling the first semiconductor integrated circuit 12, and 14 receives a signal from the first semiconductor integrated circuit 12 to further perform image processing. This is a second semiconductor integrated circuit to be performed.

Reference numeral 15 denotes an externally arranged, for example, 3 V
The high-voltage source 16 is also a low-voltage source, for example 2 V, externally arranged. The image processing apparatus A shown in FIG. 1 includes a high-voltage line 17 connected to the high-voltage source 15 and the low-voltage source 1.
6 connected to the low-voltage wiring 18. In order to reduce the power consumption of the image processing apparatus A, the low voltage source 16 is used as a voltage source for the first and second semiconductor integrated circuits 12 and 14 for image processing. It is supplied only to the first and second semiconductor integrated circuits 12 and 14. On the other hand, the high voltage of the high-voltage wiring 17 is applied to other general-purpose circuits 10, 1
1, 13 are supplied. Since the interface voltage between the circuits 10 to 14 needs to be high, the high voltage wiring 17
High voltage is applied to two semiconductor integrated circuits 12, 1 for image processing.
4 as well.

The low voltage source 16 may be an internal low voltage source in which the voltage of the high voltage wiring 17 is reduced by an internal transistor by the threshold voltage. The configuration is described in, for example,
96369, the details of which are omitted. In this case, the low voltage source 16 arranged outside is unnecessary.

The first semiconductor integrated circuit 1 for image processing
FIG. 2 shows the internal configuration of No. 2. In the figure, reference numeral 20 denotes a chip, 21... Are a plurality of input / output pads arranged on the outer periphery of the chip 20, and 22 is the plurality of input / output pads 2.
The internal core portion 22 is provided with five functional blocks A to E except for the arrangement region of 1. The functional blocks A to D are arithmetic processing circuits that perform different arithmetic processing, and the functional block E is, for example, a ROM.
, A small-capacity memory cell such as a RAM.

The present invention is applied to the functional blocks A to D other than the functional block E composed of the memory cell section in the internal core section 22 in the first semiconductor integrated circuit 12 for image processing. .

FIG. 3 shows a logic circuit diagram of an arbitrary one functional block (for example, A) of the first semiconductor integrated circuit 12.

The functional block (part of the semiconductor integrated circuit) shown in FIG. 14 shows a logic circuit logically synthesized from the RTL description shown in FIG. In the figure, reference numerals 2, 4, 6, and 8 denote flip-flop circuits constituting registers r1, r2, r3, r4 described in the RTL of FIG. 24, respectively. Reference numerals 1, 3, 5 and 7 denote combination circuits func1, func2,
It is a combinational circuit that constitutes func3 and func4 and is located between the registers r1 to r4 or at the preceding stage. In FIG. 3, for the sake of simplicity, the output of each combinational circuit is input only to the flip-flop circuit at the next stage, but the signal may be transferred to another combinational circuit.

The flip-flop circuits 2, 6 and 8 are 2V systems using the 2V low voltage source 16 as a voltage source.
The remaining flip-flop circuit 4 has a voltage source of 2V / 3 using both power sources of a low voltage source 16 of 2V and a high voltage source 15 of 3V.
It is a V system. The 2V / 3V flip-flop circuit 4 has a level conversion circuit as described later, and the 2V flip-flop circuits 2, 6 and 8 do not have a level conversion circuit. Further, the combination circuits 1, 3 and 7 are 2V combination circuits (first circuit) using a 2V low voltage source 16 as a voltage source.
A combinational circuit), that is, a logic circuit constituting this combinational circuit.
The combination circuit 5 is a combination circuit driven by a low voltage of 2V , and the remaining combination circuit 5 is a 3V combination circuit using a 3V high-voltage power supply 15 as a voltage source (second combination Circuit), that is, the logic constituting this combinational circuit
A combination circuit in which all gates are driven by a high voltage of 3V .

In addition, 9 is a 2V clock buffer (clock supply means) using a 2V low voltage source 16 as a voltage source.
Wherein the four flip-flop circuits 2, 4,.
Clock is supplied to 6 and 8.

FIG. 4 shows the configuration of the flip-flop circuits 2, 6, and 8 having no 2V-system level conversion circuit. In the figure, reference numeral 30 denotes a master latch for receiving one external signal D, and 31 denotes a slave latch which is connected in series to the output side of the master latch 30 and outputs two complementary signals. The slave latch 31 forms a temporary data storage unit 36. 32 is an output buffer connected to the output side of the slave latch 31, and 33 is an internal clock generation circuit (clock supply means) for generating complementary internal clocks CK and NCK from a clock CLK input from the outside. The circuits 30 to 33 are a 2V system using the 2V low voltage source 16 as a voltage source.

FIG. 5 shows the configuration of the flip-flop circuit 4 having the 2V / 3V system level conversion circuit. The flip-flop circuit 4 shown in FIG.
A master latch 30 and a slave latch 31 connected in series with the same configuration as the flip-flop circuit 2 of the system, an internal clock generation circuit 33, an output buffer 34 using the 3V high voltage source 15 as a voltage source, A level conversion circuit 35 is provided between the latch 31 and the output buffer 34. The level conversion circuit 3
Reference numeral 5 denotes a 2V / 3V system, in which the potential difference between complementary signals of the 2V system slave latch 31 is a low voltage (2V). Has a function of converting the level into a high voltage signal in which the potential difference between the signals is high voltage (3 V) and outputting the high voltage signal.

FIGS. 6A and 6B show a specific configuration of the level conversion circuit 35. FIG. In the level conversion circuit 35 of FIG. 3A, reference numerals 40 and 41 denote PMOS transistors, and reference numerals 42 and 43 denote NMOS transistors. One PMOS transistor 40 and one NMOS transistor 42 are connected in series. The other PMOS transistor 41 and the other NMOS transistor 43 are connected in series, and both series circuits are arranged between the high voltage source 15 of 3V and the ground. The gate of the one PMOS transistor 40 is connected to the NMO on the side not connected in series.
The drain of the S-type transistor 43 is connected to the drain of the NMOS transistor 42, and the gate of the other PMOS transistor 41 is connected to the drain of the NMOS transistor 42. The complementary output is taken from the drains of the NMOS transistors 42 and 43. With the above configuration, the PMOS transistor 40 and the NMOS transistor 42, and the PMOS transistor 41 and the NMOS transistor 43 each perform the function of an inverter. That is, when a low voltage of 2 V is supplied to the gate of one NMOS transistor 43 and 0 V is supplied to the gate of the other NMOS transistor 42 by the complementary output of the slave latch 31 in FIG. The NMOS transistor 43 is turned on and the other NMOS transistor 42 is turned off, and accordingly, one PMOS transistor 40 is turned on and the other PMOS transistor 41 is turned off. The drain is connected to the high voltage source 15 of 3V and the drain of the other NMOS transistor 43 is grounded, so that a complementary output having a high potential difference of 3V is obtained. FIG.
In the configuration of (a), the through current from the 3V high voltage source 15 to the 2V low voltage source 16 and the 3V high voltage source 15
The level of the complementary output of the slave latch 31 shown in FIG. 5 can be converted from a low voltage of 2V to a high voltage of 3V without passing through current to V (ground).

FIG. 6B shows a level conversion circuit 35 'having another specific configuration different from the above. The level conversion circuit 35 'shown in FIG.
Instead of the NMOS transistors 42 and 43, two NMOS inverters 45 and 46 are arranged. The two PMOS inverters 45 and 46 each have one
PMOS transistors 47 and 49 and one NMOS
It is formed by connecting the type transistors 48 and 50 in series. The input terminals of both the PMOS inverters 45 and 46, that is, both PMOS and NMOS transistors 47 and 4 connected in series.
The gates 8, 49 and 50 have the slave latch 31 of FIG.
Are output. An output terminal of one of the PMOS inverters 45, that is, a PMOS transistor 47
Is connected to the gate of the PMOS transistor 41 not connected in series with the PMOS inverter 45, and the output terminal of the other PMOS inverter 46 is connected to the PMOS transistor 40 not connected in series with the PMOS inverter 46. Are connected to the respective gates.
The outputs of the two PMOS inverters 45 and 46 are complementary outputs of the level conversion circuit 35 '. With the above configuration, 3V
The complementary output of the slave latch 31 shown in FIG. 5 is supplied from the low voltage of 2V without flowing a through current from the high voltage source 15 to the low voltage source 16 of 2V and a through current from the high voltage source 15 of 3V to the ground. The level can be converted to a high voltage of 3V. Further, P which constitutes the CMOS inverters 45 and 46
The MOS transistor is a 3V high voltage source 1 in a transient state.
5 to suppress the through current from flowing to ground.

As can be understood from the above description, the semiconductor integrated circuit shown in FIG.
3 is a low-voltage 2V system, has a 2V combination circuit 3 at its input, and has a 3V combination circuit 5 at its output.
Is a low-voltage / high-voltage system (2 V / 3 V system), and a flip-flop circuit 6 having a 3 V system combination circuit 5 at the input and a 2 V system combination circuit 7 at the output is a low voltage 2 V system. It is composed of a system.

In the above description, the registers r1, r2, r3, r4 are constituted by flip-flop circuits, but may be constituted by latch circuits instead of the flip-flop circuits. FIGS. 7 and 8 show a specific configuration of the latch circuit. FIG. 7 shows a low-voltage 2V-system latch circuit 51. A latch circuit 51 shown in FIG. 7 is a latch unit (temporary data storage unit) that receives and latches one signal D and obtains a complementary output.
52, an output buffer 53 connected to the output side of the latch unit 52, and an internal clock generation circuit 54 that generates an internal clock NG from the external clock G and outputs the internal clock NG to the latch unit 52. , An external clock G are also supplied to the latch unit 52. The above circuits 52 to 54 are 2V using the 2V low voltage source 16 as a voltage source.
System. FIG. 8 shows a low-voltage / high-voltage (2 V / 3 V) latch circuit 51 ′. The latch circuit 51 'in FIG.
Similarly to the configuration of the low-voltage 2V-system latch circuit, the latch unit 52 and the internal clock generation circuit 54 using the 2V low-voltage source 16 as a voltage source, and the output buffer 55 using the 3V high-voltage source 15 as a voltage source And an input signal interposed between the latch section 52 and the output buffer 55 to reduce the input signal to a low voltage (2 V).
Level conversion circuit 5 for converting the level from the high voltage (3V) to
6 is provided. The specific configuration of the level conversion circuit 56 is the same as the specific configuration shown in FIG. 6A or 6B.

Next, an algorithm of a logic synthesis method for logic-synthesizing the semiconductor integrated circuit shown in FIG. 3 based on the connection information of the logic cells will be described with reference to the logic synthesis apparatus of FIG. 9 and the flowcharts of FIGS. Will be explained.

FIG. 9 shows the overall schematic configuration of the logic synthesis device 60. In the figure, 61 is a reading unit, 62 is a translation unit, 63 is an optimization processing unit, 64 is a cell allocation unit, 65 is a timing verification unit, 66 is a circuit diagram generation unit, and 67 is an output unit. The reading unit 61 is the same as that shown in FIG.
RTL description (hardware description language) shown in
A netlist shown in FIG. 11 in which the signal transmission relationship between registers is clearly defined based on the connection information level of the logic cell based on the L description, or a schematic shown in FIG. The translation unit 62 converts the RTL description read from the reading unit 61 into a state transition diagram, a Boolean expression, a timing diagram, and memory specifications such as a memory type, the number of bits and the number of words.

The optimization processing unit 63 includes a state transition diagram optimization processing unit 63a for optimizing the obtained state transition diagram and a state for generating a circuit (state machine) corresponding to the optimized state transition diagram. A machine generator 63b, a compiler 63c for compiling the obtained timing diagram, and a memory composing unit 63d for composing a memory based on the obtained memory specifications; Combining unit 63 for combining the interface unit based on the stored memory
e. Further, the optimization processing unit 63 includes the reading unit 6
If the input to 1 is an RTL description, the logic is optimized based on the obtained state machine, the obtained Boolean expression and the synthesized interface unit, and the connection information of the optimized logic cell is obtained. While generating, the reading unit 61
In the case where the input to is a netlist or schematic, there is a logic optimization unit 63f that optimizes the logic of the input netlist or schematic and generates connection information of the optimized logic.

The output unit 67 externally outputs a netlist indicating the logic circuit of FIG. 3 or a logic circuit diagram (schematic) obtained by schematizing the netlist.

The present invention resides in the cell allocating section 64 shown in FIG. Next, based on the cell allocation (cell mapping) processing by the cell allocation section 64, ie, the cell connection information obtained by the logic optimization section 63f, FIG.
The algorithm for logically synthesizing the semiconductor integrated circuit shown in FIG. 1 will be described with reference to the flowchart of FIG. Note that FIG. 13 mainly illustrates features of the present invention.

Referring to FIG.
In 1 to S4 (first step), the combinational circuit whose signal propagation delay time is equal to or less than the designed delay upper limit value is combined with the first combinational circuit using the 2V low voltage source 16 as a voltage source, and vice versa. The combinational circuit whose signal propagation delay time exceeds the designed delay upper limit value is combined with the second combinational circuit using the 3V high voltage source 15 as a voltage source.

The first step is performed as follows in this embodiment. That is, first, after reading the cell connection information from the logic optimizing unit 63f, an arbitrary flip-flop is used in step S1 by using each signal propagation delay time of the low-voltage (2V) flip-flop circuit and the combinational circuit. The signal propagation delay time in the signal propagation path from the clock input of the flip-flop circuit to the data input of the next flip-flop circuit is estimated for each signal propagation path. The estimation of the signal propagation delay time is performed, for example, by using a logic (AND circuit, NOR
Circuit or NOT circuit), for example, the type of logic, the number of inputs, and the number of logic stages are extracted, and the signal propagation delay when each logic is mapped to a cell based on the logic-related information and the cell technology. This is done by calculating and estimating the time. Then, estimation result of the signal propagation delay time to determine whether more than the upper limit of the delay in the design step S2, in the case of more than the upper limit, Shin in step S3
Circuit, which is an aggregate of logic gates arranged on the signal propagation path, is changed to a combination circuit (first combination circuit) of a low-voltage (2 V) logic cell library (hereinafter, referred to as lib). If the estimation result exceeds the upper limit value of the delay in the design, it is arranged on the signal propagation path in step S4.
A combinational circuit, which is a set of logic gates, is connected to a high voltage (3
V) This is performed by mapping to a combinational circuit of lib (a second combinational circuit).

Subsequently, the following processing is performed in steps S5 and S6 (second step). That is, in step S5, the combination circuit of the 2V system and the combination circuit of the 3V system are mixed so that the output of the combination circuit of the low voltage system (2V system) becomes the input of the combination circuit of the high voltage system (3V system). It is checked whether or not there is a mixture of the above shapes. In step S6, the 2V system combination circuit (first combination circuit) is formed.
Input of the 3V system combination circuit among the 2V system logic gates
The subsequent logic gates including the logic gates serving as power
3V system that composes ib combination circuit (second combination circuit)
Is again mapped so as to be replaced by the logic gate of. If there is no mixture, 3V logic gates should be 3
There is no need to convert to V-based logic gates.

After that, since the voltage systems of the combinational circuits located on the input side and the output side of the register have already been determined by the above-described logic synthesis, steps S7 to S9 (third step) are performed.
In step (3), the following processing is performed. That is, it is checked whether or not each register converts the level of the potential from the input of the low voltage (2 V) to the output of the high voltage (3 V). If the level is to be converted, the register (the flip-flop circuit) that performs the level conversion in step S8. 4 is mapped to the 2V / 3V-system flip-flop circuit of FIG. 5 or the 2V / 3V-system latch circuit of FIG. 8, and if the level is not to be converted, the register whose level is not converted is replaced with the 2V / 3V of FIG. 7 is mapped to the flip-flop circuit of the system or the latch circuit of the 2V system in FIG.

FIG. 14 shows a modification of the logic synthesis method shown in FIG. In the logic synthesis method of FIG. 13, the signal propagation delay time is estimated in the first step, and the combinational circuit is mapped to a low-voltage (2V) combinational circuit or a high-voltage (3V) combinational circuit according to the estimation result. Instead of
In the present modified example, first, in step S10, mapping is performed on a 2V lib combinational circuit (first combinational circuit), and then, in step S11, it is determined whether or not the result of the combination is equal to or less than a design delay upper limit value. Only when the delay exceeds the upper limit value, mapping is performed again in step S12 so that the combined circuit of 2Vlib (first combined circuit) is replaced with a combined circuit of 3Vlib (second combined circuit). The second and third steps of this modified example are the same as the logic synthesis method of FIG. 13 described above, and a description thereof will be omitted.

FIG. 15 shows a modified example in which a part of the logic synthesis algorithm shown in FIG. Hereinafter, the logic synthesis algorithm of FIG. 15 will be described with respect to portions different from FIG. In the first step, step S1
3 is added. This step S13 is equivalent to step S2
In the case where the estimation result of the signal propagation delay time exceeds the upper limit value, all the low voltages (2 V) li exceeding the upper limit value are set in advance.
b), and after this step S13, the extracted first combinational circuit is combined in step S4 with a high-voltage (3V) lib combinational circuit (the second combinational circuit). Circuit). In the second step, step S14 is added. This step S14 is a step of, in the case where the combination circuit of the 2V system and the combination circuit of the 3V system are mixed in step S5, extracting all of the mixed circuit (first combination circuit) of the 2V system in advance. After step S14, the extracted first combinational circuit is mapped again to the high-voltage (3V) lib combinational circuit (second combinational circuit) in step 6. Further, in the second step, after re-mapping to the second combinational circuit in the step 6,
An algorithm returning to step 5 is added. This algorithm takes into consideration that the combination of the 2V system combination circuit and the 3V system combination circuit may newly occur due to the mapping to the 3V system combination circuit in step 6 described above. This mixture is determined in step 5, and if there is this mixture, again in steps S14 and S6,
This is for repeating the extraction of the mixed circuit of the mixed 2V system and the re-mapping of the extracted first combination circuit to the combination circuit of the high voltage (3V) lib (the second combination circuit).

FIG. 16 shows a modified example in which a part of the logic synthesis algorithm shown in FIG. As in the case of FIG. 15, in this modification, when the signal propagation delay time exceeds the upper limit (step S11), the combination circuit (the first combination) of all low-voltage (2V) libs exceeding the upper limit is used in advance. Step 15 for extracting the circuit
If the combination circuit of the 2V system and the combination circuit of the 3V system are mixed together (step S5), all of the mixed 2V system combination circuits (first combination circuits) are extracted in advance. Step 16 is added to the second step. In this second step, the 2V-system combination circuit and the 3V-system combination circuit are added due to the remapping to the 3V-system combination circuit (step 6). In consideration of the fact that a mixture of
An algorithm is added to return to step 5 for determining the presence or absence of the coexistence after the processing of.

[0053] Thus, in each algorithm logic synthesis method shown in FIGS. 15 and 16, for example, as shown in FIG. 17 (a), the signal propagation delay time or the estimated result design
When exceeding the maximum delay values above, the critical path
A first combining circuit, as shown in hatching with
Four logic gates 5a, 5a, 5b driven at a high voltage of 3V
b, 5c, and mapped to the second combining circuit 5 consisting 5d, the signal of the signal propagation path of the second combinational circuit 5
Propagation delay time should be less than the design delay upper limit
To

[0054] After that, a logic gate driven by a low voltage source
Output goes to the input of a logic gate driven by a high voltage source.
Determining whether the form of a mixed being force, if there is this mixed, first logic to the mix as shown in FIG. (B)
The gate 100b is connected to a high voltage source as shown by hatching in the figure.
Is re-mapped to the second logic gate driven by . This
, The first driven by a lower voltage source
Of the logic gate 100a is driven by a high voltage source
Mixed form input to input of second logic gate 100b
, So that the mixed first logic gate
100a is driven by a high voltage source as shown by hatching in the figure.
To a second logic gate to be mapped. Continued stomach,
By the remapping , the first driven by the low voltage source
The output of the logic gate 101a is driven by a high voltage source.
Shows a mixed form that is input to the input of the second logic gate 100b occurs newly Runode, the first logic gate 101a to the Mixed As shown in FIG. 5 (c) in hatching
To a second logic gate driven by a high voltage source .

Then, when the mixture is eliminated,
When each flip-flop circuit converts the level of a potential from a low-voltage (2 V) input to a high-voltage (3 V) output, as shown in FIG. Is mapped to the 2V / 3V-system flip-flop circuit shown by.

Here, the semiconductor shown in FIG.
As can be seen from the integrated circuit, this semiconductor integrated circuit
High voltage driven second located on the critical path
Circuit having a logic gate 5b of
1 as well as the critical circuit
High voltage driven second logic gate located on path
5d on its own signal propagation path.
1). The pair
The matching circuit 110 includes a second logic gate driven by a high voltage.
100a and the high voltage output of its logic gate 100a
Is input to the second logic gate 5b and the logic gate
5b high voltage output is input, driven by low voltage
And a first logic gate 102. In addition, the other union
The delay circuit 111 has all the signals on its own signal propagation path.
Logic gates are driven by three second logic
Gates 101a, 101b, 5d, driven at low voltage
Does not have a first logic gate. This combination circuit 1
11, the three second logic gates 101a, 1
01b and 5d are connected in series, and the second logic gate
High-voltage output is applied to the input of the next second logic gate
Is done.

FIG. 18 shows an embodiment in which the logic synthesis method of FIG. 13 is applied to a semiconductor integrated circuit having a different configuration from the semiconductor integrated circuit of FIG.

FIG. 9 shows a semiconductor integrated circuit using a flip-flop circuit for scan test as a register.
Scan flip-flop circuits 80, 81, 82, 83
And 84 are 2V / 3V scan flip-flop circuits, and the other scan flip-flop circuits are 2V scan flip-flop circuits.

FIG. 19 shows the configuration of the 2V-system scan flip-flop circuit. The scan flip-flop circuit shown in the figure includes a multiplexer 90 in addition to the configuration of the low-voltage (2 V) flip-flop circuit shown in FIG. The multiplexer 90 uses the low voltage source 16 of 2V as a voltage source, and receives two data D and DT by a control signal SE.
Is selected and output. The data selected by the multiplexer 90 is input to the master latch 30. About the other structure, the same code | symbol is attached | subjected to the same part as the structure of the flip-flop circuit shown in FIG. 4, and the description is abbreviate | omitted.

FIG. 21 shows a 2V-system scan flip-flop circuit having another configuration. The 2V-system scan flip-flop circuit shown in FIG. 9 includes a data input selection circuit 91 in addition to the configuration of the flip-flop circuit shown in FIG. The data input selection circuit 91 is connected to the master latch 30
When the data D is input by the external clock CLK, the input of the other data DT is inhibited. When the master latch 30 inhibits the input of the data D, the other data DT is input by the other clock CLKT. Output to the master latch 30. In the figure, reference numeral 92 denotes an internal clock generation circuit which receives the two types of external clocks CLK and CLKT to generate two types of internal clocks CK and NCK, and applies the internal clocks CK and NCK to a master latch 30 and a slave. Latch 31
Output to

FIG. 20 shows a 2V / 3V scan flip-flop circuit. 19 includes the same circuits as the master latch 30, slave latch 31, internal clock generation circuit 33, and multiplexer 90 of the 2V-system scan flip-flop circuit in FIG. It has an output buffer 95 as a source and a level conversion circuit 96 of a 2V / 3V system. The 2V / 3V system level conversion circuit 96 is interposed between the slave latch 31 and the output buffer 95. The specific configuration of the 2V / 3V system level conversion circuit 96 is the same as that shown in FIG. 6A or 6B.

FIG. 22 shows another 2V / 3V scan flip-flop circuit. The scan flip-flop circuit shown in FIG. 21 includes the master latch 30, the slave latch 31, and the scan flip-flop circuit of the 2V system shown in FIG.
Internal clock generation circuit 92 and data input selection circuit 91
And an output buffer 97 using a 3V high voltage source as a voltage source, and a 2V / 3V system level conversion circuit 98. The 2V / 3V level conversion circuit 98 is interposed between the slave latch 31 and the output buffer 97. The specific configuration of the 2V / 3V level conversion circuit 98 is the same as that shown in FIG. 6A or 6B.

A method of logically synthesizing the semiconductor integrated circuit of FIG. 18 will be described. Assume that combinational circuits 86, 87 and 88 have a critical path. According to the algorithm of the logic synthesis method shown in FIG. 13, the combination circuits 86 and 8 are mapped in the first mapping stage (first step) of the combination circuit.
7 and 88 are mapped to a 3V lib combinational circuit (second combinational circuit), and the other combinational circuits are mapped to a 2V lib combinational circuit (first combination circuit).

Next, in the remapping stage of the combinational circuit (second step), the combinational circuit 89 is remapped to a combinational circuit of 3 Vlib. Then, at the stage of register (flip-flop circuit) mapping (third step), the flip-flop circuits 80, 81, 82, 83 and 84 are formed.
Is mapped to a 2V / 3V flip-flop circuit,
Another flip-flop circuit is mapped to a 2V-system flip-flop circuit.

In the semiconductor integrated circuit of FIG. 18 generated as described above, a low-voltage logic lib of 2 V and a high-voltage logic lib of 3 V are mixed, but the voltage source of each combinational circuit is 2 V. Of the low voltage source 16 or the high voltage source 15 of 3V, and the level conversion of the voltage from the low voltage of 2V to the high voltage of 3V is performed by a level conversion circuit in a scan flip-flop circuit of a 2V / 3V system. Done.

The semiconductor integrated circuit of FIG. 18 has eight scan chains indicated by broken lines in the figure, in which signals are transmitted only through a plurality of scan flip-flop circuits without passing through combinational circuits in the scan test mode. For example, input
In the scan chain connected to Si3, the scan flip-flop circuit 81 of the 2V / 3V system performs level conversion from a low voltage of 2V to a high voltage of 3V, as in the normal mode, and the next stage scan flip-flop circuit of the scan flip-flop circuit 81 Circuit 99 from 3V high voltage to 2
Level conversion is performed to a low voltage of V. Therefore, even when the scan flip-flop circuit shown in FIG. 20 or FIG. 22 is used, even in the scan test mode in which the signal transmission path is different from the normal path (that is, the path passing through the combinational circuit), 2V
The scan test of the semiconductor integrated circuit of the present invention in which the low-voltage system and the 3V high-voltage system coexist is possible.

In the above description, the present invention has been applied to the functional block A which constitutes other than the memory cell section E formed in the internal core section 22 of the chip 20, but has been applied to the other functional blocks BD. It goes without saying that a plurality of functional blocks A to
Needless to say, the present invention can be similarly applied between D.

Therefore, the semiconductor integrated circuit of this embodiment has
According to combinational circuits with critical paths
And the logic gates 5a to 5d on the critical path
Since the logic is synthesized so as to be driven by a high voltage system of 3 V,
Of critical path signal propagation delay time by design
To be less than the maximum delay value.

In addition, the logic gate driven by the high voltage system
Another combinational circuit including ports 5b and 5d on a signal propagation path
110 and 111 are logic gates driven by a low voltage system
Or <br/> those containing logic gate driven by other high-voltage system, because the number of pairs combined circuits which such is a very small number compared to the number of combinational circuit provided in the semiconductor integrated circuit, While the increase in current consumption is kept small , all the remaining combinational circuits are driven by the low voltage source 16 of 2 V, so that the current consumption of the entire semiconductor integrated circuit can be reduced, and the power consumption can be reduced.

The semiconductor integrated circuit of this embodiment shown in FIG.
5 is compared with the conventional semiconductor integrated circuit of FIG. In the conventional semiconductor integrated circuit of FIG. 25, each of the combinational circuits 100, 102,.
Signal propagation delay times of 104 and 106 are 6 ns and 12 n as shown in the figure.
s, 18 ns, and 8 ns, and the delay time from the clock input to the data output of the flip-flop circuit is 2 ns. Since the maximum delay of the combinational circuit is 18 ns of the combinational circuit 104, the maximum delay of the circuit of FIG. The operating frequency is 1000 / (2 + 18) = 50MH.

On the other hand, in the semiconductor integrated circuit of this embodiment shown in FIG. 3, the delay time of the combinational circuit 5 having a critical path is the same voltage system (3 V) as in the prior art. is there. The delay time of the combinational circuits 1, 3 and 7 having no critical path increases as the delay of the logic cell increases, since the power supply voltage is reduced from the high voltage of 3V to the low voltage of 2V. FIG.
Of semiconductor integrated circuits, the upper limit of the design delay time is 20 ns
It is assumed that the delay time of a cell is 1.5 times as large as that of a low voltage source of 2 V with respect to a high voltage source of 3 V. The maximum of the delay times of the combination circuits 1, 3 and 7 having no critical path is 18 ns of the combination circuit 3.

The low voltage source 16 of 2V and the high voltage source 15 of 3V
As a result, the maximum delay of the combinational circuit is 18 ns for the combinational circuit 3 having no critical path and the combinational circuit 5 having the critical path. Since each signal propagation delay time from the clock input to the data output of the flip-flop circuits 2 and 4 is 2 ns, and the delay time of each of the combinational circuits 3 and 5 is 18 ns, the maximum operating frequency of the semiconductor integrated circuit of this embodiment is Is 1000 / (2 + 18) = 50MH, and the combinational circuits 1 and 3 having no critical path
And 7 are driven by the low voltage source 16 of 2 V, the same maximum operating frequency as that of the conventional semiconductor integrated circuit can be obtained.

FIG. 23 shows the delay between the clock input of the flip-flop circuit and the data input of the next-stage flip-flop circuit in the semiconductor integrated circuit of this embodiment of FIG. 3 and the conventional semiconductor integrated circuit of FIG. That is, the distribution of the signal propagation delay time obtained by adding the delay times of the register and the combinational circuit is shown. FIG. 3A shows the delay distribution of a conventional 3 V voltage semiconductor integrated circuit, and FIG. 3B shows the delay distribution of a 2 V and 3 V mixed semiconductor integrated circuit of the present embodiment. In a conventional semiconductor integrated circuit, when only the power supply voltage is changed from a high voltage system of 3V to a low voltage system of 2V, the maximum delay time is 20 ns.
In contrast, the delay time of the critical path exceeds the upper limit of the designed delay of 20 ns, whereas the semiconductor integrated circuit of this embodiment shown in FIG. Is changed to a high voltage system of 3V, and the other combinational circuits having no critical path are set to a low power system of 2V.
20ns can be satisfied. FIG. 11B shows the delay distribution at this time.

Next, the power consumption of the conventional semiconductor integrated circuit is compared with that of the semiconductor integrated circuit of the present invention. The power consumption of the conventional semiconductor integrated circuit is P, the power supply is a dual power supply of a high voltage source of 3 V and a low voltage source of 2 V, the ratio of the critical path in the entire circuit is 10%, and the 2V / 3V flip-flop of the present invention. Assuming that the power consumption of the flip-flop circuit is different from that of the conventional flip-flop circuit by 10%,
As shown in the following equation, the power consumption of the semiconductor integrated circuit of the present invention is [Px (2/3)] ² x 0.9 + Px 1.1 x 0.1 = Px 0.51, and the power consumption is reduced by 49%.

Further, assuming that the ratio of the critical path to the whole circuit is 5% under the above conditions, the power consumption of the semiconductor integrated circuit of the present invention is expressed by the following equation: [Px (2/3)] ² x 0.95 + Px 1.1 x 0.05 = P x 0.48, and the power consumption is reduced by 52%.

Subsequently, the circuit scale is compared between the conventional semiconductor integrated circuit and the semiconductor integrated circuit of the present invention.

The circuit size of the conventional semiconductor integrated circuit is S, the proportion of the flip-flop circuit in the semiconductor integrated circuit is 20%, and the proportion of the flip-flop circuit having the level conversion circuit in the whole flip-flop circuit is 10
%, And if the 2V / 3V flip-flop circuit of the present invention has an area increase of 10% due to a difference in circuit configuration from the conventional flip-flop circuit, the circuit scale of the semiconductor integrated circuit of the present invention is expressed by the following equation. Then, S x 0.8 + S x 0.18 + S x 1.1 x 0.02 = S x 1.002, and the increase in the circuit scale is limited to 0.2%.

Further, assuming that the proportion of the flip-flop circuit having the level conversion circuit in the whole flip-flop circuit is 5% under the above-mentioned conditions, the circuit scale of the semiconductor integrated circuit of the present invention is expressed by the following equation. , S x 0.8 + S x 0.19 + S x 1.1 x 0.01 = S x 1.001, and the increase in the circuit scale remains at 0.1%.

[0079]

As described in the foregoing, according to the semiconductor integrated circuit of the invention of claim 1 to claim 10, wherein the high voltage source logic gates in combinational circuit with a critical path
, Which suppresses the increase in power consumption and reduces power consumption.
It is possible to reduce the signal propagation delay time of the critical path to less than the delay upper limit allowed by design while reducing power consumption .

In addition, the high voltage on the critical path
Sets including logic gates driven by the system in the signal propagation path
In matching circuits, logic gates driven by low voltage systems or other
Including logic gates driven by high voltage
The number of combination circuits, such as
Because the number is very small compared to the number of circuits, the current consumption increases.
While the size can be kept small, all the remaining combinational circuits
Since it is driven by the low voltage source 16 of 2V, the semiconductor integrated circuit
Overall current consumption can be reduced, reducing power consumption
Noh.

[Brief description of the drawings]

FIG. 1 is an overall schematic configuration diagram of an image processing system.

FIG. 2 is an overall schematic configuration diagram of a semiconductor chip.

FIG. 3 is a diagram illustrating a connection relationship between a plurality of registers and a plurality of combinational circuits of the semiconductor integrated circuit according to the embodiment of the present invention.

FIG. 4 is a configuration diagram of a flip-flop circuit having no level conversion circuit.

FIG. 5 is a configuration diagram of a flip-flop circuit having a level conversion circuit.

FIG. 6 is a diagram showing a specific configuration of a level conversion circuit.

FIG. 7 is a configuration diagram of a latch circuit having no level conversion circuit.

FIG. 8 is a configuration diagram of a latch circuit having a level conversion circuit.

FIG. 9 is a diagram showing an overall schematic configuration of a logic synthesis device.

FIG. 10 is a diagram illustrating a hardware description language.

FIG. 11 is a diagram showing a net list.

FIG. 12 is a diagram showing a schematic.

FIG. 13 is a diagram illustrating a logic synthesis method of a semiconductor integrated circuit.

FIG. 14 is a diagram illustrating another logic synthesis method of the semiconductor integrated circuit.

FIG. 15 is a diagram showing a modification of the logic synthesis method of FIG.

FIG. 16 is a diagram illustrating a modification of the other logic synthesis method in FIG. 14;

FIG. 17 is an explanatory diagram of mapping to a flip-flop circuit having a second combinational circuit and a level conversion circuit.

FIG. 18 is a diagram showing another semiconductor integrated circuit to be developed.

FIG. 19 is a configuration diagram of a scan flip-flop circuit having no level conversion circuit.

FIG. 20 is a configuration diagram of a scan flip-flop circuit having a level conversion circuit.

FIG. 21 is a configuration diagram of another scan flip-flop circuit having no level conversion circuit.

FIG. 22 is a configuration diagram of another scan flip-flop circuit having a level conversion circuit.

FIG. 23 is a diagram showing a signal propagation delay time of a semiconductor integrated circuit according to a conventional example and an example of the present invention and a distribution of the number of combinational circuits having the delay time.

FIG. 24 is a diagram showing a description of a register transfer level.

FIG. 25 is a diagram showing a logic circuit of a conventional semiconductor integrated circuit.

FIG. 26 is a diagram showing an arrangement position of a level conversion circuit when only a critical path is driven by a high voltage source in an arbitrary semiconductor integrated circuit.

FIG. 27 is a diagram showing an arrangement position of a level conversion circuit in a case where only a critical path is driven by a high voltage source in another arbitrary semiconductor integrated circuit.

[Description of Signs] 1, 3, 7 First combination circuit 5 Second combination circuit 2, 4, 6, 8 Flip-flop circuit (register) 9 Clock buffer (clock supply means) 15 High voltage source 16 Low voltage source 22 Internal core unit 30 Master latch 31 Slave latch 33, 3354, 92 Internal clock generation circuit 35, 3556, 96, 98 Level conversion circuit 36 Data temporary storage unit 40, 41 PMOS transistor 42, 43 NMOS transistor 45, 46 CMOS type Inverters 47, 49 PMOS transistors 48, 50 NMOS transistors 51, 51 'Latch circuit (register) 52 Latch section 65 Timing verification section 80 to 84 Scan test flip-flop circuit (register) 90 Multiplexer 91 Data input selection circuit 110 111 pairs To circuit

[Procedure amendment 2]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG.

Claims (23)

[Claims] 1. A logic synthesis method for synthesizing a semiconductor integrated circuit including a plurality of registers and a plurality of combinational circuits located between the plurality of registers based on connection information of a logic cell. If the signal propagation delay time of the combinational circuit is equal to or less than the design delay upper limit, this combinational circuit is combined with a first combinational circuit using a low voltage source as a voltage source, and the signal propagation A first step of combining this combinational circuit with a second combinational circuit using a high voltage source as a voltage source when the delay time exceeds a design delay upper limit value; It is determined whether the output of the combinational circuit is mixed with the form input to the second combined circuit, and if there is, the first combinational circuit is re-synthesized into the second combinational circuit. A second step; The register determines whether or not the register is a register that outputs a signal to the combined or recombined second combinational circuit. If any of the registers is the register, the register is set to a high voltage source as a voltage source. And synthesizing the register with a register that uses a low-voltage source as a voltage source if the register is not the register. 2. The first step comprises first combining a register driven by the low voltage source and the first combination circuit using a first combinational circuit and a register driven by the low voltage source. Estimating the signal propagation delay time, and then, when there is a first combinational circuit in which the estimation result is equal to or less than the designed delay upper limit value, synthesizes the first combinational circuit with the first combinational circuit, 2. The logic synthesis according to claim 1, wherein when there is a first combinational circuit whose result exceeds the design delay upper limit value, the first combinational circuit is combined with the second combinational circuit. Method. 3. The first step is to first synthesize all the combinational circuits using the first combinational circuit, and then determine whether the signal propagation delay time of the combinational circuit exceeds the designed delay upper limit value. Determining whether or not there is a first combinational circuit exceeding a design delay upper limit value and resynthesizing the first combinational circuit into a second combinational circuit. 2. The logic synthesis method according to 1. 4. The second step is as follows: as a result of re-synthesizing the first combinational circuit into the second combinational circuit, the output of any one of the first combinational circuits is newly combined with the second combinational combination. It is determined whether or not a mixture of shapes input to the circuit has occurred.
2. The logic synthesizing method according to claim 1, further comprising the step of repeating the re-synthesis of the combinational circuit into the second combinational circuit. 5. A register transfer level design data describing a plurality of registers and a plurality of combinational circuits located between the respective registers, wherein the connection information of the logic cells in the first step is the inputted register transfer. 2. The logic synthesis method according to claim 1, wherein the logic synthesis method is generated from level design data. 6. A netlist describing connection information of a logic cell is input, and the connection information of the logic cell in the first step is generated from the connection information of the logic cell described in the input netlist. The logic synthesis method according to claim 1, wherein: 7. A schematic representing the connection information of the logic cell is inputted, and the connection information of the logic cell in the first step is generated from the connection information of the logic cell represented in the inputted schematic. The logic synthesis method according to claim 1, wherein 8. A method for optimizing connection information of a logic cell based on an input register transfer level, an input netlist, or an input schematic, comprising: 8. The logic synthesis method according to claim 5, wherein the logic synthesis method is used as connection information of a logic cell. 9. The method according to claim 1, further comprising the step of verifying the timing of each register after the third step.
Logic synthesis method as described. 10. A semiconductor integrated circuit having a plurality of registers and a plurality of combinational circuits located between the registers, wherein some of the plurality of combinational circuits use a low voltage source as a voltage source. And the other combinational circuit of the plurality of combinational circuits comprises a second combinational circuit using a high voltage source as a voltage source. The register in which the first combinational circuit is located and the second combinational circuit is located on the output side are a data temporary storage unit using a low voltage source as a voltage source, and a low-level data storage unit using a high voltage source as a voltage source. A semiconductor integrated circuit, comprising: a register having a level conversion circuit for level-converting a voltage output signal into a high-voltage output signal. 11. A register in which a first combinational circuit is located on each of an input side and an output side among a plurality of registers, a second combinational circuit is located on an input side, and a first combinational circuit is located on an output side. The registers located are each configured by a register having a low voltage source as a voltage source and having no level conversion circuit. Of the plurality of registers, a register in which a second combinational circuit is located on an input side and an output side is, A register having a data temporary storage unit using a low voltage source as a voltage source, and a level conversion circuit for level converting a low voltage output signal of the data temporary storage unit to a high voltage output signal using a high voltage source as a voltage source. The semiconductor integrated circuit according to claim 10, wherein: 12. The semiconductor integrated circuit according to claim 10, further comprising clock supply means for using a low voltage source as a voltage source and supplying a clock to each register. 13. A register having a level conversion circuit comprises a flip-flop circuit, wherein the flip-flop circuit uses a low voltage source as a voltage source, a master latch and a slave latch connected in series using a low voltage source, and a high voltage source as a voltage source. An output buffer, and a level conversion circuit interposed between the slave latch and the output buffer for level-converting a low-voltage signal input from the slave latch into a high-voltage signal and outputting the high-voltage signal to the output buffer. 13. The semiconductor integrated circuit according to claim 10, wherein: 14. A register having no level conversion circuit comprises a flip-flop circuit, wherein the flip-flop circuit uses a low voltage source as a voltage source, a master latch and a slave latch connected in series, and a low voltage source as a voltage source. 13. The semiconductor integrated circuit according to claim 11, further comprising: an output buffer for receiving an output signal from the slave latch. 15. A register having a level conversion circuit, comprising a latch circuit, wherein the latch circuit includes a latch unit using a low voltage source as a voltage source, an output buffer using a high voltage source as a voltage source, and the latch unit. 11. The level conversion circuit interposed between the output buffer and a level conversion circuit for level-converting a low-voltage signal input from the latch unit to a high voltage and outputting the high-voltage signal to the output buffer. The semiconductor integrated circuit according to claim 11 or 12. 16. A register having no level conversion circuit comprises a latch circuit, wherein the latch circuit uses a low voltage source as a voltage source, and outputs a signal from the latch unit using a low voltage source as a voltage source. 13. The semiconductor integrated circuit according to claim 11, comprising an output buffer for inputting. 17. The semiconductor integrated circuit according to claim 10, wherein each register is constituted by a scan test flip-flop circuit. 18. A scan test flip-flop circuit having a level conversion circuit out of the scan test flip-flop circuits, which uses a low voltage source as a voltage source and receives any one of a plurality of input data in response to a control signal externally input. A multiplexer for selecting one of the data, a master latch and a slave latch connected in series to input a signal from the multiplexer using a low voltage source as a voltage source, an output buffer using a high voltage source as a voltage source, and the slave A level conversion circuit interposed between the latch and the output buffer, the level conversion circuit converting the level of a low voltage signal input from the slave latch into a high voltage signal and outputting the high voltage signal to the output buffer. 18. The semiconductor integrated circuit according to item 17. 19. A scan test flip-flop circuit having a level conversion circuit among the scan test flip-flop circuits, wherein one of a plurality of input data is selected by a clock using a low voltage source as a voltage source. A data input selection circuit, a series-connected master latch and a slave latch for inputting a signal from the data input selection circuit using a low voltage source as a voltage source, an output buffer using a high voltage source as a voltage source, and the slave latch 18. A level conversion circuit interposed between the output buffer and the output buffer for level-converting a low-voltage signal input from the slave latch into a high-voltage signal and outputting the high-voltage signal to the output buffer. A semiconductor integrated circuit as described in the above. 20. A level conversion circuit comprising two PMOS transistors and two NMOS transistors, wherein the gate of one PMOS transistor is connected to the other PMOS transistor.
Connected to the drain of the transistor
The drain of the MOS transistor is connected to the gate of the other PMOS transistor, and the two PMOS transistors are connected to each other.
The source of the transistor is connected to a high voltage source, and the two NMOS transistors receive the complementary signal of a slave latch that outputs a complementary signal to both gates, and each drain has two drains. Are connected to each drain of the PMOS transistor of
20. The semiconductor according to claim 13, wherein the sources of the MOS transistors are grounded, and the potentials of the drains of the two NMOS transistors are output as signals. Integrated circuit. 21. A level conversion circuit comprising two PMOS transistors and two PMOS inverters, wherein each of the PMOS inverters comprises one PMOS transistor connected in series.
It comprises a MOS type transistor and one NMOS type transistor. Both gates of the PMOS type and NMOS type transistors are input terminals, and the PMOS type and N type
An output terminal is a serially connected portion of the two MOS type transistors. The complementary signal of a slave latch that outputs a complementary signal is input to input terminals of the two CMOS type inverters. The two PMOS transistors have their drains connected to the sources of the PMOS transistors of the two PMOS inverters, the respective sources connected to a high voltage source, and the NMOS transistors of the two PMOS inverters. The source is grounded, the output terminal of each of the PMOS inverters is connected to the gate of a PMOS transistor on the side not connected in series, and the potential of each output terminal of the two PMOS inverters is output as a signal. 20. A semiconductor integrated circuit according to claim 13, wherein the semiconductor integrated circuit is a semiconductor integrated circuit. 22. The semiconductor integrated circuit according to claim 10, wherein the low voltage source and the high voltage source are respectively input from outside. 23. An input / output pad arrangement area and an internal core part, wherein a plurality of registers and a plurality of combinational circuits are arranged and a memory cell part is arranged in the internal core part. 13. The semiconductor integrated circuit according to claim 10, wherein: