JP2948524B2 - Design method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention is semiconductive in order to produce semiconductor integrated circuits from a register transfer level
Improvement of method of designing a body integrated circuits, in particular, regarding the method for designing a semiconductor integrated circuit for generating a low-power semiconductor integrated circuit
You.

[0002]

2. Description of the Related Art Today, in the design of a semiconductor integrated circuit, a semiconductor integrated circuit to be developed is represented by a function description at a register transfer level (hereinafter, referred to as RTL), and the logic is synthesized using the RTL description. ,
A top-down design for generating a semiconductor integrated circuit to be developed is employed.

FIG. 29 shows a conventional RTL description, and FIG. 30 shows a logic circuit (semiconductor integrated circuit) generated by logic synthesis using the RTL description.

[0004] The RTL description in FIG. 29 is a description that clearly defines data transfer between a plurality of registers at a functional level. In the RTL description shown in the figure, r1, r2, r3, and r4 are registers, func1, func2, func3, and func4 are descriptions of the function of a combinational circuit between the registers. It describes the connection relationship.

In the case of synthesizing logic from the RTL description of FIG. 29, a circuit is determined on a curve of a trade-off between area and speed by giving constraints on area or speed.

In the logic circuit shown in FIG. 30 generated from the RTL description, 101, 103, 105 and 107 are flip-flops in which registers r1, r2, r3 and r4 specified in the RTL description are mapped by logic synthesis. And a register r1, r2 specified in the RTL description of FIG.
Corresponds directly to 2, r3, r4. 108 is the clock buffer, 10
0, 102, 104 and 106 are func1 and Runc of the RTL description in FIG.
This is a combinational circuit corresponding to func2, func3, and func4. The combinational circuits 100, 102, 104 and 106 correspond to the RT of FIG.
It is mapped from the function description of L as one circuit on the curve of trade-off between area and speed.

[0007]

By the way, the power consumption P of the semiconductor integrated circuit can be expressed as follows: operating frequency f, load capacitance C,
As the voltage and V [Equation 1], represented by [Equation 1] P = f x C x V 2. Therefore, there are three methods for reducing the power consumption of the semiconductor integrated circuit: lowering the operating frequency, lowering the load capacity, or lowering the power supply voltage. The reduction effect due to the reduction in the power supply voltage is the largest.

However, when the power supply voltage is set low, the delay time of the critical path having the maximum delay time among many paths constituting the logic circuit also increases.

In view of the above, for example, a technique disclosed in Japanese Patent Laid-Open Publication No. Hei 5-299624, that is, a logic gate which operates at a low speed among a large number of logic gates is driven by a low voltage source,
Utilizing technology for driving other logic gates requiring high-speed operation by a high voltage source, only the logic gates constituting the critical path are driven by a high voltage source, and the other logic gates are driven by a low voltage source. Thus, it is conceivable to reduce the current consumption of the entire semiconductor integrated circuit by using a low-voltage power supply without increasing the maximum delay time of the critical path, thereby achieving low power consumption. However, this idea has the following disadvantages.

The details of the above disadvantages are as follows. As described above, when data is transmitted from a low-speed logic gate driven by a low voltage source to a high-speed logic gate driven by a high voltage source, for example, Japanese Patent Laid-Open No. 5-67963
As disclosed in Japanese Patent Application Laid-Open Publication No. H10-115, it is necessary to arrange a level conversion circuit between the two logic gates for converting the output level of the logic gate driven by the low voltage source to a high level. However, each of the combinational circuits shown in FIG.
Since the circuit is composed of a large number of logic gates as shown in FIG. 1 or FIG. 32, assuming that the critical path in the combinational circuit in each figure is a path indicated by a thick line in FIG. In order to drive with a plurality of positions (in FIG.
It is determined that a level conversion circuit is required at eight locations and at twelve locations in FIG. In a highly integrated semiconductor integrated circuit, the number of combination circuits is extremely large, and the number of logic gates constituting each combination circuit is also extremely large. Therefore, in such a highly integrated semiconductor integrated circuit, the number of positions requiring a level conversion circuit in one combinational circuit having a critical path is large, and the number of combinational circuits having a critical path is large. The number of positions requiring a level conversion circuit in the entire circuit is enormous. As a result, in the design of a highly integrated semiconductor integrated circuit, it is possible to determine and arrange the position where the level conversion circuit is required as described above using a combination circuit that is only partially limited. However, there are drawbacks in that the determination of the arrangement position of the level conversion circuit is complicated and troublesome, takes a long time, and makes the design difficult.

[0011] The present invention has been made in view of mow斯, its object is the method of designing semiconductors integrated circuits, the delay time of the critical path of each combination circuit of the semiconductor integrated circuit as a target of development An object of the present invention is to provide a design method capable of easily generating a low power consumption semiconductor integrated circuit without increasing the number of semiconductor integrated circuits.

[0012]

In order to achieve the above object, the present invention focuses on the following points. First, as shown in FIG. 30, the semiconductor integrated circuit is composed of a large number of registers and a large number of combinational circuits located between the respective registers. It is not necessary to arrange level conversion circuits at various locations inside the combination circuit, that is, at a plurality of positions where a level conversion circuit is required when a critical path is driven by a high power supply. Second, if the level conversion circuit is arranged in the register as described above, in the combinational circuit to which data is transmitted from this level conversion circuit, even if the entire combinational circuit is driven by a high power supply, In a semiconductor integrated circuit, the number of logic gates present on the critical path is approximately 5% of the number of logic gates forming the entire integrated circuit. The ratio of the combinational circuit having a critical path to the entire combinational circuit is small, so that even if the whole combinational circuit having a critical path is driven by a high power supply, the power consumption does not increase much. Third, the maximum delay of the critical path Since the time is sufficient if the time is limited to less than the design delay upper limit, if the entire combinational circuit with the critical path is not driven by the high power supply, but only a part of it is driven by the high power supply, it becomes critical. We focused on the fact that the maximum delay time of a path was shortened, and it was possible to limit the delay to a value equal to or less than a design delay upper limit value, thereby suppressing an increase in power consumption.

In view of the above, the present invention employs a configuration in which, in principle, a level conversion circuit is arranged only in a register and only a part of a combinational circuit having a critical path is driven by a high power supply.

That is, the semiconductor integrated circuit according to the first aspect of the present invention.
The method of designing a path is a combinational circuit with one signal propagation path.
And at least one combinational circuit
Having a register disposed at a stage preceding and succeeding a stage
A method of designing an integrated circuit, wherein when a signal propagation delay time of a signal propagation path of any one of the combinational circuits is equal to or less than a design delay upper limit value, the combination circuit uses a low voltage source as a voltage source. If the signal propagation delay time of the signal propagation path of any one of the combination circuits exceeds the designed delay upper limit, the signal of this combination circuit is generated.
As the signal propagation delay time of the propagation path is less than the maximum delay value of the design, the remainder of the combination circuit low voltage source a voltage with a high voltage source part of the combined circuit and a voltage source
A first step of generating a second combinational circuit as a source;
The remainder of the second combinational circuit using a low voltage source as a voltage source
Another second combination in which the output of the high voltage source is a voltage source
Determining whether the mixed form that is input to a part of the circuit, that
If there is a mixture, the low power of the second combinational circuit
The remainder using the pressure source as the voltage source is referred to as the high voltage source as the voltage source.
And a second step of regenerating a part of the second combinational circuit .

[0015] According to a second aspect of the invention, in a method of designing a semiconductor integrated circuit of claim 1, wherein in the first step, the part of the second combinational circuit is a front portion of the combinational circuit And wherein the remaining part of the second combinational circuit is a rear part of the combinational circuit.

According to a third aspect of the present invention, there is provided the first or second aspect of the invention.
The method for designing a semiconductor integrated circuit according to claim 2, prior
A second combination in which each register is generated or regenerated.
Determines whether the register outputs a signal to the part of the circuit
And one of the registers is the one of the second combinational circuits.
If the register outputs a signal to the
Resistor that uses a voltage source including a high voltage source as the voltage source.
And outputs a signal to the part of the second combinational circuit.
If this register is not a register to output,
A third step of generating in a register using the pressure source as a voltage source;
It is characterized by doing.

According to a fourth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the second aspect, the first step includes:
First, all combinational circuits are converted using the first combinational circuit.
Generating , and then determining whether the signal propagation delay time of the generated first combinational circuit exceeds a design delay upper limit. If there is a first combinational circuit exceeding the design delay upper limit, the, characterized by regenerating the front of all of the first combining circuit to the part of the second combinational circuit.

The invention according to claim 5 is the invention according to claim 2 ,
In the method for designing a semiconductor integrated circuit according to claim 3 or claim 4 , when the first step includes a first combinational circuit in which a signal propagation delay time exceeds a design delay upper limit value. First, the first combinational circuit is conceptually divided into a plurality of combinational parts, and the first combinational part is first driven by a high voltage source.
Regenerate the combination unit being, then, the signal propagation delay time of the combination circuit after regeneration it is determined whether or not exceeding the maximum delay value of the design, then the signal propagation of a combination circuit after regeneration If the delay time still exceeds the designed delay upper limit, the high voltage source drives the next combination unit located in the signal propagation direction in the first combination circuit.
It is characterized in that the re- generation of the combined part and the determination of the signal propagation delay time after the generation are repeated.

[0019] According to a sixth aspect of the invention, in a method of designing a semiconductor integrated circuit of claim 4, wherein in the first step, a voltage source the low voltage source in the second combinational circuit
A second combination using the high voltage source as a voltage source.
Before regenerating part of the circuit , before the second combinational circuit
The remainder is conceptually divided into a plurality of combination parts, and the regenerated part is regenerated in the part of the second combination circuit among the plurality of combination parts.
A set combined unit which, using a binary search, the signal propagation delay time of the second combinational circuit less the maximum delay value of the design
Made up, characterized in that repeated to explore.

According to a seventh aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the second aspect, the first step includes:
First, using the register driven by the first combinational circuit and the low voltage source, the signal propagation delay time of the register driven by the low voltage source and the first combinational circuit is estimated, and It is determined whether or not the estimation result exceeds the designed delay upper limit value. If there is a first combinational circuit that is equal to or less than the designed delay upper limit value, the first combinational circuit is replaced with the first combined circuit. generated, if the first combination circuit, wherein the estimation result exceeds the maximum delay value of the design is present, the first combining circuit, the high voltage source portion
Is the voltage source and the rest is the low voltage source as the voltage source.
2 is a step of generating the combinational circuit .

According to an eighth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the seventh aspect , in the first step, the result of estimating the signal propagation delay time exceeds the design delay upper limit value. When there is a combinational circuit, the first combinational circuit is conceptually divided into a plurality of combination units, and the second combinational circuit is divided based on the ratio between the estimation result of the signal propagation delay time and the design delay upper limit. raw the balance between the number of combination parts to be generated as part the second combinational circuit of the circuit
Calculating a ratio between the number of combination parts to be formed, then, on the basis of the percentage of the number and the calculation of combination parts which constitute the first combining circuit, as part of the second combinational circuit
Calculating a generation all-out range, then the combined unit in the range where the calculated, to generate a portion of the second combinational circuit to the voltage source a high voltage source, without combining unit to the range , Low power
The voltage is generated in the remainder of the second combinational circuit using the voltage source as the voltage source .

The ninth aspect of the present invention is the above-mentioned first or second aspect.
The method for designing a semiconductor integrated circuit according to claim 3 wherein, prior to the first step, specifies the components sac Chi part of the combinational circuit, a voltage source the high voltage source portion that is the designated When
And a step of disposing a level conversion circuit using a high voltage source as a voltage source at a stage preceding the generated part .

According to a tenth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the ninth aspect , a part of the specified combination circuit is a rear part of the combination circuit.

According to an eleventh aspect of the present invention, in the method for designing a semiconductor integrated circuit according to the ninth or tenth aspect , the designation is to supply a high voltage source among components of the combinational circuit.
This is performed by a function description including a description designating a part as a pressure source, and the function description is input before the first step.

According to a twelfth aspect of the present invention, in the method for designing a semiconductor integrated circuit according to the ninth or tenth aspect , the high voltage source is used as a voltage source after the second step. determines whether the level conversion circuit exists between a portion of the part and other high voltage source and voltage source, when the level conversion circuit is present, a step of deleting the level conversion circuit It is characterized by the following.

According to a thirteenth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect, in the first step, in the combinational circuit, a signal propagation delay time exceeds a design delay upper limit value. A plurality of windows of a predetermined size are set as a search range, and a window having the smallest total area or the smallest delay of the combination part in each of the plurality of windows is selected. The high voltage source is a voltage source.
The signal transmission is defined in the part of the second combinational circuit
With transportable delay time to produce a combined circuit exceeding the maximum delay value on design <br/> second combinational circuit, first and the generating 2
A level conversion circuit using a high voltage source as a voltage source is arranged at a stage preceding the part of the combinational circuit.

The invention according to claim 14 is the invention according to claim 13.
In the method for designing a semiconductor integrated circuit described above, the predetermined size of the window is calculated based on the signal propagation delay time and the designed upper limit of delay.

According to a fifteenth aspect of the present invention, the thirteenth aspect is provided.
In the method for designing a semiconductor integrated circuit described in the above, the second step
After the second combinational circuit , the high voltage source of the second combinational circuit is used as a voltage source.
One of the parts and the high voltage source the other second combining circuit a voltage source
It is characterized in that it has a step of determining whether or not there is a level conversion circuit between the first and second sections and, if there is a level conversion circuit, deleting this level conversion circuit.

The invention according to claim 16 is the invention according to claim 1 ,
In the design method <br/> a semiconductor integrated circuit according to claim 2 or claim 3, wherein, the second step, the low-voltage of the second combinational circuit
The remainder using the pressure source as the voltage source is referred to as the high voltage source as the voltage source.
As a result of regenerating part of the second combinational circuit ,
The output of the remainder of any of the second combinational circuits is the reproduction
Whether mixed form the input to the part of the second combinational circuit is formed occurs is determined, a second combination of the remainder of the second combinational circuit if the mixed occurs circuit
Characterized by a step of repeating the regeneration of the part .

According to a seventeenth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect, the register transfer level design data describing a plurality of registers and a plurality of combinational circuits located between the registers is provided. type, generates a connection information of logic cells from the design data of the entering force the register transfer level, the logic
The first combinational circuit and the second combinational circuit based on cell connection information;
Is generated .

[0031] The invention of claim 18, wherein, in the method for designing a semiconductor integrated circuit of claim 1, enter the net list describing the connection information of logic cells, as described in the entering force the netlist logic based on the connection information of the cell
Generating the first combinational circuit and the second combinational circuit .

[0032] The invention of claim 19, wherein, in the method for designing a semiconductor integrated circuit of claim 1, enter the schematic representation of the connection information of logic cells, the logic cell represented in the entering force the schematic based on the connection information
Generating the first combinational circuit and the second combinational circuit .

[0033] According to the twentieth aspect , in the first aspect,
7, the semiconductor integrated circuit according to claim 18 or claim 19, wherein
In the design method , the connection information of the logic cell based on the input register transfer level, the input netlist, or the input schematic is optimized, and the first information is based on the optimized connection information of the logic cell . set
A combination circuit and a second combination circuit are generated .

The invention according to claim 21 is the invention according to claim 3.
The method for designing a semiconductor integrated circuit described above is characterized in that after the third step, a step of verifying the timing of each register is provided.

The semiconductor integrated circuit according to the twenty-second aspect of the present invention
The design method involves combining a combinational circuit with one signal propagation path.
Number and before said at least one combinational circuit
Semiconductor integrated circuit including a stage and a register arranged at a subsequent stage
A method of designing a circuit, signal of said one of the combinational circuit
When the signal propagation delay time of the signal propagation path is equal to or less than the design delay upper limit, a step of generating the combination circuit in a first combination circuit using a low voltage source as a voltage source; If the signal propagation delay time of the signal propagation path exceeds the design delay upper limit, the signal propagation
A portion of this combined circuit to transportable delay time is less than the maximum delay value of the design as well as a voltage source a high voltage source, a second combination of a low-voltage source the remainder of the combination circuit and a voltage source Generating in a circuit, the second combination
In the path generation process, the signal propagation delay time is
In combinational circuits exceeding the extension upper limit,
Set a plurality of windows of a predetermined size, and
Combination part in each window among windows
Window with the smallest total area or minimum delay
And select the combination in the selected window
Of the combinational circuit of (2) with the high voltage source as the voltage source
Characterized in that that.

The invention according to claim 23 is the invention according to claim 22.
In the method for designing a semiconductor integrated circuit described above, the predetermined size of the window is calculated based on the signal propagation delay time and the designed upper limit of delay.

According to the above construction, claims 1 to
The method of designing a semiconductor integrated circuit described in 21 has the following effects. That is, a semiconductor integrated circuit has a plurality of combinational circuits .
And, a portion of the combinational circuit among the plurality of combinational circuits has a critical path. Only a part of the signal propagation path of the combinational circuit having the critical path is driven by the high voltage source, and the rest of the signal propagation path is driven by the low voltage source. Other combinational circuits having no critical path are driven by a low voltage source. Here, since a part of the combinational circuit having the critical path is driven by the high power supply, the time delay of the critical path can be suppressed to less than the delay upper limit allowable in design.

Further, the low voltage source of the second combinational circuit
The output of the driven remainder is high among other second combinational circuits.
When there is a mixture of shapes that are input to a part driven by a voltage source
In the case, the rest driven by the low voltage source is driven by a high voltage
Re-synthesize as follows. Therefore, the two second unions
It is no longer necessary to arrange registers between the interlock circuits, and the register located before the combinational circuit having a critical path, that is, the register that transmits data to this combinational circuit,
Since only one level conversion circuit can be arranged, the number of required level conversion circuits can be reduced as compared with a case where only a combinational circuit having a critical path is driven by a high voltage source. Design becomes extremely easy. In addition, the number of combinational circuits having a critical path is extremely small in view of the entire combinational circuit, and only a part of the signal propagation paths of the extremely small number of combinational circuits is driven by a high voltage source. Less suppressed. On the other hand, the rest of the combinational circuits having the critical path and many combinational circuits having no critical path are driven by a low power supply, so that the power consumption is significantly reduced. As a result, power consumption is significantly reduced in the entire semiconductor integrated circuit.

In particular, there is provided a semiconductor integrated circuit according to claim 5.
In the measuring method , in one combinational circuit, one combination unit is driven by a high voltage source one by one from a signal input side.
Since it generated the section, the boundary between the part and the remainder of the one combination circuit, i.e., driven by a high voltage source in a single combinational circuit
It is possible to find the boundaries of a combination part driven by the combination unit and the low voltage source accurately, the number of combinations portion to a voltage source a high voltage source to limit to a minimum, low even more Power consumption.

The semiconductor integrated circuit according to claim 6 is provided.
In the summation method , since the boundary between a part of one combinational circuit and the rest is easily searched by a binary search method, logic synthesis or the like is performed.
The design can be speeded up.

Further, the semiconductor integrated circuit according to claim 8 is provided.
In the measurement method , the boundary between a part of one combinational circuit and the rest is more easily searched based on the ratio between the estimation result of the signal propagation delay time and the upper limit of the designed delay . The design can be further speeded up.

In addition, the half of claim 9 and claim 10
In the design method of the conductor integrated circuits, the combination is driven one Runode be synthesized <br/> the combination part driven a particular combination unit with a high voltage source in a combinational circuit, a high voltage source which requires If it is known in advance that the number of parts can be reduced, such a specific combination part can be designated, so that the required height can be reduced.
The number of combination units driven by the voltage source and the number of required level conversion circuits can be reduced.

In addition, according to claims 13, 22 and 23 ,
In a method of designing a semiconductor integrated circuit, a part to be driven by a high voltage source in one combinational circuit is searched using a window, and a total area (number) of combinational parts or a window having a minimum delay is searched. A part to be driven by the high voltage source is set, and a part in which the high voltage source is used as a voltage source in this window.
Generate as Therefore, it is driven by the required high voltage source.
Since the number of combinations portion to be less, Ru can der improve power consumption or the processing speed.

[0044]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of an image processing apparatus A having a semiconductor integrated circuit according to the present invention. In FIG. 1, reference numeral 10 denotes an A / D converter for converting an external signal from analog to digital, 11 denotes a general-purpose DRAM, and 12 denotes a semiconductor integrated circuit of the present invention, which takes out data from the DRAM 11 or stores data. A first semiconductor integrated circuit 13 for performing image processing, 13 is a general-purpose control microcomputer for controlling the first semiconductor integrated circuit 12, and 14 receives a signal from the first semiconductor integrated circuit 12 to further perform image processing. This is a second semiconductor integrated circuit to be performed.

Reference numeral 15 designates, for example, 3 V
The high-voltage source 16 is also a low-voltage source, for example 2 V, externally arranged. The image processing apparatus A shown in FIG. 1 includes a high-voltage line 17 connected to the high-voltage source 15 and the low-voltage source 1.
6 connected to the low-voltage wiring 18. In order to reduce the power consumption of the image processing apparatus A, the low voltage source 16 is used as a voltage source for the first and second semiconductor integrated circuits 12 and 14 for image processing. It is supplied only to the first and second semiconductor integrated circuits 12 and 14. On the other hand, the high voltage of the high-voltage wiring 17 is applied to other general-purpose circuits 10, 1
1, 13 are supplied. Since the interface voltage between the circuits 10 to 14 needs to be high, the high voltage wiring 17
High voltage is applied to two semiconductor integrated circuits 12, 1 for image processing.
4 as well.

The low voltage source 16 may be an internal low voltage source in which the voltage of the high voltage wiring 17 is reduced by an internal transistor by the threshold voltage. The configuration is described in, for example,
96369, the details of which are omitted. In this case, the low voltage source 16 arranged outside is unnecessary.

The first semiconductor integrated circuit 1 for image processing
FIG. 2 shows the internal configuration of No. 2. In the figure, reference numeral 20 denotes a chip, 21... Are a plurality of input / output pads arranged on the outer periphery of the chip 20, and 22 is the plurality of input / output pads 2.
The internal core portion 22 is provided with five functional blocks A to E except for the arrangement region of 1. The functional blocks A to D are arithmetic processing circuits that perform different arithmetic processing, and the functional block E is, for example, a ROM.
, A small-capacity memory cell such as a RAM.

The present invention is applied to the function blocks A to D other than the function block E including the memory cell section in the internal core section 22 in the first semiconductor integrated circuit 12 for image processing. .

FIG. 3 shows a logic circuit diagram of an arbitrary one of the functional blocks (for example, A) of the first semiconductor integrated circuit 12.

The functional block (part of the semiconductor integrated circuit) shown in FIG. 14 shows a logic circuit obtained by performing logic synthesis from the RTL description shown in FIG. 29, reference numerals 2, 4, 6, and 8 denote registers r1, r2, r3, and r3 of the RTL description of FIG.
This is a flip-flop circuit constituting r4. Each of the registers r1 to r4 is applied to various registers such as a register constituting a part of a pipeline processing circuit of a computer. Also, 1, 3, 5 and 7 are combinational circuits func1, func2, fu described in the RTL description of FIG.
nc3 and func4 are combinational circuits located between the registers r1 to r4 or at the preceding stage. In FIG. 3, for the sake of simplicity, the output of each combinational circuit is input only to the flip-flop circuit at the next stage, but the signal may be transferred to another combinational circuit.

The flip-flop circuits 2, 6, and 8 are 2V systems using the 2V low voltage source 16 as a voltage source.
The remaining flip-flop circuit 4 has a voltage source of 2V / 3 using both power sources of a low voltage source 16 of 2V and a high voltage source 15 of 3V.
It is a V system. The 2V / 3V flip-flop circuit 4 has a level conversion circuit as described later, and the 2V flip-flop circuits 2, 6 and 8 do not have a level conversion circuit. Further, the combination circuits 1, 3 and 7 are 2V combination circuits (first circuit) using a 2V low voltage source 16 as a voltage source.
The remaining combinational circuit 5 is composed of a 3V combinational circuit (second combinational circuit) using a high voltage power supply 15 of 3V at the front as a voltage source, because of the demand for high-speed operation. 2 uses a low voltage source 16 of 2V as a voltage source.
It consists of a V-system combination circuit (first combination circuit).

In addition, 9 is a 2V clock buffer (clock supply means) using a 2V low voltage source 16 as a voltage source.
Wherein the four flip-flop circuits 2, 4,.
Clock is supplied to 6 and 8.

FIG. 4 shows the configuration of the flip-flop circuits 2, 6, and 8 having no 2V-system level conversion circuit. In the figure, reference numeral 30 denotes a master latch for receiving one external signal D, and 31 denotes a slave latch which is connected in series to the output side of the master latch 30 and outputs two complementary signals. The slave latch 31 forms a temporary data storage unit 36. Each of the latches 30 and 31 is connected to an inverter 34.
a, 34b. 32 is the slave latch 31
The output buffer 33 connected to the output side of the internal clock CK and NCK complementary to the externally input clock CLK
Clock generation circuit (clock supply means) for generating clock
These circuits 30 to 33 are provided with a low voltage source 1 of 2V.
6 is a 2V system using a voltage source.

FIG. 5 shows the configuration of the flip-flop circuit 4 having the 2V / 3V system level conversion circuit. The flip-flop circuit 4 shown in FIG.
A master latch 30 and a slave latch 31 connected in series with the same configuration as the flip-flop circuit 2 of the system, an internal clock generation circuit 33, an output buffer 34 using the 3V high voltage source 15 as a voltage source, A level conversion circuit 35 is provided between the latch 31 and the output buffer 34. The level conversion circuit 3
Reference numeral 5 denotes a 2V / 3V system, in which the potential difference between complementary signals of the 2V system slave latch 31 is a low voltage (2V). Has a function of converting the level into a high voltage signal in which the potential difference between the signals is high voltage (3 V) and outputting the high voltage signal.

FIGS. 6A and 6B show a specific configuration of the level conversion circuit 35. FIG. In the level conversion circuit 35 of FIG. 7A, reference numerals 40 and 41 denote PMOS transistors, and reference numerals 42 and 43 denote NMOS transistors.
One PMOS type transistor 40 and one NMOS type transistor 42 are connected in series, and the other
The S-type transistor 41 and the other NMOS-type transistor 43 are connected in series.
Between the high voltage source 15 and the ground. The gate of the one PMOS transistor 40 is connected to the drain of the NMOS transistor 43 on the side not connected in series, and the gate of the other PMOS transistor 41 is connected to the drain of the NMOS transistor 42. The complementary output is taken from the drains of the NMOS transistors 42 and 43.

With the above configuration, the PMOS transistor 40 and the NMOS transistor 42, and the PMOS transistor 41 and the NMOS transistor 43 each perform the function of an inverter. That is, when a low voltage of 2 V is supplied to the gate of one NMOS transistor 43 and 0 V is supplied to the gate of the other NMOS transistor 42 by the complementary output of the slave latch 31 in FIG. The NMOS transistor 43 is turned on and the other NMOS transistor 42 is turned off.
F, and accordingly, one PMOS transistor 40 is turned on and the other PMOS transistor 41 is turned on.
Since the FF is performed, the drain of one NMOS transistor 42 is connected to the high voltage source 15 of 3V, and the drain of the other NMOS transistor 43 is grounded.
A complementary output with a high potential difference of 3 V is obtained.

In the configuration of FIG. 6A, the high voltage source 1 of 3 V
The complementary output of the slave latch 31 of FIG. 5 is output from the low voltage of 2V without passing through current from the low voltage source 16 of 5 to 2V and through current from the high voltage source 15 of 3V to 0V (ground). The level can be converted to a high voltage of 3V.

FIG. 6B shows a level conversion circuit 35 'having another specific configuration different from the above. The level conversion circuit 35 'shown in FIG.
Instead of the two NMOS transistors 42 and 43,
This is one in which CMOS inverters 45 and 46 are arranged. Each of the CMOS inverters 45 and 46 is formed by connecting one PMOS transistor 47 and 49 and one NMOS transistor 48 and 50 in series. The complementary output signal of the slave latch 31 of FIG. 5 is input to the input terminals of the CMOS inverters 45 and 46, that is, both gates of the PMOS and NMOS transistors 47, 48, 49 and 50 connected in series. Is done. The output terminal of one CMOS inverter 45, ie, PMO
S type transistor 47 and NMOS type transistor 4
8 is connected to the gate of the PMOS transistor 41 not connected in series to the CMOS inverter 45, and the output terminal of the other CMOS inverter 46 is connected to the gate of the PMOS transistor 40 not connected in series to the CMOS inverter 46. Connected. The outputs of both CMOS inverters 45 and 46 are complementary outputs of the level conversion circuit 35 '.

With the above configuration, the through current from the high voltage source 15 of 3V to the low voltage source 16 of 2V and the through current from the high voltage source 15 of 3V to the ground flow through the slave latch 31 of FIG. The level of the complementary output can be converted from a low voltage of 2V to a high voltage of 3V. Furthermore, CMOS
The PMOS transistors forming the type inverters 45 and 46 suppress a through current from the 3 V high voltage source 15 to the ground in the transient state.

As can be seen from the above description, the semiconductor integrated circuit shown in FIG.
The flip-flop circuit 2 having a low-voltage / low-voltage 2V-system combination circuit 3 at the input and the 3V / 2-V-system combination circuit 5 at the output has a low-voltage / The flip-flop circuit 6 which is composed of a high voltage system (2 V / 3 V system), has a 3 V / 2 V system combination circuit 5 at the input and has a 2 V system combination circuit 7 at the output, is composed of a low voltage 2 V system Have been.

In the above description, the registers r1, r2, r
Although 3 and r4 are configured by flip-flop circuits, they may be configured by latch circuits instead of the flip-flop circuits.

FIGS. 7 and 8 show a specific configuration of the latch circuit. FIG. 7 shows a low-voltage 2V-system latch circuit 51. A latch circuit 51 shown in FIG. 7 includes a latch section (data temporary storage section) 52 which receives and latches one signal D and obtains a complementary output, and an output buffer 53 connected to the output side of the latch section 52. , An internal clock NG is generated from the external clock G, and this internal clock NG is
And an external clock G is also provided to the latch unit 52.
The above circuits 52 to 54 are 2V systems using the 2V low voltage source 16 as a voltage source.

FIG. 8 shows a low voltage / high voltage system (2V / 3V system).
Is shown in FIG. The latch circuit 51 'of FIG.
Is the same as that of the low-voltage 2V latch circuit.
A latch unit 52 and an internal clock generation circuit 54 using the V low voltage source 16 as a voltage source, an output buffer 55 using a 3 V high voltage source 15 as a voltage source, and a connection between the latch unit 52 and the output buffer 55 Input signal to a low voltage (2
V) to a high voltage (3 V). The specific configuration of the level conversion circuit 56 is the same as the specific configuration shown in FIG. 6A or 6B.

Next, an algorithm of a logic synthesis method for logic-synthesizing the semiconductor integrated circuit shown in FIG. 3 based on the connection information of the logic cells will be described with reference to the logic synthesis apparatus of FIG. 9 and the flowchart of FIG. .

FIG. 9 shows the overall schematic configuration of the logic synthesis device 60. In the figure, 61 is a reading unit, 62 is a translation unit, 63 is an optimization processing unit, 64 is a cell allocation unit, 65 is a timing verification unit, 66 is a circuit diagram generation unit, and 67 is an output unit.

The reading unit 61 clearly defines the signal transmission relation between registers based on the RTL description (hardware description language) shown in FIG. 29 or FIG. The netlist shown in FIG. 11 or FIG.
Enter the schematic shown in.

The translation unit 62 converts the RTL description read from the reading unit 61 into a state transition diagram, a Boolean expression, a timing diagram, and memory specifications such as memory type, number of bits and number of words.

The optimization processing unit 63 includes a state transition diagram optimization processing unit 63a that optimizes the obtained state transition diagram and a state that generates a circuit (state machine) corresponding to the optimized state transition diagram. A machine generator 63b, a compiler 63c for compiling a timing diagram obtained for compiling the obtained timing diagram, a composing unit 63d for composing a memory based on the specification of the obtained memory, Combining unit 63 for combining the interface unit based on the stored memory
e. Further, the optimization processing unit 63 includes the reading unit 6
If the input to 1 is an RTL description, the logic is optimized based on the obtained state machine, the obtained Boolean expression and the synthesized interface unit, and the connection information of the optimized logic cell is obtained. While generating, the reading unit 61
In the case where the input to is a netlist or schematic, there is a logic optimization unit 63f that optimizes the logic of the input netlist or schematic and generates connection information of the optimized logic.

The output section 67 externally outputs a netlist indicating the logic circuit of FIG. 3 or a logic circuit diagram (schematic) obtained by schematizing the netlist.

The present invention exists in the cell allocating section 64 shown in FIG. Next, based on the cell allocation (cell mapping) processing by the cell allocation section 64, ie, the cell connection information obtained by the logic optimization section 63f, FIG.
The algorithm for logically synthesizing the semiconductor integrated circuit shown in FIG. 1 will be described with reference to the flowchart of FIG. Note that FIG. 13 mainly illustrates features of the present invention.

In the figure, starting and step S
After performing a function design using HDL (hardware description language) in step 1, the HDL description is input in step S2, and based on the input HDL description, a high voltage is output from a logic cell library shown in the table of FIG. (3V) logic cell library (hereinafter referred to as “lib”) is selected, and this 3V
The combination circuit is mapped by lib.

Next, in step S3, after calculating the maximum delay time of the mapped combinational circuit, it is determined whether or not this maximum delay time exceeds the designed delay upper limit value. Creates a new HDL description by correcting the input HDL description or redoing the function design in step S4. For example, in the partial circuit shown in FIG. 15, when a combinational circuit f is located between two registers r1 and r2 and the function of the combinational circuit f is composed of functions A and B, the combinational circuit f When the maximum delay time exceeds the delay upper limit value, as shown in FIG. 16, the combinational circuit f is divided into two combinational circuits f1 and f2, and the function A is assigned to the combinational circuit f1,
2 has a function B, and the two combination circuits f1,
HDL so that one register is separately arranged between f2 and three registers r1 to r3 are provided in total.
The description is modified from the function description shown in FIG. 17 to the function description shown in FIG.

Thereafter, in steps S5 to S9 (first step), the combinational circuit whose signal propagation delay time is equal to or less than the designed delay upper limit value is set to the 2V low voltage source 1
6 is combined with a first combinational circuit having a voltage source, and a combinational circuit having a signal propagation delay time exceeding a design upper limit of delay has a high voltage source 15 of 3 V at its front as a voltage source. To
When both synthesize its rear to a second combining circuit to a voltage source of low-voltage source 16 of 2V.

In the present embodiment, the first step is performed as follows. That is, first, in step S5, all the combinational circuits are combined by a low-voltage (2V) combinational circuit (first combinational circuit), and then in step S6, the signal propagation delay time of each combined circuit is calculated. It is calculated for each signal propagation path. Then, extracted the calculated delay time to determine whether it exceeds the upper limit of the design, if exceeding the upper limit, the delay time at the step S 7 is all combinational circuit exceeds the upper limit of the design After that, the combining operation of steps S8 and S9 is performed for each of the extracted combinational circuits.
That is, as consisting of a combination of plural combinational circuits that the extracted respective (m pieces), n th (initially n = 1) a high voltage (3V) system combining portion of the combination portion in step S8
After the re-synthesis by the combination circuit (the second combination circuit), the maximum delay time of the re-synthesis combination circuit is compared with an upper limit in design in step S9. The next combination part (n = second combination part) located in the propagation direction is a high-voltage (3 V) combination
Re-synthesis is performed by a combinational circuit (second combinational circuit) as a part. The above operation is repeated until the maximum delay time of the combinational circuit after re-synthesis becomes equal to or less than the upper limit in design.

Subsequently, in steps S10 to S12 (second step), the following processing is performed. That is, in step S10, the combination of the 2V system is such that the output of the combination unit of the low voltage system (2V system) becomes the input of the combination unit of the high voltage system (3V system).
It is checked whether or not there is a mixture of the combination part and the combination part of the 3V system. If there is a mixture of the above forms, all the combination parts of the 2V system in the mixture form are extracted in step S11, and then, in step S12. in 3Vli combination of 2V system and the extracted
The mapping is performed again so as to be replaced by the combination part of b. After this remapping, the process returns to step S10, and the operations of steps 11 and S12 are repeated again. This is that mixed due to remapping to the combination of the 3V type with 2V system combining unit and the 3V system combining unit <br/> of at step 12 in some cases will occur anew Is considered.

After that, since the voltage systems of the combinational circuits located on the input side and the output side of the register have already been determined by the above-described logic synthesis, steps S13 to S15
In the (third step), the following processing is performed. That is, step S
At 13, it is checked whether or not each register converts the potential from a low voltage (2V) input to a high voltage (3V) output.
If the level conversion is not to be performed, the register whose level is not to be converted is mapped to the 2V system flip-flop circuit in FIG. 4 or the 2V system latch circuit in FIG. 7 if the level conversion is to be performed. Register (flip-flop circuit or latch circuit)
8 or the 2V / 3V flip-flop circuit shown in FIG.
2V / 3V system latch circuit.

Therefore, according to the algorithm of the logic synthesis method shown in FIG. 13, when all the combinational circuits are mapped by a low-voltage (2 V) combinational circuit (first combinational circuit), for example, FIG. As shown, when the delay time of the signal propagation path of one combinational circuit 70 located between two predetermined registers exceeds the designed delay upper limit, as shown in FIG. Among them, as shown by hatching in the figure, the first and second combination parts 70a and 70b located at the front part (the starting point of signal propagation)
After mapping to the combination circuit of the system, when the combination unit of the 2V system and the combination circuit of the 3V system in which the output of the combination unit of the 2V system becomes the input of the combination circuit of the 3V system,
As shown in FIG. 11C, the combination part 71a of the mixed 2V combination circuit 71 is remapped to a 3V combination part as shown by hatching in the figure. Subsequently, it is determined whether or not a new mixture of the 2V-system combination part and the 3V-system combination part has newly occurred by the remapping. In FIG. In the case where it is necessary to level-convert the potential from a low-voltage (2 V) input to a high-voltage (3 V) output, FIG.
As shown in the figure, the flip-flop circuit for level conversion is mapped to a 2V / 3V system flip-flop circuit as shown by hatching in the figure.

Therefore, in the finally obtained semiconductor integrated circuit shown in FIG. 9D , a set having one signal propagation path
In the matching circuit 70, the delay time of the signal propagation path
If the delay exceeds the design upper limit, the signal propagation path
Of the high voltage (3
V) Generated by the combination part of the system, and
Generates the combination part located in the low voltage (2V) system combination part
Since the the combinational circuit (second combinational circuit), the combination of the 3V type with all combinations of the combination circuit 70 a signal propagation delay time as shown in FIG. (E) exceeds the maximum delay value of the design Compared with the case where mapping is performed, the number of combination parts to be mapped to the combination part of the 3V system can be reduced, so that power consumption can be reduced.

(Second Embodiment) FIG. 20 shows a second embodiment of the present invention. In the present embodiment, the boundary between the front part and the rear part of the combinational circuit, that is, 3V
Search method to determine the boundary between the combination part to be combined with the combination circuit of the system and the combination part to be combined with the combination circuit of the 2V system
(for example, see "Iwanami Koza Software Science 2 Programming Method" by Kei Iwanami, Iwanami Shoten, 1988, pp. 143 and 144).

That is, steps S18 to S27 (first
In the step (b), the boundary between the front part and the rear part of the combinational circuit is searched using the binary search method, and the front part is synthesized into a second combinational circuit using the 3V high voltage source 15 as a voltage source. The subsequent part is combined with a first combinational circuit using the 2V low voltage source 16 as a voltage source.

More specifically, in the first step,
In step 18, first, all the combinational circuits are mapped by a low-voltage (2V) combinational circuit, and in step S19, whether or not each maximum delay time of each combinational circuit exceeds a design upper limit value. Is determined, and if it exceeds, all such combinational circuits are extracted in step S20, and the operations of steps S21 to S27 are performed on all the extracted combinational circuits. First, in step S21, the addresses of the first and last combination units to be mapped by the 2V-system combination circuit are set to ks and ke, and these addresses are set to ks
= 1 and ke = m (m is the number of combination units constituting the combinational circuit), and then, in step S22, it is determined whether or not ke-ks = 1, and if ke-ks = 1, Can not be 2 minutes and immediately proceeds to the second step, but initially k
Since e−ks ≠ 1, the intermediate value k is calculated by the following equation k = (ks + ke) / 2 in step S23, and the first to k-th combination parts are mapped by the 3V system lib in step S24. , K +
The first to m-th combination parts are mapped by the 2V-system lib.

Thereafter, the maximum delay time of the combinational circuit after the mapping is calculated, and in step S25, this delay time is compared with the upper limit of the designed delay. In step S26, the first address ks is set to the obtained intermediate value k (ks = k) in order to further divide the combination part into 2 (ks = k). In step S27, the last address ke is set to the intermediate value k (ke = k) in order to further divide the combination part into two.
Return to If ke-ks = 1 in step S22, it is determined that the boundary between the front part and the rear part of the combinational circuit has been searched by the binary search method, and the process proceeds to the second step.

Since the second step and the third step are the same as those in the first embodiment, FIG.
The same steps as those in the flowchart of FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.

Therefore, in this embodiment, for example, when a combinational circuit composed of 20 stages of logic gates has a critical path, first, the first 10 stages are 3Vlib and the second 10 stages are along the signal flow. To 2Vlib
After re-synthesizing, the condition of maximum delay> upper limit is checked, and YE
If S, the last 10 stages are further divided into two, and the 5 stages connected to the end point are recombined into 2 Vlib and the others into 3 Vlib. If NO, the first 10 stages are further divided into two, and the 5 stages connected to the starting point are recombined into 3Vlib and the others into 2Vlib. Further, the condition of maximum delay> upper limit is checked, and this process is repeated. If the binary search method is used, the boundary can be searched by several resynthesis processes, so that the processing can be speeded up.

(Third Embodiment) FIG. 21 shows a third embodiment of the present invention. In the present embodiment, the configuration is such that the boundary between the front part and the rear part of the combinational circuit is roughly estimated.

That is, in the figure, after starting, a functional design using HDL is performed in step S1, and a high-voltage (3V) lib is generated based on the HDL description in step S2.
The signal propagation delay time of each combinational circuit when the combinational circuit is mapped is estimated in step S3, and it is determined in step S3 whether or not the estimation result exceeds a design delay upper limit value.
If it exceeds the delay upper limit value, a new HDL description is created in step S4 by modifying the input HDL description or redoing the function design as shown in FIGS.

Thereafter, in steps S30 to S37 (first step), the boundary between the front part and the rear part of the combinational circuit is roughly calculated, and the front part is determined using the high voltage source 15 of 3V as the voltage source. 2 and a subsequent portion is combined with a first combinational circuit using the 2V low voltage source 16 as a voltage source.

More specifically, in the first step,
First, in step 30, all the combinational circuits are set to 2Vlib.
The signal propagation delay time of each combinational circuit when mapping is performed is estimated, and the respective delay times are compared with the designed delay upper limit value in step S31. If the delay time is equal to or smaller than the upper limit value, the delay time is determined in step S32. The following combinational circuit
Mapping by Vlib.

On the other hand, if the delay time exceeds the upper limit value, all the combinational circuits whose delay estimation results exceed the upper limit value are extracted in step S33, and then the processing in steps S32 and S34 to S37 is performed on each of the combinational circuits. Perform the operation. First, in step S34, the result of delay estimation is divided by the upper limit value, and the existence ratio p of 3Vlib and 2Vlib is calculated based on the result of the division. In step S35, the number of stages of the logic gate (combination unit) constituting the combinational circuit And the ratio p
To calculate the mapping range of 3Vlib, that is, the range of the logic gates constituting the front part. Thereafter, in step S36, it is determined whether or not each logic gate is within the calculated 3Vlib mapping range. If so, the logic gate is mapped by 3Vlib in step S37. Is Step S
At 32, the logic gate is mapped by 2Vlib.

Since the second step and the third step are the same as those in the first embodiment, FIG.
The same steps as those in the flowchart of FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.

Therefore, in the present embodiment, for example, when the delay of 3 Vlib is set to “1”, 2 Vlib
Assuming that the delay of the critical path is 1.8 and the upper limit of the designed delay is 50 ns, when the delay of the critical path is 90 ns,
The entire critical path is set as a synthesis range of 3Vlib.
Further, when the delay of the critical path is 50 ns, there is no 3Vlib synthesis range of the critical path, and all the combination parts are synthesized with 2Vlib. When the delay of the critical path is 60 ns, a range of 1/4 from the starting point of the critical path is the front part, and this range is 3 Vlib.
In the case of 70 ns, the range of か ら from the starting point of the critical path is the front part, and synthesized at 3 Vlib. In the case of 80 ns, the range of ／ of the starting point of the critical path is the front part. And synthesized with 3Vlib.

In the present embodiment, since the boundary between the combination part synthesized by 3Vlib and the combination part synthesized by 2Vlib (the boundary between the front part and the rear part) is roughly calculated, the processing speed of logic synthesis is high. . However, the calculation accuracy of the boundary is not high. In normal logic synthesis, once logic synthesis is performed, synthesis may be performed again based on the synthesis result to optimize the circuit. In this case, the first logic synthesis is performed according to the present embodiment. If the subsequent re-synthesis is performed according to the first or second embodiment, the accuracy of the boundary calculation is increased while the processing speed of the logic synthesis is improved, and the combination unit synthesized by the high voltage (3V) lib is used. Can be limited to a minimum, and the power consumption can be further reduced.

(Fourth Embodiment) FIG. 22 shows a fourth embodiment of the present invention. In the present embodiment, when it is known in advance that mapping a predetermined combination part with 3 Vlib among a plurality of combination parts constituting a combinational circuit can synthesize a semiconductor integrated circuit having better power consumption, Such a predetermined combination is designated in advance to perform mapping by 3Vlib.

That is, in the logic synthesis method of FIG.
Steps S40 to S45 are added before the first step (steps S5 to S9). In this additional step, first, in step S40, a predetermined combination part is set to 3Vli.
b, it is determined whether or not the logical designer designates the mapping. If so, the HD is determined in step S41.
L is designated to map a predetermined combination part by 3Vlib. This specification is performed, for example, as shown in FIG. 23 with respect to a normal function description of an adder for adding eight input data a, b, c, d, e, f, g, and h as shown in FIG. Specifies that the last adder element is mapped by 3Vlib. “// low-powe” in Figure 23
r-synthesis-high-voltage "is the specified part.

Thereafter, a function description is input, and step S4
In step 2, it is determined whether or not the combination part is designated as described above. If there is no designation, all combination parts are mapped by 2Vlib. If there is designation, the designated combination part is designated by 3Vlib in step S43. Map.

Next, in step S44, it is determined whether or not there is a mixture of the 2V system combination unit and the 3V system combination unit with the output of the 2V system combination unit being input to the 3V system combination unit. Only when there is, in step S45, a level conversion circuit is inserted in the preceding stage of the 3V system combination part in the mixture. The level conversion circuit to be inserted is shown in FIG.
A level conversion circuit 35 shown in (a) and a level conversion circuit 35 'shown in FIG.

The first step (steps S5 to S9) and the second step
(Steps S10 to S12) and the third step (Steps S13 to S15) are the same as those in the flowchart of FIG. 13 of the first embodiment. Description is omitted. However, the second
In step S10, if there is no mixture at step S10, it is determined at step S50 whether or not there is a level conversion circuit between the 3V system combination unit and another 3V system combination unit. In some cases, it is added to delete the level conversion circuit in step S51. This is because when the 2V-system combination part is replaced by the 3V-system combination part by the re-synthesis processing of the second step, the 3V-system combination part is replaced with another 3V-system combination part. Is assumed to include a level conversion circuit.

Therefore, in the present embodiment, FIG. 13 (first embodiment) using the normal function description (without designation of a predetermined combination part mapped by 3Vlib) of FIG.
The design method of the semiconductor integrated circuit according to the embodiment) is shown in FIG.
In the adder having seven adder elements (arithmetic elements) shown in (a), the four adder elements located at the preceding stage are combined by 3Vlib as shown by hatching in FIG. The eight registers located at the preceding stage
In this embodiment, the mapping is performed by a V / 3V flip-flop circuit. In the present embodiment, as shown by hatching in FIG. 2B, only the last addition element is synthesized by 3Vlib. , A level conversion circuit is arranged in the preceding stage, and the present embodiment is
The number of combination parts synthesized by ib is small, and low power consumption can be achieved.

(Fifth Embodiment) FIGS. 26 to 28 show a fifth embodiment of the present invention. In the present embodiment, the portion to be combined with the second combinational circuit using the 3V high voltage source 15 as the voltage source is not limited to the front portion, and the area of the combinational circuit whose signal propagation delay time exceeds the upper limit value is not limited to the front portion. Alternatively, it is appropriately selected from the viewpoint of the processing speed.

FIG. 26 shows the first half of the flowchart of FIG. 21 showing the third embodiment.
7 shows the latter half of the flowchart. Step S35 of the flowchart is replaced with steps S60 to S6 in FIG.
9 and steps S70 and S71 in FIG. 27 between steps S10 and S13 of the flowchart.
Has been added.

More specifically, in FIG. 26, in step S34, the high voltage (3V) li in one combinational circuit is determined based on the estimation result of the signal propagation delay time and the upper limit value of the designed delay.
After calculating the ratio P between b and the low voltage (2V) lib,
In step S60, the total number of gate stages of the combinational circuit is multiplied by the ratio P, and the high voltage (3
V) The number of gate stages mapped by lib (high voltage (3
V) Lib mapping range) is calculated. Subsequently, in step S61, a mapping range (predetermined size) of the high voltage (3V) lib is set as a search range (window).
After calculating the number n of windows in one combinational circuit, each of the plurality of windows n is evaluated in step S62 and thereafter. That is, first, the variable k is set to an initial value (= 0) in step S62, and then k = k + 1 in step S63.
Is set in step S64, and the combination part in the first window is set in step S64, and the area and delay of the combination part in this window are evaluated in step S65. After that, in step S66, the variable k is compared with the number n of the windows. If k <n, the process returns to the step 63 to sequentially calculate the total area and delay of the combination parts in the second to n-th windows. evaluate. Then, in step S67, a window having the smallest total area or the smallest delay of the combination part existing in the windows among the plurality of windows is selected. In step 68, if the selected window is not the first window In step S69, a level conversion circuit is inserted before the selected window.

In FIG. 27, 2 V is applied in step S10.
If the combination of the combination part of the system and the combination part of the 3V system is eliminated, the combination part of the 3V system and the other three
It is determined whether or not there is a level conversion circuit between the V-system combination unit and, if so, the 3V-system combination unit and another 3V-system combination unit are recombined in the second step. Since it is a situation that a level conversion circuit is to be included between the combination unit and the combination unit, it is added to delete the level conversion circuit in step S71.

Therefore, the present embodiment has the following advantages. That is, in the combinational circuit shown in FIG. 28 (that is, the adder having the seven adding elements shown in FIG. 25),
In the first, second, and third windows shown by hatching in FIGS. 7A, 7B, and 7C, respectively, FIG.
Is the total area (number) of adders
Is minimized, so this range is mapped with a high voltage (3V) lib. Therefore, the number of adder elements mapped by the high voltage (3V) lib can be minimized, and power consumption can be further reduced.

( Application Example ) FIGS. 33 and 34 show application examples of the present invention. In the fourth embodiment, the combination unit located at the last stage of the adder is synthesized by 3Vlib, and the combination unit located at the last stage of the carry-save parallel multiplier is changed to 3Vlib.
lib.

FIG. 33 shows a function description including a designation to combine the combination section located at the last stage of the carry-save parallel multiplier by 3Vlib. This function description is input to the reading section 61 of the logic synthesis apparatus 60. Is done.

FIG. 34 shows a carry-save parallel multiplier which is logically synthesized based on the function description input to the reading section 61. In the parallel multiplier shown in the figure, a plurality of AND circuits 90, a plurality of half adders HA and a full adder FA are arranged in an array, and a multi-bit adder 91 is provided at the last stage.
Are arranged, and the lowermost full adder 91 is 3V
lib and the others are synthesized by 2Vlib. In addition, 16 level conversion circuits 92 are arranged in a stage preceding the lowermost full adder 91. Each of the level conversion circuits 92 converts the level (2 V) of the signal input from the previous-stage adder to a high level (3 V) and outputs it.

Therefore, in this application example , since the carry-save parallel multiplier is used, the adder array occupying most of the circuit may be an ordinary adder, but the lowermost adder 91 needs to be high-speed. There is. In this case, in order to increase the speed, the adder 91 of the lowermost stage normally uses an adder of a carry look ahead, but the adder 91 of the lowermost stage is used.
Is a high voltage (3V) system, so that a circuit excellent in circuit scale and power consumption can be generated, and
It is possible to generate a multiplier that is faster than before.

In this application example , the parallel multiplier of the carry-save system has been described. Of course, the same can be applied to a vessel.

In the above description, the present invention has been applied to the functional block A constituting the memory cell unit E other than the memory cell unit E formed in the internal core unit 22 of the chip 20, but to the other functional blocks BD. It goes without saying that a plurality of functional blocks A to
Needless to say, the present invention can be similarly applied between D.

As described above, the semiconductor integrated circuit of the present invention
According to the design method of the circuit, only a part of the combination portion of the plurality of combination parts constituting the combination circuit having a critical path with the high voltage system of 3V, a combination circuit low
The output of the combination part of the voltage system (2V) is before the other combination circuits
There is a form that is input to the combination part of the high voltage system of 3V.
In this case, the combination part of the low-voltage system is
Since it is regenerated in the combination part, it is compared with the case where only the combinational circuit having a critical path is targeted for the 3V high voltage system.
In addition , the number of required level conversion circuits can be reduced, and the design of a semiconductor integrated circuit becomes extremely easy. Moreover, the number of combinational circuits having a critical path is extremely small compared to the number of combinational circuits provided in the semiconductor integrated circuit, and some of the combinational parts constituting such a critical path combinational circuit are combined. Since only the section is driven by the high voltage source 15 of 3V, the increase in current consumption can be suppressed to a very small level. On the other hand, all the combinational circuits having no critical path are driven by the low voltage source 16 of 2V. Current consumption can be reduced as a whole circuit, and power consumption can be reduced.

The semiconductor integrated circuit according to the present embodiment shown in FIG.
A comparison is made with the conventional semiconductor integrated circuit of FIG. In the conventional semiconductor integrated circuit of FIG.
Assuming that the signal propagation delay times of 102, 104 and 106 are 6 ns, 12 ns, 14.4 ns and 8 ns as shown in the figure, and the delay time from the clock input to the data output of the flip-flop circuit is 2 ns, the combinational circuit 30 is 14.4 ns of the combinational circuit 104, the maximum operating frequency of the circuit of FIG. 30 is 1000 / (2 + 14.4) =
It becomes 60.98 MH.

On the other hand, in the semiconductor integrated circuit of the present embodiment shown in FIG.
Has a high voltage (3V) system at the front and a low voltage (2V) system at the rear, and its delay time is the designed upper limit of delay (for example, 20 ns). The delay time of the combinational circuits 1, 3 and 7 without a critical path reduced the power supply voltage from a high voltage of 3V to a low voltage of 2V,
It increases as the delay of the logic cell increases. still,
In the semiconductor integrated circuit shown in FIG.
It is assumed that the cell delay time is increased by a factor of 1.5 with the low voltage source of FIG. The maximum of the delay times of the combinational circuits 1, 3 and 7 having no critical path is 18 ns of the combinational circuit 3.

A low voltage source 16 of 2V and a high voltage source 15 of 3V
As a result, the delay of the combinational circuit 5 having a critical path becomes 18 ns (the high voltage source 15 of 3 V).
It is assumed that the delay is 1.25 times that of the case of driving with (1). Since the signal propagation delay time from the clock input to the data output of the flip-flop circuit is 2 ns, and the delay times of the combinational circuits 3 and 5 are 18 ns, the maximum operating frequency of the semiconductor integrated circuit of the present embodiment is , 1000 / (2 + 18) = 50 MHz, but there is no problem if the maximum delay time is equal to or less than the design delay upper limit value. That is, the combination circuits 1, 3 and 7 having no critical path are driven by the low voltage source 16 of 2V, and the combination circuit 5 having the critical path is driven by the high voltage source 15 of 3V and the low voltage source 16 of 2V. However, the maximum operating frequency in design can be satisfied.

FIG. 35 shows that the design delay upper limit is set to 20 ns.
In the conventional semiconductor integrated circuit and the semiconductor integrated circuit of the present invention, the signal from the clock input of the flip-flop circuit to the data input of the next-stage flip-flop circuit, that is, the signal obtained by adding the delay time of the register and the combinational circuit 5 shows a distribution of propagation delay time. FIG. 1A shows the delay distribution of a conventional 3 V voltage semiconductor integrated circuit, and FIG. 2B shows the delay distribution of a 2 V and 3 V mixed semiconductor integrated circuit of the present embodiment. In a conventional semiconductor integrated circuit, when only the power supply voltage is changed from a high-voltage system of 3 V to a low-voltage system of 2 V, the maximum delay time is changed from 20 ns to 30 ns, and the delay time of the critical path is reduced to the design upper limit value 20 ns. In contrast, in the semiconductor integrated circuit according to the present embodiment shown in FIG. 3, a part of each of the combinational circuits having a critical path whose delay time exceeds 20 ns when the combinational circuits are combined in a low-voltage system of 2 V is used. Is changed to the high voltage system of 3V, and the remaining combination parts and other combination circuits having no critical path are set to the low power supply system of 2V, so that the upper limit of the design delay of 20 ns can be satisfied. it can. FIG. 3B shows the delay distribution at this time.

Next, the circuit scale of the conventional semiconductor integrated circuit and the semiconductor integrated circuit of the present invention will be compared.

The circuit size of the conventional semiconductor integrated circuit is S, the proportion of the flip-flop circuit in the semiconductor integrated circuit is 20%, and the proportion of the flip-flop circuit having the level conversion circuit in the whole flip-flop circuit is 10%.
%, And if the 2V / 3V flip-flop circuit of the present invention has an area increase of 10% due to a difference in circuit configuration from the conventional flip-flop circuit, the circuit scale of the semiconductor integrated circuit of the present invention is expressed by the following equation. Then, S × 0.8 + S × 0.18 + S × 1.1 × 0.02 = S × 1.002, and the increase in the circuit scale is limited to 0.2%.

Further, assuming that the ratio occupied by the flip-flop circuit having the level conversion circuit in the whole flip-flop circuit is 5% under the above conditions, the circuit scale of the semiconductor integrated circuit of the present invention is expressed by the following equation. S × 0.8 + S × 0.19 + S × 1.1 × 0.01 = S × 1.001, and the increase in circuit scale remains at 0.1%.

( Other Applications ) FIGS. 36 to 39 show other applications of the present invention. In each of the above embodiments, when a combination circuit of a high (3 V) voltage system is used, the register located at the preceding stage has a level conversion circuit. The reason for providing this level conversion circuit is
For example, a flip-flop circuit (register) 2 shown in FIG.
Inverters 34c and 34 constituting the output buffer 32 of FIG.
This is to prevent a through current from flowing through d. The reason why this through current flows will be described in detail below. FIG. 42 shows the internal configuration of the inverter. In the figure, the high voltage (3
V) P-channel and N-channel transistors Tp and Tn are arranged in series between the power supply Vo and the ground power supply VSS. A signal is input to the gates of the two transistors, and a connection point is an output terminal of the inverter. The "H" level of the input signal is the low voltage of the low voltage source 16, that is, 2V. When the input signal is at "H" level, the N-channel transistor Tn is turned on, but the P-channel transistor Tp is not completely turned off.
5 through the low-voltage source 16.

However, the high voltage source 15 and the low voltage source 16
Is smaller than or equal to the threshold voltage Vt of the P-channel transistor Tp, the P-channel transistor Tp is reliably turned off, and no through current flows. Therefore, the potential difference is set to be equal to or lower than the threshold voltage Vt of the P-channel transistor Tp. For example, when the threshold voltage Vt = 0.5 V, the high voltage of the high voltage Setting the low voltage to 2.7 V eliminates the need for providing a level conversion circuit. This application example shows an example in this case.

In the functional block shown in FIG. 36, the three combination circuits 1, 3, and 7 are composed of a 2.7V-system combination circuit (first combination circuit) using a 2.7V low voltage source as a voltage source. The other combinational circuit 5 is composed of a 3V combinational circuit (second combinational circuit) using a 3V high voltage source as a voltage source. The flip-flop circuits 2, 4, 6, 8 are 2.7
It is composed of a 2.7 V system using a low voltage source of V as a voltage source. The 2.7-V flip-flop circuit is specifically the same as the configuration shown in FIG. 4 except for the power supply voltage.

FIG. 37 shows an example of a logic synthesizing method constituting the functional blocks of FIG. In FIG.
The signal propagation delay time of each combinational circuit when each combinational circuit is mapped by the low voltage (2.7 V) lib is estimated in step S1, and it is determined in step S2 whether the estimation result exceeds the designed delay upper limit value. However, in the case of a combination circuit having a delay equal to or less than the delay upper limit value, the combination circuit is set to 2.7 V in step S3.
Into a first combinational circuit using the low voltage source of
If the combinational circuit exceeds the delay upper limit value, the combinational circuit is combined with a second combinational circuit using a high voltage source of 3 V in step S4. Thereafter, in step S5, the flip-flop circuit is mapped to the 2.7 Vlib flip-flop circuit.

FIG. 38 shows an example of another logic synthesis method. 36 is different from FIG. 36 in that all the combinational circuits and flip-flop circuits are initially set to 2.7 V in step S1 '.
After the mapping to the combination circuit and the flip-flop circuit of lib, the combination circuit that is determined in step S2 ′ to have the signal propagation delay time exceeding the designed delay upper limit value is re-mapped to the combination circuit of 3 Vlib in step S4 ′. Is a point. Therefore, other configurations are omitted.

Therefore, in this application example , as shown in FIG. 39, one combinational circuit 70 located between two registers
When the signal propagation delay time exceeds the upper limit in design, the entire combination circuit 70 is mapped at 3 Vlib as shown by hatching in FIG. As shown by, mapping is performed by a flip-flop circuit having a 2.7 V system and having no level conversion circuit. In this case, the above 3
The combinational circuit 70 mapped in vlib, 2.
7 Combination parts 71a and 71b mapped by Vlib
, A low-voltage (2.7 V) signal is input. However, the combination circuit 70 mapped with 3 Vlib operates normally even when receiving the low-voltage signal. 71a and 71b are not remapped to 3Vlib.

FIG. 40 shows a modification of this application example . Other
In the application example of the above, in a combinational circuit in which the signal propagation delay time exceeds the designed delay upper limit, the entire combinational circuit is
lib, but only part of it was mapped to 3Vlib
, And the rest is mapped to 2.7 Vlib. The method of mapping which part to 3Vlib is the same as the method shown in FIGS. 26 and 27 using the window of the fifth embodiment. In FIG. 40 of this modification, since a level conversion circuit is unnecessary, the level conversion circuit is inserted (steps S68 and S69 in FIG. 26) compared to FIGS. 26 and 27 showing the fifth embodiment. , And the accompanying deletion of the level conversion circuit (steps S70 and S71) are omitted.

FIG. 41 shows the effect of this application example . As can be seen from the figure, when the design delay upper limit is set to 20 ns, the 3V voltage system is reduced by 2 with respect to the delay distribution of the 3V voltage semiconductor integrated circuit as shown in FIG. When the voltage is changed to a low voltage system of 0.7 V, the maximum delay time is increased from 20 ns to 24 ns as shown by a broken line in FIG. This application shows
In the example of the delay distribution of the 2.7 V system and 3 V system mixed semiconductor integrated circuit, the upper limit of the designed delay of 20 ns can be satisfied.

[0127]

As described in the foregoing, according to the method of designing a semiconductor integrated circuit of the invention of claim 1 to claim 21, wherein, in each combination circuit with a critical path,
Only a portion of the signal propagation path is driven at a high voltage source, to drive the remainder at a low voltage source, the low-voltage combination circuit
The output of the remainder driven by the source is the high voltage of another combinational circuit.
If there is a form input to the part driven by the source,
The remainder driven by the low voltage source is driven by a high voltage source.
Since design, placing the level conversion circuit only register located upstream of a combinational circuit that has a critical path
Therefore, while suppressing the signal propagation delay time of the critical path to less than the upper limit of the delay allowed by the design, the required level conversion circuit is required as compared with the case where only the critical path is driven by the high voltage source. The number can be reduced, and the top-down design from the function description can be easily performed. Therefore, the design of a semiconductor integrated circuit with low power consumption can be performed very easily.

In particular, the semiconductor integrated circuit according to the fifth aspect of the present invention.
According to the road design method , a high
It finds the boundary of the remainder to be driven in part and the low-voltage source to be driven by a voltage source accurately set to a voltage source a high voltage source
Since the number of matching portions can be limited to a minimum, power consumption can be further reduced.

In addition, a semiconductor integrated circuit according to claim 6 is provided.
According to meter method, since searching for the boundary between the part and the remainder of the one combined circuit simply by binary search, logic synthesis
It is possible to increase the speed of the design method such as .

Further, a semiconductor integrated circuit according to claim 8 is provided.
According to meter method, the boundary between the part and the remainder of the one combination circuit, since the search more easily based on the ratio between the maximum delay value on design and estimation results of the signal propagation delay time, logic synthesis, etc. The speed of the design method can be further increased.

In addition, the half of claim 9 and claim 10
According to the design method of the conductor integrated circuit, a specific combination to be driven by the high voltage source is specified, so that the required high voltage source is required.
Thus, the number of combination units to be driven and the number of required level conversion circuits can be reduced.

Further, a half of the invention described in claims 13 , 22 and 23.
According to the design method of the conductor integrated circuits, one part to be driven by a high voltage source in a combinational circuit to search with window, the minimum total area of the combined section (number) is or delay the smallest window Inside as a part to be driven by a high voltage source.
Since formation, Ru <br/> Ah can improve the power consumption or the processing speed.

[Brief description of the drawings]

FIG. 1 is an overall schematic configuration diagram of an image processing system.

FIG. 2 is an overall schematic configuration diagram of a semiconductor chip.

FIG. 3 is a diagram illustrating a connection relationship between a plurality of registers and a plurality of combinational circuits of the semiconductor integrated circuit according to the embodiment of the present invention;

FIG. 4 is a configuration diagram of a flip-flop circuit having no level conversion circuit.

FIG. 5 is a configuration diagram of a flip-flop circuit having a level conversion circuit.

FIG. 6 is a diagram showing a specific configuration of a level conversion circuit.

FIG. 7 is a configuration diagram of a latch circuit having no level conversion circuit.

FIG. 8 is a configuration diagram of a latch circuit having a level conversion circuit.

FIG. 9 is a diagram showing an overall schematic configuration of a logic synthesis device.

FIG. 10 is a diagram illustrating a hardware description language.

FIG. 11 is a diagram showing a net list.

FIG. 12 is a diagram showing a schematic.

FIG. 13 is a diagram illustrating a method of designing a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 14 is a diagram showing a table of a cell library.

FIG. 15 is a diagram showing a part of a semiconductor integrated circuit.

FIG. 16 is a diagram showing a circuit in which a part of a semiconductor integrated circuit is changed.

FIG. 17 is a diagram showing a description of a register transfer level.

FIG. 18 is a diagram showing a description of a register transfer level corrected when logical synthesis cannot be performed.

FIG. 19 is a diagram illustrating the order of the logic synthesis method according to the first embodiment of the present invention.

FIG. 20 is a diagram illustrating a logic synthesis method according to the second embodiment of the present invention.

FIG. 21 is a diagram illustrating a logic synthesis method according to a third embodiment of the present invention.

FIG. 22 is a diagram illustrating a logic synthesis method according to a fourth embodiment of the present invention.

FIG. 23 is a diagram showing a function description which is an input of the method of designing a semiconductor integrated circuit according to the present invention.

FIG. 24 is a diagram showing a function description which is an input of a conventional logic synthesis method.

FIG. 25 is a diagram showing an adder generated by the present invention and a conventional method for designing a semiconductor integrated circuit .

FIG. 26 shows a semiconductor device according to the fifth embodiment of the present invention.
It is a figure showing the front part of the design method of an integrated circuit .

FIG. 27 shows a semiconductor device according to the fifth embodiment of the present invention.
FIG. 10 is a diagram illustrating the rear part of the design method of the integrated circuit .

FIG. 28 is a semiconductor integrated circuit according to a fifth embodiment of the present invention.
FIG. 6 is a diagram showing an adder generated by the design method of FIG.

FIG. 29 is a diagram showing a description of a register transfer level.

FIG. 30 is a diagram showing a logic circuit of a conventional semiconductor integrated circuit.

FIG. 31 is a diagram showing an arrangement position of a level conversion circuit when only a critical path is driven by a high voltage source in an arbitrary semiconductor integrated circuit.

FIG. 32 is a diagram showing an arrangement position of a level conversion circuit when only a critical path is driven by a high voltage source in another arbitrary semiconductor integrated circuit.

FIG. 33 is a diagram illustrating another example of a function description that is an input of a logic synthesis method according to an application example of the present invention.

FIG. 34 is a circuit diagram showing a carry-save parallel multiplier generated by a logic synthesis method according to an application example of the present invention.

FIG. 35 is a diagram showing a signal propagation delay time of a semiconductor integrated circuit and a distribution of the number of combinational circuits having the delay time in the conventional example and the present invention example.

FIG. 36 is a diagram showing a configuration of a semiconductor integrated circuit generated by a logic synthesis method according to another application example of the present invention.

FIG. 37 is a view illustrating a flowchart of a logic synthesis method according to another application example of the present invention.

FIG. 38 is a view illustrating a flowchart of another logic synthesis method according to another application example of the present invention.

FIG. 39 is a diagram showing an execution result of a logic synthesis method according to another application example of the present invention.

FIG. 40 is a view showing still another flowchart of a logic synthesis method according to another application example of the present invention.

FIG. 41 is a diagram showing a signal propagation delay time of a semiconductor integrated circuit and a distribution of the number of combinational circuits having the delay time in a conventional example and another application example of the present invention.

FIG. 42 is a diagram showing a configuration of an inverter provided in a register.

[Explanation of symbols]

1, 3, 7 First combination circuit 5 Second combination circuit 2, 4, 6, 8 Flip-flop circuit (register) 9 Clock buffer (clock supply means) 15 High voltage source 16 Low voltage source 22 Internal core unit 30 Master latch 31 Slave latch 33, 33 54, 92 Internal clock generation circuit 35, 35 56, 96, 98 Level conversion circuit 36 Data temporary storage unit 40, 41 PMOS transistor 42, 43 NMOS transistor 45, 46 CMOS inverter 47, 49 PMOS transistor 48, 50 NMOS transistor 51, 51 'Latch circuit (register) 52 Latch section 65 Timing verification section 70, 71 Combination circuit 70a, 70b 71a Combination section 90 Logical product circuit 91 Adder located at the rear end HA Half adder FA Full adder 92 level conversion circuit

Continuation of front page (56) References JP-A-6-348459 (JP, A) JP-A-5-289851 (JP, A) JP-A-2-187706 (JP, A) JP-A-4-223616 (JP) JP-A-3-220668 (JP, A) JP-A-4-354020 (JP, A) 1995 International Symposium on Low Power Design, April (1995) p. p. 3-8 (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/82 G06F 17/50 JICST file (JOIS)

Claims (23)

(57) [Claims] 1. A combination circuit having one signal propagation path
A plurality of the at least one combinational circuit
Semiconductor device including a register arranged at the front and rear stages
A method of designing an integrated circuit, wherein when the signal propagation delay time of the signal propagation path of any one of the combinational circuits is equal to or less than a design delay upper limit value, the combination circuit uses a low voltage source as a voltage source. Generated in one combinational circuit
On the other hand, when the signal propagation delay time of the signal propagation path of any one of the combinational circuits exceeds the designed delay upper limit , the signal propagation delay time of the signal propagation path of this combinational circuit is as less than the maximum delay value of the design, a low voltage source and the remainder of the combination circuit with a voltage source a high voltage source part of the combined circuit to the second combinational circuit to a voltage source
A first step of generating, and a step of using a low voltage source as a voltage source in the second combinational circuit.
Another second combination wherein the output of the unit is the high voltage source as a voltage source
Judge whether or not the input shapes are mixed in a part of the
When there is a mixture of
The remainder with the voltage source as the voltage source, the high voltage source as the voltage source
Method for designing a semiconductor integrated circuit, characterized in that it comprises a second step of regenerating a portion of the second combination circuit. 2. A first step, said portion of said second combining circuit is a front portion of the combinational circuit, the remainder of the second combinational circuit is a rear portion of the combinational circuit The half according to claim 1, characterized in that:
Design method of conductor integrated circuit . 3. The method according to claim 1, wherein each of said registers is generated or regenerated.
Register for outputting a signal to the part of the selected second combinational circuit.
And whether any of the registers is the second set
A register that outputs a signal to the part of the matching circuit.
In this case, connect this register to a voltage source, including the high voltage source.
Generated in a register as a pressure source,
If the register is not a register that outputs a signal to a part,
Registers to the registers that use the low voltage source as the voltage source.
3. The method according to claim 1, further comprising a third step.
The method for designing a semiconductor integrated circuit according to claim 2. 4. The first step is to first convert all the combinational circuits using the first combinational circuit.
Generated, then if the signal propagation delay time of the first combining circuit and said generating it is determined whether it exceeds the maximum delay value of the design, the first combinational circuit exceeding the maximum delay value in design there the method for designing a semiconductor integrated circuit according to claim 2, wherein the regenerating the front of all of the first combining circuit to the part of the second combinational circuit. 5. In the first step, when there is a first combinational circuit in which a signal propagation delay time exceeds a design delay upper limit value, the first combinational circuit is conceptually divided into a plurality of combination units. First, the first combination is driven by a high voltage source.
That regenerates the combination unit, then the signal propagation delay time of the combination circuit after regeneration it is determined whether or not exceeding the maximum delay value of the design, then the signal propagation delay of the combination circuit after regeneration If the time still exceeds the design delay upper limit, the next combination unit in the signal propagation direction in the first combination circuit is switched to the combination unit driven by the high voltage source . Re
The method of designing a semiconductor integrated circuit according to claim 2 , wherein the generation and the determination of the signal propagation delay time after the generation are repeated. 6. The remainder of the first step, wherein the low voltage source of the second combinational circuit is a voltage source.
Is a second combinational circuit using the high voltage source as a voltage source.
When regenerating the second combinational circuit , the remaining part of the second combinational circuit is conceptually partitioned into a plurality of combinational parts, and the set regenerated in the part of the second combinational circuit among the plurality of combinational parts The combining unit uses the binary search method to calculate the signal propagation delay time of the second combinational circuit.
5. The semiconductor integrated circuit according to claim 4 , wherein the search is repeated until the delay becomes equal to or less than a design delay upper limit value .
Design method . 7. A first step comprising: combining a register driven by the low-voltage source and the first combination circuit using a register driven by the first combinational circuit and a low-voltage source. Then, it is determined whether or not the estimation result exceeds a design delay upper limit value. If there is a first combinational circuit that is equal to or less than the design delay upper limit value, A first combinational circuit is generated in the first combinational circuit, and if there is a first combinational circuit whose estimation result exceeds the design delay upper limit value, the first combinational circuit is partially set to high. Use voltage source as voltage source
And a second combinational circuit using a low voltage source as a voltage source
According to claim 2, characterized in that the step of generating the
A method for designing a semiconductor integrated circuit . 8. In the first step, when there is a first combinational circuit whose signal propagation delay time estimation result exceeds a design delay upper limit, the first combinational circuit is assigned to a plurality of combination units. The number of the combination units to be conceptually partitioned and to be generated as a part of the second combination circuit based on the ratio between the estimation result of the signal propagation delay time and the upper limit value of the design delay, and the second And the rest of the combinational circuit
Then, the ratio of the number of combination parts to be generated is calculated, and then, based on the number of combination parts constituting the first combination circuit and the calculated ratio, the second combination circuit is calculated .
Calculating a generation all-out range in part, then, a combination portion in a range in which the calculated high voltage source
The generated part of the second combinational circuit to a voltage source, wherein
The combination part outside the range is set to the second
8. The method as claimed in claim 7, wherein the signal is generated in the remainder of the combinational circuit.
The method for designing a semiconductor integrated circuit according to the above. Before 9. first step, it specifies the components sac Chi part of the combinational circuit, to generate a portion that is the specified portion to a voltage source the high voltage source < 4. The semiconductor integrated circuit according to claim 1, further comprising a step of arranging a level conversion circuit using a high voltage source as a voltage source at a stage preceding the generated part.
Design method . 10. The method for designing a semiconductor integrated circuit according to claim 9 , wherein a part of the specified combinational circuit is a rear part of the combinational circuit. 11. The designation is made in the constituent parts of the combinational circuit.
Performed by specifying that contains a description functional description part of the high voltage source and voltage source, according to claim 9 or claim 10, wherein the inputting the functional description before the first step Installation of semiconductor integrated circuit
Metering method . 12. After the second step , a part using the high voltage source as a voltage source and another high voltage source as a voltage source
To determine whether the level conversion circuit exists between a portion, in the case where the level conversion circuit is present, according to claim 9 or claim 10, characterized by comprising the step of deleting the level conversion circuit The method for designing a semiconductor integrated circuit according to the above. 13. In a first step, a plurality of windows of a predetermined size as a search range are set in a combinational circuit in which a signal propagation delay time exceeds a design delay upper limit value. Among them, a window in which the total area of the combination units in each window is the smallest or the delay is the smallest is selected, and the combination unit in the selected window is used as the voltage source of the second combination circuit of the high voltage source. Previous
In some cases, the signal propagation delay time is a design delay.
<br/> to generate a combined circuit exceeding the upper limit value in the second combinational circuit Rutotomoni, in front of the part of the second combinational circuit described above generates, the level conversion circuit to a voltage source a high voltage source 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged. 14. The semiconductor device according to claim 13 , wherein the predetermined size of the window is calculated based on the signal propagation delay time and the designed upper delay limit.
How to design integrated circuits . 15. After the second step, a part of the second combinational circuit using the high voltage source as a voltage source and a part of the other second combinational circuit using the high voltage source as a voltage source 14. The semiconductor integrated circuit according to claim 13, further comprising a step of determining whether or not there is a level conversion circuit in between, and when there is a level conversion circuit, deleting the level conversion circuit.
Circuit design method . 16. The second step includes: rest of the second combinational circuit using the low voltage source as a voltage source.
Is a second combinational circuit using the high voltage source as a voltage source.
Whether the output of the remaining portion of any of the second combinational circuits is newly mixed with the input of the part of the regenerated second combinational circuit as a result of the regeneration of the second combinational circuit. And if the mixture occurs, the second combinational circuit
2. The method according to claim 1 , further comprising the step of: regenerating the remaining part of the second combinational circuit into the part of the second combinational circuit .
A method for designing a semiconductor integrated circuit according to claim 2 or 3.
Law . 17. Enter a plurality of registers and the design data of register transfer level that describes a plurality of combinational circuits located between the respective registers, the connection information of the entering force the register transfer level logic cells from design data of generated, the first combinational circuit based on the connection information of the logic cell
2. The method for designing a semiconductor integrated circuit according to claim 1, further comprising generating a second combinational circuit . 18. Enter the net list describing the connection information of logic cells, entering-force above based on the connection information of logic cells described in the netlist first combining circuit and the second combined times
2. The semiconductor device according to claim 1, wherein a path is generated.
How to design integrated circuits . 19. Enter the schematic representation of the connection information of logic cells, the entering force to said based on the connection information of logic cells represented in the schematic first combining circuit and the second combined times
2. The semiconductor device according to claim 1, wherein a path is generated.
How to design integrated circuits . 20. Optimizing connection information of a logic cell based on an input register transfer level, an input netlist, or an input schematic, and the first information based on the optimized connection information of the logic cell .
Generating a combining circuit and a second combining circuit according to claim 17, wherein, according to claim 18 or claim 19, wherein the
A method for designing a semiconductor integrated circuit . After 21. third step, the method for designing a semiconductor integrated circuit according to claim 3, characterized in that it comprises a step of verifying the timing of each register. 22. A combination circuit having one signal propagation path
And at least one combinational circuit
Having a register disposed at a stage preceding and succeeding a stage
A method of designing an integrated circuit, wherein when a signal propagation delay time of a signal propagation path of any one of the combinational circuits is equal to or less than a design delay upper limit value, the combination circuit uses a low voltage source as a voltage source. Generated in one combinational circuit
A step of, when a signal propagation delay time of the signal propagation path of said any combination circuit exceeds the maximum delay value of the design, this union
Signal propagation delay time is less than the design delay upper limit
It becomes as part of the combination circuit with a high voltage source and the voltage source, and a step of generating the remainder of the combination circuit in the second combinational circuit to a voltage source of low voltage source, the second In the process of generating a combinational circuit, the combination in which the signal propagation delay time exceeds the design delay upper limit
A window of a certain size as a search range in the circuit
Are set, and among the plurality of windows,
C) the total area of a combination is the smallest or the delay is the smallest
Select a window and select the combination in this selected window
The high voltage source of the second combinational circuit as a voltage source
Design of semiconductor integrated circuit characterized by partial generation
How . 23. The semiconductor device according to claim 22 , wherein the predetermined size of the window is calculated based on the signal propagation delay time and the designed upper limit of delay.
How to design integrated circuits .