JPH11274413A - Arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic circuit which processes at a high speed and does not consume much electric power. SOLUTION: In an arithmetic circuit, a plurality of AND circuits 90, a plurality of half-adders HA, and a plurality of full-adders FA are arranged in an array-like state and a multi-bit adder 91 is arranged in the last stage. The adder 91 in the last stage is driven by means of a high-voltage source of 3 V and the other adders are driven by means of low-voltage sources of 2 V. In the preceding stage of the last-stage adder 91, level converting circuits 92 are arranged. The circuits 92 respectively convert the low-voltage levels of the signals inputted from the adders in the preceding stage into high-voltage levels. Since the last-stage adder 91 is operated with the high voltage, the operating speed of the arithmetic circuit can be increased. Since the other adders are operated with the low voltages, in addition, the power consumption of the circuit can be reduced. Moreover, since the level converting circuits 92 are arranged in the preceding stage of the last-stage adder 91, the number of the circuits 92 and, accordingly, the circuit scale of the arithmetic circuit can be reduced as compared with the case where the level converting circuits are arranged closer to the input side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit, and more particularly to an improvement for providing a high-speed operation circuit with low power consumption and a small circuit scale.

[0002]

2. Description of the Related Art Today, in the design of a semiconductor integrated circuit, a semiconductor integrated circuit to be developed is represented by a function description at a register transfer level (hereinafter, referred to as RTL), and the logic is synthesized using the RTL description. ,
A top-down design for generating a semiconductor integrated circuit to be developed is employed.

FIG. 29 shows a conventional RTL description, and FIG. 30 shows a logic circuit (semiconductor integrated circuit) generated by logic synthesis using the RTL description.

[0004] The RTL description in FIG. 29 is a description that clearly defines data transfer between a plurality of registers at a functional level. In the RTL description shown in the figure, r1, r2, r3, and r4 are registers, func1, func2, func3, and func4 are descriptions of the function of a combinational circuit between the registers. It describes the connection relationship.

In the case of synthesizing logic from the RTL description of FIG. 29, a circuit is determined on a curve of a trade-off between area and speed by giving constraints on area or speed.

In the logic circuit shown in FIG. 30 generated from the RTL description, 101, 103, 105 and 107 are flip-flops in which registers r1, r2, r3 and r4 specified in the RTL description are mapped by logic synthesis. And a register r1, r2 specified in the RTL description of FIG.
Corresponds directly to 2, r3, r4. 108 is the clock buffer, 10
0, 102, 104 and 106 are func1 and Runc of the RTL description in FIG.
This is a combinational circuit corresponding to func2, func3, and func4. The combinational circuits 100, 102, 104 and 106 correspond to the RT of FIG.
It is mapped from the function description of L as one circuit on the curve of trade-off between area and speed.

[0007]

By the way, the power consumption P of the semiconductor integrated circuit can be expressed as follows: operating frequency f, load capacitance C,
As the voltage and V [Equation 1], represented by [Equation 1] P = f x C x V 2. Therefore, there are three methods for reducing the power consumption of the semiconductor integrated circuit: lowering the operating frequency, lowering the load capacity, or lowering the power supply voltage. The reduction effect due to the reduction in the power supply voltage is the largest.

However, when the power supply voltage is set low, the delay time of the critical path having the maximum delay time among many paths constituting the logic circuit also increases.

In view of the above, for example, a technique disclosed in Japanese Patent Laid-Open Publication No. Hei 5-299624, that is, a logic gate which operates at a low speed among a large number of logic gates is driven by a low voltage source,
Utilizing technology for driving other logic gates requiring high-speed operation by a high voltage source, only the logic gates constituting the critical path are driven by a high voltage source, and the other logic gates are driven by a low voltage source. Thus, it is conceivable to reduce the current consumption of the entire semiconductor integrated circuit by using a low-voltage power supply without increasing the maximum delay time of the critical path, thereby achieving low power consumption. However, this idea has the following disadvantages.

The details of the above disadvantages are as follows. As described above, when data is transmitted from a low-speed logic gate driven by a low voltage source to a high-speed logic gate driven by a high voltage source, for example, Japanese Patent Laid-Open No. 5-67963
As disclosed in Japanese Patent Application Laid-Open Publication No. H10-115, it is necessary to arrange a level conversion circuit between the two logic gates for converting the output level of the logic gate driven by the low voltage source to a high level. However, each of the combinational circuits shown in FIG.
Since the circuit is composed of a large number of logic gates as shown in FIG. 1 or FIG. 32, assuming that the critical path in the combinational circuit in each figure is a path indicated by a thick line in FIG. In order to drive with a plurality of positions (in FIG.
It is determined that a level conversion circuit is required at eight locations and at twelve locations in FIG. In a highly integrated semiconductor integrated circuit, the number of combination circuits is extremely large, and the number of logic gates constituting each combination circuit is also extremely large. Therefore, in such a highly integrated semiconductor integrated circuit, the number of positions requiring a level conversion circuit in one combinational circuit having a critical path is large, and the number of combinational circuits having a critical path is large. The number of positions requiring a level conversion circuit in the entire circuit is enormous. As a result, in the design of a highly integrated semiconductor integrated circuit, it is possible to determine and arrange the position where the level conversion circuit is required as described above using a combination circuit that is only partially limited. However, there are drawbacks in that the determination of the arrangement position of the level conversion circuit is complicated and troublesome, takes a long time, and makes the design difficult.

Therefore, in the method of designing a semiconductor integrated circuit, low power consumption semiconductor integrated circuits can be simply designed without increasing the delay time of the critical path of each combinational circuit of the semiconductor integrated circuit to be developed. It is desired to provide a method which can be performed and a semiconductor integrated circuit which does not increase the delay time of such a critical path and consumes low power.

[0012]

The present inventors have focused on the following points. First, as shown in FIG. 30, the semiconductor integrated circuit is composed of a large number of registers and a large number of combinational circuits located between the respective registers. Of the combinational circuit at various locations inside the circuit, that is, at a plurality of positions that require a level conversion circuit when the critical path is driven by a high power supply,
There is no need to dispose each level conversion circuit, and the number of positions of the level conversion circuits can be reduced. Second, if the level conversion circuits are arranged in the registers as described above, data is transmitted from this level conversion circuit. In a combinational circuit, even if the entire combinational circuit is driven by a high power supply,
In a semiconductor integrated circuit, the number of logic gates existing on the critical path is about 5% of the number of logic gates forming the entire integrated circuit. Therefore, even if the whole combinational circuit having a critical path is driven by a high power supply, the power consumption does not increase so much. Third, the maximum delay time of the critical path is limited to a design delay upper limit or less. If the entire combinational circuit with a critical path is not driven by a high power supply, but only a part of the combinational circuit is driven by a high power supply, the maximum delay time of the critical path is reduced and the design delay is reduced. We focused on the fact that the power consumption can be limited to the upper limit or less and the increase in power consumption can be suppressed to a small value.

In view of the above, the present inventor of the present invention has a method of designing a semiconductor integrated circuit in which a level conversion circuit is disposed only in a register in principle and only a part of a combinational circuit having a critical path is driven by a high power supply. I came to think about adopting a configuration.

Further, the inventor of the present application applied the above idea to an arithmetic circuit, and considered to configure an arithmetic circuit driven by using two power supplies of a high voltage source and a low voltage source. .

That is, an object of the present invention is to provide a high-speed operation circuit with low power consumption and a small circuit scale.

To achieve the above object, the present invention provides:
In the arithmetic circuit, a portion driven by a high voltage source is specified in consideration of the required number of level conversion circuits.

That is, the arithmetic circuit according to the first aspect of the present invention comprises:
With a predetermined number of arithmetic elements arranged in a row as one stage, a plurality of arithmetic elements in this row are arranged in a plurality of stages, an arithmetic element at the foremost stage receives a signal from the outside, and an arithmetic element at each stage except the foremost arithmetic element. Is an arithmetic circuit that receives an output from an arithmetic element located at a preceding stage, and an arithmetic element at the last stage externally outputs an arithmetic result, wherein the arithmetic element at the last stage uses a high voltage source as a voltage source, and The operation elements other than the elements use a low-voltage source as a voltage source, and the high-voltage source is used as a voltage source between the last-stage operation element and the previous-stage operation element. A level conversion circuit for level-converting a low-voltage output signal from a located arithmetic element into a high-voltage output signal of the high-voltage source is provided.

According to a second aspect of the present invention, in the arithmetic circuit according to the first aspect, the arithmetic circuit is an adder having a plurality of adding elements.

According to a third aspect of the present invention, in the arithmetic circuit according to the first aspect, the arithmetic circuit includes a plurality of AND circuits and a plurality of adders arranged in an array, and a plurality of logical AND circuits are provided at the lowest stage. It is a carry-save parallel multiplier in which bit adders are arranged.

According to the above construction, the arithmetic circuit according to the first to third aspects of the present invention has a plurality of arithmetic circuits located near the input side because only the last arithmetic element is driven by the high voltage source. The power consumption is lower than when the device is driven by a high voltage source. In addition, since the level conversion circuit is only arranged before the last operation element, compared with the case where the level conversion circuit is arranged before each of a plurality of operation elements located near the input side. In addition, the number of level conversion circuits can be reduced.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, but before that, the basic idea of the present invention will be described with specific examples.

FIG. 1 shows the overall configuration of an image processing apparatus A having a semiconductor integrated circuit. In FIG. 1, reference numeral 10 denotes an A / D converter for converting an external signal from analog to digital;
1 is a general-purpose DRAM, 12 is a semiconductor integrated circuit, which is a first semiconductor integrated circuit for taking out data from the DRAM 11 or performing image processing while storing data, and 13 is a general-purpose DRAM for controlling the first semiconductor integrated circuit 12 The microcomputer for controlling the first semiconductor integrated circuit 1
2 is a second semiconductor integrated circuit that receives a signal from the second and further performs image processing.

Reference numeral 15 denotes an externally arranged, for example, 3 V
The high-voltage source 16 is also a low-voltage source, for example 2 V, externally arranged. The image processing apparatus A shown in FIG. 1 includes a high-voltage line 17 connected to the high-voltage source 15 and the low-voltage source 1.
6 connected to the low-voltage wiring 18. In order to reduce the power consumption of the image processing apparatus A, the low voltage source 16 is used as a voltage source for the first and second semiconductor integrated circuits 12 and 14 for image processing. It is supplied only to the first and second semiconductor integrated circuits 12 and 14. On the other hand, the high voltage of the high-voltage wiring 17 is applied to other general-purpose circuits 10, 1
1, 13 are supplied. Since the interface voltage between the circuits 10 to 14 needs to be high, the high voltage wiring 17
High voltage is applied to two semiconductor integrated circuits 12, 1 for image processing.
4 as well.

The low voltage source 16 may be an internal low voltage source in which the voltage of the high voltage wiring 17 is reduced by an internal transistor by the threshold voltage. The configuration is described in, for example,
96369, the details of which are omitted. In this case, the low voltage source 16 arranged outside is unnecessary.

The first semiconductor integrated circuit 1 for image processing
FIG. 2 shows the internal configuration of No. 2. In the figure, reference numeral 20 denotes a chip, 21... Are a plurality of input / output pads arranged on the outer periphery of the chip 20, and 22 is the plurality of input / output pads 2.
The internal core portion 22 is provided with five functional blocks A to E except for the arrangement region of 1. The functional blocks A to D are arithmetic processing circuits that perform different arithmetic processing, and the functional block E is, for example, a ROM.
, A small-capacity memory cell such as a RAM.

The basic idea of the present invention is that, in the first semiconductor integrated circuit 12 for image processing, functional blocks A to D other than the functional block E composed of the memory cell section in the internal core section 22 are provided. Applied to

FIG. 3 is a logic circuit diagram of any one of the functional blocks (for example, A) of the first semiconductor integrated circuit 12.

The functional block (part of the semiconductor integrated circuit) shown in FIG. 13 shows a logic circuit obtained by performing logic synthesis from the RTL description shown in FIG. 29, reference numerals 2, 4, 6, and 8 denote registers r1, r2, r3, and r3 of the RTL description of FIG.
This is a flip-flop circuit constituting r4. Each of the registers r1 to r4 is applied to various registers such as a register constituting a part of a pipeline processing circuit of a computer. Also, 1, 3, 5 and 7 are combinational circuits func1, func2, fu described in the RTL description of FIG.
nc3 and func4 are combinational circuits located between the registers r1 to r4 or at the preceding stage. In FIG. 3, for the sake of simplicity, the output of each combinational circuit is input only to the flip-flop circuit at the next stage, but the signal may be transferred to another combinational circuit.

The flip-flop circuits 2, 6 and 8 are 2V systems using the 2V low voltage source 16 as a voltage source.
The remaining flip-flop circuit 4 has a voltage source of 2V / 3 using both power sources of a low voltage source 16 of 2V and a high voltage source 15 of 3V.
It is a V system. The 2V / 3V flip-flop circuit 4 has a level conversion circuit as described later, and the 2V flip-flop circuits 2, 6 and 8 do not have a level conversion circuit. Further, the combination circuits 1, 3 and 7 are 2V combination circuits (first circuit) using a 2V low voltage source 16 as a voltage source.
The remaining combinational circuit 5 is composed of a 3V combinational circuit (second combinational circuit) using a high voltage power supply 15 of 3V at the front as a voltage source, because of the demand for high-speed operation. 2 uses a low voltage source 16 of 2V as a voltage source.
It consists of a V-system combination circuit (first combination circuit).

In addition, 9 is a 2V clock buffer (clock supply means) using the 2V low voltage source 16 as a voltage source.
Wherein the four flip-flop circuits 2, 4,.
Clock is supplied to 6 and 8.

FIG. 4 shows the configuration of the flip-flop circuits 2, 6, and 8 having no 2V system level conversion circuit. In the figure, reference numeral 30 denotes a master latch for receiving one external signal D, and 31 denotes a slave latch which is connected in series to the output side of the master latch 30 and outputs two complementary signals. The slave latch 31 forms a temporary data storage unit 36. Each of the latches 30 and 31 is connected to an inverter 34.
a, 34b. 32 is the slave latch 31
The output buffer 33 connected to the output side of the internal clock CK and NCK complementary to the externally input clock CLK
Clock generation circuit (clock supply means) for generating clock
These circuits 30 to 33 are provided with a low voltage source 1 of 2V.
6 is a 2V system using a voltage source.

FIG. 5 shows the configuration of the flip-flop circuit 4 having the 2V / 3V system level conversion circuit. The flip-flop circuit 4 shown in FIG.
A master latch 30 and a slave latch 31 connected in series with the same configuration as the flip-flop circuit 2 of the system, an internal clock generation circuit 33, an output buffer 34 using the 3V high voltage source 15 as a voltage source, A level conversion circuit 35 is provided between the latch 31 and the output buffer 34. The level conversion circuit 3
Reference numeral 5 denotes a 2V / 3V system, in which the potential difference between complementary signals of the 2V system slave latch 31 is a low voltage (2V). Has a function of converting the level into a high voltage signal in which the potential difference between the signals is high voltage (3 V) and outputting the high voltage signal.

FIGS. 6A and 6B show a specific configuration of the level conversion circuit 35. FIG. In the level conversion circuit 35 of FIG. 7A, reference numerals 40 and 41 denote PMOS transistors, and reference numerals 42 and 43 denote NMOS transistors.
One PMOS type transistor 40 and one NMOS type transistor 42 are connected in series, and the other
The S-type transistor 41 and the other NMOS-type transistor 43 are connected in series.
Between the high voltage source 15 and the ground. The gate of the one PMOS transistor 40 is connected to the drain of the NMOS transistor 43 on the side not connected in series, and the gate of the other PMOS transistor 41 is connected to the drain of the NMOS transistor 42. The complementary output is taken from the drains of the NMOS transistors 42 and 43.

With the above configuration, the PMOS transistor 40 and the NMOS transistor 42, and the PMOS transistor 41 and the NMOS transistor 43 each perform the function of an inverter. That is, when a low voltage of 2 V is supplied to the gate of one NMOS transistor 43 and 0 V is supplied to the gate of the other NMOS transistor 42 by the complementary output of the slave latch 31 in FIG. The NMOS transistor 43 is turned on and the other NMOS transistor 42 is turned off.
F, and accordingly, one PMOS transistor 40 is turned on and the other PMOS transistor 41 is turned on.
Since the FF is performed, the drain of one NMOS transistor 42 is connected to the high voltage source 15 of 3V, and the drain of the other NMOS transistor 43 is grounded.
A complementary output with a high potential difference of 3 V is obtained.

In the configuration shown in FIG. 6A, a high voltage source 1 of 3 V is used.
The complementary output of the slave latch 31 of FIG. 5 is output from the low voltage of 2V without passing through current from the low voltage source 16 of 5 to 2V and through current from the high voltage source 15 of 3V to 0V (ground). The level can be converted to a high voltage of 3V.

FIG. 6B shows a level conversion circuit 35 'having another specific configuration different from the above. The level conversion circuit 35 'shown in FIG.
Instead of the two NMOS transistors 42 and 43,
This is one in which CMOS inverters 45 and 46 are arranged. Each of the CMOS inverters 45 and 46 is formed by connecting one PMOS transistor 47 and 49 and one NMOS transistor 48 and 50 in series. The complementary output signal of the slave latch 31 of FIG. 5 is input to the input terminals of the CMOS inverters 45 and 46, that is, both gates of the PMOS and NMOS transistors 47, 48, 49 and 50 connected in series. Is done. The output terminal of one CMOS inverter 45, ie, PMO
S type transistor 47 and NMOS type transistor 4
8 is connected to the gate of the PMOS transistor 41 not connected in series to the CMOS inverter 45, and the output terminal of the other CMOS inverter 46 is connected to the gate of the PMOS transistor 40 not connected in series to the CMOS inverter 46. Connected. The outputs of both CMOS inverters 45 and 46 are complementary outputs of the level conversion circuit 35 '.

With the above configuration, the through current from the high voltage source 15 of 3V to the low voltage source 16 of 2V and the through current from the high voltage source 15 of 3V to the ground do not flow and the slave latch 31 of FIG. The level of the complementary output can be converted from a low voltage of 2V to a high voltage of 3V. Furthermore, CMOS
The PMOS transistors forming the type inverters 45 and 46 suppress a through current from the 3 V high voltage source 15 to the ground in the transient state.

As can be seen from the above description, the semiconductor integrated circuit shown in FIG.
The flip-flop circuit 2 having a low-voltage / low-voltage 2V-system combination circuit 3 at the input and the 3V / 2-V-system combination circuit 5 at the output has a low-voltage / The flip-flop circuit 6 which is composed of a high voltage system (2 V / 3 V system), has a 3 V / 2 V system combination circuit 5 at the input and has a 2 V system combination circuit 7 at the output, is composed of a low voltage 2 V system Have been.

In the above description, the registers r1, r2, r
Although 3 and r4 are configured by flip-flop circuits, they may be configured by latch circuits instead of the flip-flop circuits.

FIGS. 7 and 8 show a specific configuration of the latch circuit. FIG. 7 shows a low-voltage 2V-system latch circuit 51. A latch circuit 51 shown in FIG. 7 includes a latch section (data temporary storage section) 52 which receives and latches one signal D and obtains a complementary output, and an output buffer 53 connected to the output side of the latch section 52. , An internal clock NG is generated from the external clock G, and this internal clock NG is
And an external clock G is also provided to the latch unit 52.
The above circuits 52 to 54 are 2V systems using the 2V low voltage source 16 as a voltage source.

FIG. 8 shows a low voltage / high voltage system (2 V / 3 V system).
Is shown in FIG. The latch circuit 51 'of FIG.
Is the same as that of the low-voltage 2V latch circuit.
A latch unit 52 and an internal clock generation circuit 54 using the V low voltage source 16 as a voltage source, an output buffer 55 using a 3 V high voltage source 15 as a voltage source, and a connection between the latch unit 52 and the output buffer 55 Input signal to a low voltage (2
V) to a high voltage (3 V). The specific configuration of the level conversion circuit 56 is the same as the specific configuration shown in FIG. 6A or 6B.

Next, an algorithm of a logic synthesis method for logic-synthesizing the semiconductor integrated circuit shown in FIG. 3 based on the connection information of the logic cells will be described with reference to the logic synthesis apparatus of FIG. 9 and the flowchart of FIG. .

FIG. 9 shows the overall schematic configuration of the logic synthesis device 60. In the figure, 61 is a reading unit, 62 is a translation unit, 63 is an optimization processing unit, 64 is a cell allocation unit, 65 is a timing verification unit, 66 is a circuit diagram generation unit, and 67 is an output unit.

The reading section 61 clearly defines the signal transmission relationship between registers based on the RTL description (hardware description language) shown in FIG. 29 or FIG. The netlist shown in FIG. 11 or FIG.
Enter the schematic shown in.

The translation unit 62 converts the RTL description read from the reading unit 61 into a state transition diagram, a Boolean expression, a timing diagram, and memory specifications such as memory type, number of bits and number of words.

The optimization processing unit 63 includes a state transition diagram optimization processing unit 63a for optimizing the obtained state transition diagram and a state for generating a circuit (state machine) corresponding to the optimized state transition diagram. A machine generator 63b, a compiler 63c for compiling a timing diagram obtained for compiling the obtained timing diagram, a composing unit 63d for composing a memory based on the specification of the obtained memory, Combining unit 63 for combining the interface unit based on the stored memory
e. Further, the optimization processing unit 63 includes the reading unit 6
If the input to 1 is an RTL description, the logic is optimized based on the obtained state machine, the obtained Boolean expression and the synthesized interface unit, and the connection information of the optimized logic cell is obtained. While generating, the reading unit 61
In the case where the input to is a netlist or schematic, there is a logic optimization unit 63f that optimizes the logic of the input netlist or schematic and generates connection information of the optimized logic.

The output unit 67 externally outputs a netlist indicating the logic circuit of FIG. 3 or a logic circuit diagram (schematic) obtained by schematizing the netlist.

The characteristic point exists in the cell allocating section 64 shown in FIG. Next, based on the cell allocation (cell mapping) processing by the cell allocation section 64, ie, the cell connection information obtained by the logic optimization section 63f, FIG.
The algorithm for logically synthesizing the semiconductor integrated circuit shown in FIG. 1 will be described with reference to the flowchart of FIG. Note that FIG. 13 mainly illustrates a characteristic portion.

In the figure, starting and step S
After performing a function design using HDL (hardware description language) in step 1, the HDL description is input in step S2, and based on the input HDL description, a high voltage is output from a logic cell library shown in the table of FIG. (3V) logic cell library (hereinafter referred to as “lib”) is selected, and this 3V
The combination circuit is mapped by lib.

Next, in step S3, after calculating the maximum delay time of the mapped combinational circuit, it is determined whether or not this maximum delay time exceeds the designed delay upper limit. Creates a new HDL description by correcting the input HDL description or redoing the function design in step S4. For example, in the partial circuit shown in FIG. 15, when a combinational circuit f is located between two registers r1 and r2 and the function of the combinational circuit f is composed of functions A and B, the combinational circuit f When the maximum delay time exceeds the delay upper limit value, as shown in FIG. 16, the combinational circuit f is divided into two combinational circuits f1 and f2, and the function A is assigned to the combinational circuit f1,
2 has a function B, and the two combination circuits f1,
HDL so that one register is separately arranged between f2 and three registers r1 to r3 are provided in total.
The description is modified from the function description shown in FIG. 17 to the function description shown in FIG.

Thereafter, in steps S5 to S9 (first step), the combinational circuit whose signal propagation delay time is equal to or less than the designed delay upper limit value is set to the 2V low voltage source 1
6 is combined with a first combinational circuit having a voltage source, and conversely, a combinational circuit having a signal propagation delay time exceeding a design delay upper limit value has a high voltage source 15 of 3 V at the front thereof as a voltage source. In addition to combining with the second combinational circuit, the rear part is combined with the second combinational circuit using the 2V high voltage source 16 as a voltage source.

The first step is performed as follows. That is,
First, in step S5, all the combinational circuits are set to the low voltage (2
The combination is performed by a V) -system combination circuit (first combination circuit), and then, in step S6, the signal propagation delay time of each combined circuit is calculated for each signal propagation path. Then, it is determined whether or not the calculated delay time exceeds an upper limit in design.
After extracting all the combinational circuits whose delay time exceeds the design upper limit value in step 8, the combining operation of steps S8 and S9 is performed for each of the extracted combinational circuits. That is, assuming that each of the extracted combinational circuits is composed of a plurality of (m) combinational parts, the n-th (initially n = 1) combinational part is set as a high-voltage (3V) combinational part in step S8. After re-synthesizing by the circuit (second combination circuit), step S
In step 9, the maximum delay time of the recombined combinational circuit is compared with the upper limit in design, and if it exceeds the upper limit, the next combination unit (n = 2nd combination) in the signal propagation direction ) Is recombined by a combination circuit (second combination circuit) in which the high-voltage (3V) combination unit is used. The above operation is repeated until the maximum delay time of the combinational circuit after re-synthesis becomes equal to or less than the upper limit in design.

Subsequently, in steps S10 to S12 (second step), the following processing is performed. That is, in step S10, the combination circuit of the 2V system and the combination circuit of the 3V system are mixed so that the output of the combination circuit of the low voltage system (2V system) becomes the input of the combination circuit of the high voltage system (3V system). It is checked whether or not there is a mixture of the above shapes.
After extracting all the 2V system combination circuits in the mixed form in step S12, the extracted 2V system combination circuit (first combination circuit) is replaced with a 3Vlib combination circuit (second combination circuit) in step S12. Mapping again. After this remapping, the process returns to step S10, and the operations of steps 11 and S12 are repeated again. This takes into account that the remapping to the 3V-system combination circuit in step 12 may cause a new mixture of the 2V-system combination circuit and the 3V-system combination circuit. It is.

Thereafter, since the voltage systems of the combinational circuits located on the input side and the output side of the register have already been determined by the above-described logic synthesis, steps S13 to S15
In the (third step), the following processing is performed. That is, step S
At 13, it is checked whether or not each register converts the potential from a low voltage (2V) input to a high voltage (3V) output.
If the level conversion is not to be performed, the register whose level is not to be converted is mapped to the 2V system flip-flop circuit in FIG. 4 or the 2V system latch circuit in FIG. 7 if the level conversion is to be performed. Register (flip-flop circuit or latch circuit)
8 or the 2V / 3V flip-flop circuit shown in FIG.
2V / 3V system latch circuit.

Therefore, in the algorithm of the logic synthesis method shown in FIG. 13, when all the combinational circuits are mapped by the low-voltage (2 V) combinational circuit (first combinational circuit), for example, FIG. As shown, when the delay time of the signal propagation path of one combinational circuit 70 located between two predetermined registers exceeds the designed delay upper limit, as shown in FIG. Among them, as shown by hatching in the figure, the first and second combination parts 70a and 70b located at the front part (the starting point of signal propagation)
After mapping to the combination circuit of the system, when the combination unit of the 2V system and the combination circuit of the 3V system in which the output of the combination unit of the 2V system becomes the input of the combination circuit of the 3V system,
As shown in FIG. 11C, the combination part 71a of the mixed 2V system combination circuit 71 is remapped to a 3V system combination part as shown by hatching in the figure. Subsequently, it is determined whether or not a new combination of the combination part of the 2V system and the combination part of the 3V system has newly occurred by the remapping, and FIG.
In the case where the flip-flop circuit needs to level-convert the potential from a low-voltage (2 V) input to a high-voltage (3 V) output, as shown in FIG. Then, the flip-flop circuit for level conversion is mapped to a 2V / 3V-system flip-flop circuit as shown by hatching in the figure.

Therefore, in the finally obtained semiconductor integrated circuit shown in FIG. 4D, as shown in FIG. 4E, the combinational circuit 7 whose signal propagation delay time exceeds the design delay upper limit value is used.
Compared to the case where all the combination parts of 0 are mapped by the combination parts of the 3V system, the number of combination parts to be mapped to the combination parts of the 3V system can be reduced, so that the power consumption can be reduced.

FIG. 20 shows another specific example. In this specific example, a binary search is performed to determine the boundary between the front part and the rear part of the combinational circuit, that is, the boundary between the combinational part to be combined with the 3V combinational circuit and the combinational part to be combined with the 2V combinational circuit. Law (bin
ary search method) (for example, see “Iwanami Koza Software Science 2 Programming Method” by Kei Kawai, Iwanami Shoten 1988, pp. 143 and 144).

That is, steps S18 to S27 (first
In the step (b), the boundary between the front part and the rear part of the combinational circuit is searched using the binary search method, and the front part is synthesized into a second combinational circuit using the 3V high voltage source 15 as a voltage source. The subsequent part is combined with a first combinational circuit using the 2V low voltage source 16 as a voltage source.

More specifically, in the first step,
In step 18, first, all the combinational circuits are mapped by a low-voltage (2V) combinational circuit, and in step S19, whether or not each maximum delay time of each combinational circuit exceeds a design upper limit value. Is determined, and if it exceeds, all such combinational circuits are extracted in step S20, and the operations of steps S21 to S27 are performed on all the extracted combinational circuits. First, in step S21, the addresses of the first and last combination units to be mapped by the 2V-system combination circuit are set to ks and ke, and these addresses are set to ks
= 1 and ke = m (m is the number of combination units constituting the combinational circuit), and then, in step S22, it is determined whether or not ke-ks = 1, and if ke-ks = 1, Can not be 2 minutes and immediately proceeds to the second step, but initially k
Since e−ks ≠ 1, the intermediate value k is calculated by the following equation k = (ks + ke) / 2 in step S23, and the first to k-th combination parts are mapped by the 3V system lib in step S24. , K +
The first to m-th combination parts are mapped by the 2V-system lib.

Thereafter, the maximum delay time of the combinational circuit after the mapping is calculated, and in step S25, this delay time is compared with the upper limit of the designed delay. In step S26, the first address ks is set to the obtained intermediate value k (ks = k) in order to further divide the combination part into 2 (ks = k). In step S27, the last address ke is set to the intermediate value k (ke = k) in order to further divide the combination part into two.
Return to If ke-ks = 1 in step S22, it is determined that the boundary between the front part and the rear part of the combinational circuit has been searched by the binary search method, and the process proceeds to the second step.

Since the second step and the third step are the same as those of the first embodiment described above, the same steps as those in the flowchart of FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted.

Therefore, in this specific example, when a combinational circuit composed of, for example, 20 logic gates has a critical path, first, the first 10 stages are set to 3 Vlib and the second 10 stages are set to along the signal flow. After re-combining to 2 Vlib, the condition of maximum delay> upper limit value is checked, and if YES, the latter 10 stages are further divided into two to connect to the end point.
Recompose the stages to 2Vlib and the others to 3Vlib. Also,
If NO, the first 10 stages are further divided into two, and the 5 stages connected to the starting point are recombined into 3 Vlib and the others into 2 Vlib.
Further, the condition of maximum delay> upper limit is checked, and this process is repeated. If the binary search method is used, the boundary can be searched by several resynthesis processes, so that the processing can be speeded up.

FIG. 21 shows still another specific example. In the present embodiment, the configuration is such that the boundary between the front part and the rear part of the combinational circuit is roughly estimated.

That is, in the figure, after starting, a functional design using HDL is performed in step S1, and a high voltage (3V) lib is generated based on the HDL description in step S2.
The signal propagation delay time of each combinational circuit when the combinational circuit is mapped is estimated in step S3, and it is determined in step S3 whether or not the estimation result exceeds a design delay upper limit value.
If it exceeds the delay upper limit value, a new HDL description is created in step S4 by modifying the input HDL description or redoing the function design as shown in FIGS.

Thereafter, in steps S30 to S37 (first step), the boundary between the front part and the rear part of the combinational circuit is roughly calculated, and the front part is determined by using the 3V high voltage source 15 as the voltage source. 2 and a subsequent portion is combined with a first combinational circuit using the 2V low voltage source 16 as a voltage source.

More specifically, in the first step,
First, in step 30, all the combinational circuits are set to 2Vlib.
The signal propagation delay time of each combinational circuit when mapping is performed is estimated, and the respective delay times are compared with the designed delay upper limit value in step S31. If the delay time is equal to or smaller than the upper limit value, the delay time is determined in step S32. The following combinational circuit
Mapping by Vlib.

On the other hand, if the delay time exceeds the upper limit value, all the combinational circuits whose delay estimation results exceed the upper limit value are extracted in step S33, and then the processing of steps S32 and S34 to S37 is performed on each of the combinational circuits. Perform the operation. First, in step S34, the result of delay estimation is divided by the upper limit value, and the existence ratio p of 3Vlib and 2Vlib is calculated based on the result of the division. In step S35, the number of stages of the logic gate (combination unit) constituting the combinational circuit And the ratio p
To calculate the mapping range of 3Vlib, that is, the range of the logic gates constituting the front part. Thereafter, in step S36, it is determined whether or not each logic gate is within the calculated 3Vlib mapping range. If so, the logic gate is mapped by 3Vlib in step S37. Is Step S
At 32, the logic gate is mapped by 2Vlib.

Since the second and third steps are the same as those of the first embodiment, the same steps as those in the flowchart of FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted.

Therefore, in this specific example, for example, assuming that the delay of 2 Vlib is 1.8 when the delay of 3 Vlib is “1” and the upper limit of the designed delay is 50 ns, the delay of the critical path is 90 ns. In the case of (1), the entire critical path is set to the synthesis range of 3Vlib. Further, when the delay of the critical path is 50 ns, there is no 3Vlib synthesis range of the critical path, and all the combination parts are synthesized with 2Vlib. When the delay of the critical path is 60 ns, a range of 1/4 from the starting point of the critical path becomes a front part, and this range is a configuration range of 3 Vlib. Is the front part and is synthesized at 3 Vlib. In the case of 80 ns, 3
The range of / 4 is the front part and is synthesized at 3 Vlib.

In this example, since the boundary between the combination part combined by 3Vlib and the combination part combined by 2Vlib (the boundary between the front part and the rear part) is roughly calculated, the processing speed of the logic combination is high. However, the calculation accuracy of the boundary is not high. In normal logic synthesis, after performing logic synthesis once,
In some cases, the circuit synthesis is performed again based on the synthesis result to optimize the circuit. In this case, the first logic synthesis is performed according to this specific example, and the subsequent resynthesis is performed as described above.
According to one specific example, while improving the processing speed of the logic synthesis, the calculation accuracy of the boundary is improved, and the high voltage (3 V)
The number of combination parts synthesized by ib can be limited to a minimum, and the power consumption can be further reduced.

FIG. 22 shows another specific example. In this specific example, when it is known in advance that mapping a predetermined combination part of the plurality of combination parts constituting the combination circuit with 3 Vlib can produce a semiconductor integrated circuit having better power consumption. This specifies that the mapping by 3Vlib is to be performed in advance for a predetermined combination part.

That is, in the logic synthesis method of FIG.
Steps S40 to S45 are added before the first step (steps S5 to S9). In this additional step, first, in step S40, a predetermined combination part is set to 3Vli.
b, it is determined whether or not the logical designer designates the mapping. If so, the HD is determined in step S41.
L is designated to map a predetermined combination part by 3Vlib. This specification is performed, for example, as shown in FIG. 23 with respect to a normal function description of an adder for adding eight input data a, b, c, d, e, f, g, and h as shown in FIG. Specifies that the last adder element is mapped by 3Vlib. “// low-powe” in Figure 23
r-synthesis-high-voltage "is the specified part.

Thereafter, a function description is input, and step S4
In step 2, it is determined whether or not the combination part is designated as described above. If there is no designation, all combination parts are mapped by 2Vlib. If there is designation, the designated combination part is designated by 3Vlib in step S43. Map.

Next, in step S44, it is determined whether there is a mixture of the 2V system combination unit and the 3V system combination unit in a form in which the output of the 2V system combination unit is input to the 3V system combination unit. Only when there is, in step S45, a level conversion circuit is inserted in the preceding stage of the 3V system combination part in the mixture. The level conversion circuit to be inserted is shown in FIG.
A level conversion circuit 35 shown in (a) and a level conversion circuit 35 'shown in FIG.

The first step (steps S5 to S9) and the second step
(Steps S10 to S12) and the third step (Steps S13 to S15) are the same as those in the flowchart of FIG. 13, and therefore, the same steps are denoted by the same reference characters and description thereof is omitted. However, in the second step, if there is no mixture in step S10, 3V is applied in step S50.
It is determined whether there is a level conversion circuit between the system combination unit and another 3V system combination unit. If there is a level conversion circuit, it is added to delete the level conversion circuit in step S51. Is done. This is because, when the 2V-system combination part is replaced by the 3V-system combination part by the re-synthesis processing in the second step, the replaced 3V-system combination part and another 3V-system combination part are replaced.
This is because it is assumed that a level conversion circuit is included between the system and the combination unit.

Therefore, in this specific example, FIG.
The logical synthesis method of FIG. 13 using the normal function description (there is no designation of a predetermined combination part to be mapped by 3Vlib) is the adder having seven addition elements (arithmetic elements) shown in FIG. In FIG. 4C, four adder elements located at the preceding stage are indicated by hatching in FIG.
Vlib and the preceding 8
In this specific example, as shown by hatching in FIG. 4B, only the last adder element located at the last stage is set to 3Vlib by the 2V / 3V system flip-flop circuit. And the level conversion circuit is arranged at the preceding stage. In this specific example, the number of combination parts combined at 3 Vlib is smaller, and low power consumption can be achieved.

FIGS. 26 to 28 show still another specific example. In this specific example, the part to be combined with the second combination circuit using the high voltage source 15 of 3V as the voltage source is not limited to the front part, of the combination circuits in which the signal propagation delay time exceeds the upper limit.
It is appropriately selected from the viewpoint of the area or the processing speed.

FIG. 26 shows the first half of the flowchart of FIG. 21, and FIG. 27 shows the second half of the flowchart. Step S35 of the flowchart is changed to steps S60 to S69 of FIG. 2 between step S10 and step S13 of FIG.
7, steps S70 and S71 are added.

Specifically, in FIG. 26, in step S34, the high voltage (3V) li in one combinational circuit is determined based on the estimation result of the signal propagation delay time and the upper limit value of the designed delay.
After calculating the ratio P between b and the low voltage (2V) lib,
In step S60, the total number of gate stages of the combinational circuit is multiplied by the ratio P, and the high voltage (3
V) The number of gate stages mapped by lib (high voltage (3
V) Lib mapping range) is calculated. Subsequently, in step S61, a mapping range (predetermined size) of the high voltage (3V) lib is set as a search range (window).
After calculating the number n of windows in one combinational circuit, each of the plurality of windows n is evaluated in step S62 and thereafter. That is, first, the variable k is set to an initial value (= 0) in step S62, and then k = k + 1 in step S63.
Is set in step S64, and the combination part in the first window is set in step S64, and the area and delay of the combination part in this window are evaluated in step S65. After that, in step S66, the variable k is compared with the number n of the windows. If k <n, the process returns to the step 63 to sequentially calculate the total area and delay of the combination parts in the second to n-th windows. evaluate. Then, in step S67, a window having the smallest total area or the smallest delay of the combination part existing in the windows among the plurality of windows is selected. In step 68, if the selected window is not the first window In step S69, a level conversion circuit is inserted before the selected window.

In FIG. 27, at step S10, 2V
If the combination of the combination part of the system and the combination part of the 3V system is eliminated, the combination part of the 3V system and the other three
It is determined whether or not there is a level conversion circuit between the V-system combination unit and, if so, the 3V-system combination unit and another 3V-system combination unit are recombined in the second step. Since it is a situation that a level conversion circuit is to be included between the combination unit and the combination unit, it is added to delete the level conversion circuit in step S71.

Therefore, this embodiment has the following advantages. That is, the combinational circuit shown in FIG.
In the first, second, and third windows shown by hatching in FIGS. 7A, 7B, and 7C, the adder having seven adding elements shown in FIG. In the third window c), the total area (number) of the adder elements is minimized, so that this range is mapped with a high voltage (3V) lib. Therefore, the number of adder elements mapped by the high voltage (3V) lib can be minimized, and power consumption can be further reduced.

(Embodiment) FIGS. 33 and 34 show an embodiment of the present invention. In FIG. 22 to FIG. 25, the combination part located at the last stage of the adder is synthesized by 3Vlib instead of the combination part located at the last stage in the adder.

FIG. 33 shows a function description including a designation to combine the combination unit located at the last stage of the carry-save parallel multiplier by 3Vlib. This function description is input to the reading unit 61 of the logic synthesis unit 60. Is done.

FIG. 34 shows a carry-save-type parallel multiplier logically synthesized according to the function description input to the reading section 61. The parallel multiplier shown in the figure has a configuration in which a plurality of AND circuits 90 as operation elements, a plurality of half adders HA and full adders FA are arranged in an array, and a multi-bit adder 91 is arranged as an operation element at the last stage. . The lowermost full adder 91 is synthesized by 3Vlib, and the others are synthesized by 2Vlib. In addition, 16 level conversion circuits 9 are provided before the lowest full adder 91.
2 are arranged. Each of the level conversion circuits 92 converts the level (2 V) of the signal input from the previous-stage adder to a high level (3 V) and outputs it.

Therefore, in this embodiment, since the carry-save-type parallel multiplier is used, the adder array occupying most of the circuit may be a normal adder, but the lowermost adder 91 is operated at high speed. There is a need. In this case, in order to increase the speed, the adder 91 of the lowermost stage normally uses an adder of a carry look ahead. However, since the lowermost adder 91 is a high voltage (3 V) system, the speeding up is performed. As a result, it is possible to generate a multiplier that is faster than in the past. Others operate at low voltage, and thus consume low power. Moreover, the level conversion circuit 92 is the last adder 91
, The number of level conversion circuits can be reduced and the circuit size can be reduced as compared with the case where the level conversion circuits are disposed near the input side.

In this embodiment, the carry-save parallel multiplier has been described. Of course, the same can be applied to the divider.

In the above description, the present invention has been applied to the functional block A constituting the memory cell section E other than the memory cell section E formed in the internal core section 22 of the chip 20, but to the other functional blocks BD. Can of course be applied similarly.

[0088]

As described above, according to the arithmetic circuit according to the first to third aspects of the present invention, only the last operation element is driven by the high voltage source, and the preceding operation element of the last operation element is driven. Since the level conversion circuit is disposed in the circuit, the number of arithmetic elements driven by a high voltage source and the number of level conversion circuits are limited to a small amount, so that power consumption can be reduced and the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is an overall schematic configuration diagram of an image processing system.

FIG. 2 is an overall schematic configuration diagram of a semiconductor chip.

FIG. 3 is a diagram illustrating a connection relationship between a plurality of registers and a plurality of combinational circuits of the semiconductor integrated circuit;

FIG. 4 is a configuration diagram of a flip-flop circuit having no level conversion circuit.

FIG. 5 is a configuration diagram of a flip-flop circuit having a level conversion circuit.

FIG. 6 is a diagram showing a specific configuration of a level conversion circuit.

FIG. 7 is a configuration diagram of a latch circuit having no level conversion circuit.

FIG. 8 is a configuration diagram of a latch circuit having a level conversion circuit.

FIG. 9 is a diagram showing an overall schematic configuration of a logic synthesis device.

FIG. 10 is a diagram illustrating a hardware description language.

FIG. 11 is a diagram showing a net list.

FIG. 12 is a diagram showing a schematic.

FIG. 13 is a diagram illustrating a logic synthesis method of a semiconductor integrated circuit.

FIG. 14 is a diagram showing a table of a cell library.

FIG. 15 is a diagram showing a part of a semiconductor integrated circuit.

FIG. 16 is a diagram showing a circuit in which a part of a semiconductor integrated circuit is changed.

FIG. 17 is a diagram showing a description of a register transfer level.

FIG. 18 is a diagram showing a description of a register transfer level corrected when logical synthesis cannot be performed.

FIG. 19 is a diagram illustrating the order of the logic synthesis method.

FIG. 20 is a diagram illustrating a logic synthesis method.

FIG. 21 is a diagram illustrating a logic synthesis method.

FIG. 22 is a diagram illustrating a logic synthesis method.

FIG. 23 is a diagram showing a function description that is an input of a logic synthesis method.

FIG. 24 is a diagram showing a function description which is an input of a conventional logic synthesis method.

FIG. 25 is a diagram illustrating an adder generated by a proposal example of the present application and a conventional logic synthesis method.

FIG. 26 is a diagram showing the front part of the logic synthesis method.

FIG. 27 is a diagram illustrating the rear part of the logic synthesis method.

FIG. 28 is a diagram illustrating an adder generated by a logic synthesis method.

FIG. 29 is a diagram showing a description of a register transfer level.

FIG. 30 is a diagram showing a logic circuit of a conventional semiconductor integrated circuit.

FIG. 31 is a diagram showing an arrangement position of a level conversion circuit when only a critical path is driven by a high voltage source in an arbitrary semiconductor integrated circuit.

FIG. 32 is a diagram showing an arrangement position of a level conversion circuit when only a critical path is driven by a high voltage source in another arbitrary semiconductor integrated circuit.

FIG. 33 is a diagram illustrating an example of a functional description for designing an arithmetic circuit according to an embodiment of the present invention.

FIG. 34 is a circuit diagram showing a carry-save-type parallel multiplier according to an embodiment of the present invention.

[Explanation of symbols]

90 AND circuit (arithmetic element) HA Half adder (arithmetic element) FA Full adder (arithmetic element) 91 Full adder at the last stage (arithmetic element at the last stage) 92 Level conversion circuit

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H03K 19/20

Claims (3)

[Claims] 1. A predetermined number of arithmetic elements arranged in a row are regarded as one stage, and a plurality of arithmetic elements in a row are arranged in a row. The first arithmetic element receives a signal from the outside and excludes the first arithmetic element. The operation element at each stage receives an output from the operation element located at the previous stage, and the operation element at the last stage is an operation circuit that externally outputs an operation result. The operation element at the last stage uses a high voltage source as a voltage source. The operation elements other than the last operation element use a low voltage source as a voltage source, and the high voltage source is used as a voltage source and the last An arithmetic circuit, comprising: a level conversion circuit for level-converting a low-voltage output signal from an arithmetic element positioned in front of the arithmetic element into an output signal having a high voltage from the high-voltage source. 2. The arithmetic circuit according to claim 1, wherein said arithmetic circuit is an adder having a plurality of adders. 3. The arithmetic circuit is a carry-save parallel multiplier in which a plurality of AND circuits and a plurality of adders are arranged in an array, and a multi-bit adder is arranged at the lowest stage. The arithmetic circuit according to claim 1, wherein: