JPH10312373A - Parallel correlation processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a real-time correlation process for a high-speed pseudo- random signal (PN) signal) by using an existing DSP(digital signal processor). SOLUTION: A spectrum spread communication type receiver distributes a receive signal including a PN signal of spread code length 2<n> and a signal speed S to output terminals D1 to DP by chips through a signal conversion part 2, and PN signals (signal speed S/P) sampled by P chips are inputted to P correlation processing blocks B1 to BP which are provided in parallel. In the respective correlation processing blocks B1 to BP, P correlation processing units are provided, partial correlation processes are performed by using reverse spread patterns of 2<n> /P chips generated from reverse spread patterns, and correlation results are outputted from the respective correlation processing blocks B1 to BP. The outputs are rearranged in series on the time base by a signal speed conversion part 4 and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlation processing circuit, and more particularly, to a correlation processing circuit suitable for use in a receiver of a spread spectrum communication system using a high-speed pseudo random signal (PN signal).

[0002]

2. Description of the Related Art In recent years, spread spectrum communication systems have attracted attention in mobile communications and the like. In this method, information is spread-modulated using a pseudo-random code (PN code) sequence to a band wider than a required frequency band and transmitted, and the reception side is despread by multiplying a received input signal by the PN code sequence. It is a communication system that performs processing and reproduces the information, and has characteristics such as being strong against noise and excellent in secrecy.

In order to receive and despread a pseudo-random signal (PN signal) in such a spread spectrum communication system receiver, a correlation processing circuit using a digital signal processor (DSP) is usually used. ing. In general, in a correlation process, it is necessary to perform a product-sum operation between a plurality of bits. Therefore, the operation speed of such a DSP cannot be increased so much, and the operation speed of a currently used DSP is the fastest. Is said to be about 33M chips / sec.

Therefore, when trying to receive a spread spectrum signal using a high-speed PN signal using such a DSP, it is not possible to perform despreading processing in real time. FIG. 7 shows a configuration example of a correlation processing circuit of a receiver of a spread spectrum communication system using a high-speed PN signal. Here, one information symbol is a PN of N chips.
It is assumed that the code is directly spread-spectrum modulated, and the signal speed is S (chip / sec). Further, the arithmetic processing speed of the DSP used for the correlation processing is S ′ (chip / sec).
c) and S> S ′ as described above.

In FIG. 7, reference numeral 1 denotes an A / D conversion circuit which samples a received signal in accordance with a PN signal clock (frequency = S) and converts it into a k-bit digital signal;
Is a memory circuit that temporarily stores the output of the A / D conversion circuit 1, and 6 is an N-stage shift register that reads the output of the memory circuit 13 according to a shift clock (frequency = S ′) and sequentially shifts the output. Composed shift circuit, 7
Saves the despread pattern quantized to k bits N
A despreading pattern storage circuit 8 constituted by a buffer of stages is used for storing the received signal sequentially stored in each stage of the shift circuit 6 and the despreading pattern stored in each stage of the despreading pattern storage circuit 7. It is a correlation detection circuit that performs a correlation operation.

The correlation detection circuit 8 is provided with the shift circuit 6
Multiplying the k-bit output of each stage by the k-bit content of each stage of the despreading pattern storage circuit, and outputting an r-bit multiplication result; An adder circuit 14 adds the outputs of the circuit 15 and outputs an m-bit correlation output. Here, the shift circuit 6, the despreading pattern storage circuit 7, and the correlation detection circuit 8 are constituted by a DSP.

In the thus constructed correlation processing circuit, the received signal is converted into a k-bit digital signal by the A / D conversion circuit 1 based on the PN signal clock (S) that matches the PN signal speed. Thereafter, it is temporarily stored in the memory circuit 13. On the other hand, since the processing speed of the correlation detection circuit 8 is lower than the PN signal speed as described above, the received signal stored in the memory circuit 13
The signal is read out by a shift clock (S ′) lower than the signal speed (S) and is input to the shift circuit 6. The contents of the shift circuit 6 are sequentially shifted repeatedly by the shift clock (S '), and each time the contents of the shift circuit 6 and the contents of the despreading pattern storage circuit 7 are subjected to correlation detection by the correlation detection circuit 8. Thus, a high correlation signal can be obtained when the contents of each stage in the shift circuit 6 match the contents stored in the despreading pattern storage circuit.

[0008]

As described above, the multiplication circuit 15 for performing a product-sum operation between a plurality of bits (k bits) is used.
The arithmetic processing speed of the DSP suitable for the design of the correlation detection circuit 8 composed of the adder circuit 14 is low, so that when a high-speed PN signal is used, the correlation processing cannot be performed in real time. It is necessary to temporarily store the received signal. Further, the capacity of the memory circuit 13 needs to be large, and furthermore, there is a problem that when the capacity of the received signal exceeds the capacity of the memory circuit 13, normal reception cannot be performed.

As described above, when increasing the signal speed of the PN signal used for spread spectrum communication, the operation speed of the correlation processor of the receiver becomes a problem. Generally, the correlation processing device is used not only in the spread spectrum communication system but also in various fields such as pattern matching.
In these cases as well, an improvement in processing speed is required.

Accordingly, the present invention provides a DSP which cannot perform high-speed PN signal correlation processing in real time.
An object of the present invention is to provide a correlation processing circuit that can perform high-speed correlation processing of a high-speed PN signal, which has been impossible in the past, using real-time processing. It is another object of the present invention to provide a parallel correlation processing circuit capable of performing high-speed correlation processing.

[0011]

To achieve the above object, a parallel correlation processing circuit according to the present invention is a parallel correlation processing circuit in a spread spectrum communication system receiving apparatus for receiving a pseudo random signal having a code length of N. Then, the received signal of the signal speed S is sampled one chip at a time and sequentially output to P output terminals (P is an integer of 2 or more), and the signal speed (S / P)
And a parallel operation processing block disposed downstream of the signal speed conversion unit, wherein the P output signals from the signal speed conversion unit are input. A parallel processing block having P parallel processing blocks provided in parallel, and correlation outputs respectively output from the P correlation processing blocks of the parallel processing block are sequentially selected and arranged in series on a time axis. And a signal speed inverse conversion unit having a function of changing the signal speed, wherein each of the P correlation processing blocks is provided with P correlation processing units, and each of the P correlation processing units is required for despreading. Correlation processing is performed using the despreading pattern of (N / P) chips generated from the despreading pattern of N chips, and the P correlation processing blocks are required for the despreading. That N in which correlation of the phase different despreading patterns by one chip despreading pattern of the chip have been made to run in parallel.

In addition, an analog-to-digital converter for converting the received signal into a digital signal is provided at a stage preceding the parallel processing block, and the parallel processing block is realized by a digital signal processor. is there. Further, each of the correlation processing blocks includes a P correlation processing unit provided corresponding to each output terminal of the signal speed conversion unit, and a unit addition unit that adds output signals of the P correlation processing units. And each of the correlation processing units sequentially reads and shifts a signal output from a corresponding output terminal of the signal speed conversion unit at a parallel signal speed (S / P), and shifts the signal in (N / P) stages. A despreading pattern storage unit for storing a despreading pattern of the spreading code length (N / P), and a product-sum operation result of the contents of the shift unit and the contents of the despreading pattern storage unit as a correlation signal. It has a correlation detection unit.

Further, a first despreading pattern having a code length (N / P) obtained by sampling a despreading pattern having a code length N required for the despreading for every P chips; A second to a P-th despreading pattern having a code length (N / P) obtained by shifting each of the N despreading patterns by one chip and sampling each P chip;
The (P + 1) th to (2P-1) th despreading patterns obtained by sequentially shifting each code backward in the Pth despreading pattern and moving the last code to the forefront are stored. To provide a parallel correlation coefficient database
For the despreading pattern storage circuits in the first to Pth correlation processing units of the first correlation processing block, the first to Pth despreading patterns are read out from the parallel correlation processing coefficient database and set, respectively. Each of the despreading pattern storage circuits in the first to (i-1) th correlation processing units of the i correlation processing block (i = 2 to P) stores the (P + i) th data from the parallel correlation processing coefficient database.
-1) to (P + 1) -th despreading pattern are read and set, and the first to (P-th) despreading pattern storage circuits in the i-th to P-th correlation processing units are stored.
The despreading pattern of (i + 1) is read and set.

Still another parallel correlation processing circuit according to the present invention is a speed conversion circuit for sequentially switching input data input continuously to P output terminals (P is an integer of 2 or more) and outputting the data. P correlation processing blocks connected in parallel to the output of the speed conversion circuit, and a speed inverse conversion circuit for sequentially selecting and outputting the outputs of the P correlation processing blocks, wherein the input data and N A parallel correlation processing circuit that performs correlation processing with a pattern of bits (N is an integer of 2 or more), wherein each of the correlation processing blocks is provided corresponding to each of P outputs of the speed conversion circuit, P correlation processing units for performing a correlation process between the output from the speed conversion circuit and an N / P bit pattern obtained by extracting the N bit pattern every P bits, and the P correlation processing units of It has a unit adder circuit for adding the force, in the P number of correlation processing block, in which is adapted to perform a correlation processing for pattern obtained by shifting the pattern of the N-bit by one bit, respectively.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The parallel correlation processing circuit of the present invention is not limited to a spread spectrum communication type receiver, but can be applied to correlation processing in any field. An embodiment in which the parallel correlation processing circuit is used in a spread spectrum communication type receiver will be described.

FIG. 1 is a block diagram showing the configuration of this embodiment of the parallel correlation processing circuit of the present invention. In this embodiment, the code length N of the PN signal is set to 2 ⁿ (n
Is an integer), and the signal speed of the PN signal is S chips / sec.
It is described as c. In FIG. 1, reference numeral 1 denotes a received signal
An analog-to-digital conversion circuit (A / D conversion circuit) that samples by a signal clock (frequency = S) and converts the data into k-bit digital data, operates according to the PN signal clock, and performs the A / D conversion. This is a signal speed conversion circuit for sequentially sorting and outputting k-bit received data output from the circuit 1 to P (P is an integer of 2 or more) output terminals D _{1 to} D _P. Reference numeral 5 denotes a parallel operation processing block, and as shown, P correlation processing blocks B _{1 to} B _P having the same configuration are provided in parallel.

In each of the correlation processing blocks B _{1 to} B _P , P input terminals IN 1 to INP connected to P output terminals of the signal speed conversion circuit 2 and a frequency (S /
P) a clock input terminal to which a parallel signal clock is input and an output terminal OU to output a t-bit correlation output
T is provided. 4 is a signal speed reverse conversion circuit,
The output terminal OUT of the P input terminal IN1~INP and t bits correlation output t bits are input from the correlation processing block B ₁ .about.B _P is provided.

As shown, the A / D conversion circuit 1,
A PN signal clock of frequency S is applied to the signal speed conversion circuit 2 and the signal speed reverse conversion circuit 4,
These circuits operate with the PN signal clock. Also, the clock input terminal of each correlation block B ₁ .about.B _P, the frequency parallel signal clock of (S / P) is input, the correlation block B ₁ .about.B _P For the parallel signal Operates by clock. As described above, each of the correlation processing blocks B _{1 to} B _P operates by a clock having a frequency of 1 / P of the PN signal frequency.

FIG. 2 is a diagram showing a configuration example of the correlation processing blocks B _{1 to} B _P. In this figure, reference numeral 3 denotes the correlation processing block (B _{1 to} B _P ).
_P correlation processing units _{1 to} UP are connected to each of the input terminals IN1 to IN1.
It is provided corresponding to each INP. The outputs from the correlation processing units U _{1 to} U _P are added in a unit addition circuit 10, and the unit addition circuit 10 outputs a t-bit block correlation signal.

As a result, each of the k-bit parallel received signals separated in the signal speed conversion circuit 2 is connected to each of the _P correlation processing units U _{1 to} UP prepared. Each output of the m bits of each correlation unit U ₁ ~U _P are added by the adding circuit 10, the correlation processing blocks B ₁ ~
It is output as a t-bit correlation signal of _BP .

[0021] FIG. 3 is a diagram showing a configuration example of the correlation processing unit U ₁ ~U _P. In this figure, reference numeral 9 denotes the correlation processing units (U _{1 to} U _P ).
Has the same configuration as the DSP shown in FIG. That is, each correlation processing unit 9 reads a k-bit input signal from one of the input terminals IN1 to INP of the correlation processing block by the parallel signal clock and sequentially shifts (2 ⁿ / P) shift registers. , A despreading pattern storage circuit 7 comprising (2 ⁿ / P) stages of buffers for storing correlation processing coefficients as despreading patterns, k-bit outputs of the respective stages of the shift circuit 6 and the inverse (2 ⁿ / P) multiplication circuits 15 for multiplying the k-bit outputs of the respective stages of the diffusion pattern storage circuit 7 and r-bit multiplication result data from the multiplication circuits 15 are added, and m And an addition circuit 14 for outputting bit addition result data. The despreading pattern storage circuit 7 is configured so that the despreading pattern can be supplied and set from outside the correlation processing block.

In such a configuration, the k-bit parallel reception signal from the signal speed conversion circuit 2 is sequentially shifted by the shift circuit 6 at the parallel signal speed (S / P).
Then, the content of the shift circuit 6 is multiplied by the k-bit correlation processing coefficients stored in the despreading pattern storage circuit 7 in the multiplication circuit 15, and the multiplied r-bit signal is added by the addition circuit 14, It is output as an m-bit correlation signal. This correlation signal outputs a value having a sharp peak, for example, when all match, and shows a low value similar to that when no reception signal is received. When a completely uncorrelated signal is received, it always shows a low value.

In the parallel correlation processing circuit of the present invention configured as described above, the received signal at the signal speed S is equal to the A / D signal.
One sample is converted into a k-bit quantized digital signal by the PN signal clock (frequency S) in the conversion circuit 1, and the signal is converted to P parallel output terminals D 1 to DP by the signal speed conversion circuit 2. And are sequentially sorted. Thereby, the parallel output terminals D1 to DP
The parallel reception signal having the signal speed (S / P) is output to the P correlation processing blocks B _{1 to} B _P provided in parallel in the parallel operation processing block 5.

Then, in the P correlation processing units U _{1 to} U _P of the operating frequency (S / P) provided in each of the correlation processing blocks B _{1 to} B _P , the corresponding parallel reception signal is inverted. Generated from a despreading pattern consisting of 2 ⁿ chips required for spreading as described later (2 ⁿ /
Correlation between the despreading pattern P) chips is performed, the correlation output of the correlation processing block is obtained by adding the unit adder circuit 10 the correlation processing result from each correlation processing unit U ₁ ~U _P, One block correlation signal is output from each of the correlation processing blocks B _{1 to} B _P. The output of the block correlation signal is sequentially rearranged in series on the time axis by the signal speed inverse conversion circuit 4, whereby a correlation signal having the same speed as the PN signal speed (S) is output.

Since the parallel operation processing block 5 operates at the parallel signal speed (S / P), the parallel signal processing (S / P)
A high-speed PN signal despreading process (correlation process) can be realized in real time by a DSP operable on a PC.

In the correlation processing blocks B _{1 to} B _P , correlation processing is performed on each despread pattern obtained by shifting the phase of the despread pattern required for despread by one chip. That is, in correlating block B ₁ performs correlation processing using the inverse spreading pattern required for the despreading, using despreading pattern 1 chip shifting the despreading pattern in the correlation processing block B _2, Similarly, the correlation processing block B is used by using the despread pattern shifted one chip at a time.
_{In P} , the correlation processing is performed using the despread pattern obtained by shifting the despread pattern by (P-1) chips.

In each of the correlation processing units U _{1 to} UP provided in each of the correlation processing blocks B _{1 to} B _P , the inverse assigned to the correlation processing block B _i (i = _{1 to P} ) is used. A pattern obtained by shifting the diffusion pattern one chip at a time and selecting every P chip is stored as a despread pattern in the despread pattern storage circuit 7 to perform despread.

The first to P-th correlation processing blocks B ₁ to B ₁
The despreading pattern despreading pattern storing circuit 7 in the first through P-correlation processing unit U ₁ ~U _P will be explained how the stored and distributed are respectively provided in the B _P. FIG. 4 shows the correlation processing blocks B ₁ to B ₁ .
For each _BP , each of the first to P-th correlation processing units U ₁ to U ₁ to
Is a diagram showing an example of the despread pattern stored in the U _P, despreading patterns required to despread (hereinafter,
“Basic despreading pattern” is ΔS [1], S
[2], S [3], ..., S [2 ⁿ -1], S
[2 ⁿ ]}.

As shown in FIG. 4, the despreading pattern storage circuit 7 of the first correlation processing unit U ₁ in the first correlation processing block B ₁ stores the first chip, the (P + 1) th chip of the basic despreading pattern. Chip, the (2P + 1) th chip, and so on, with the first chip at the top.
Chips sampled every time, ｛S [1], S [P + 1],
S [2P + 1],..., S [2 ⁿ −P + 1]} are stored. Therefore, the first correlation processing unit U
₁ , a signal sampled for every P chips of an input received signal and a despread pattern {S [1], S
[P + 1], S [2P + 1],..., S [2 ⁿ −P +
1] A correlation process with｝ is performed.

The despreading pattern storage circuit 7 of the second correlation processing unit U ₂ of the first correlation processing block B ₁ includes:
Chips {S [2], S [P +] selected for each P starting from the second chip S [2] of the basic despreading pattern
, S [2 ⁿ -P + 2]} are stored. Similarly, each correlation despreading pattern storage circuit in the processing unit is stored sampled despread pattern shifted one by one chip for each P is, stored despread pattern of the P correlation processing unit U _P less Circuit 7 has $ S
[P], S [2P],..., S [2 ⁿ ]} are stored.

Thus, each of the correlation processing units U ₁
In ~U _P, the partial correlation of despreading pattern selected for each P chip is taken by shifting each one by one chip the basic despreading pattern, the basic as a result, from the first correlation processing block B ₁ The result of the correlation processing with the despreading pattern is output.

The despreading pattern storage circuit 7 of the first correlation processing unit U ₁ in the second correlation processing block B ₂ stores a subset ｛S of the basic despreading pattern.
[2 ⁿ ], S [P],..., S [2 ⁿ −P]} are stored. This pattern the first despreading pattern stored in the P correlation processing unit U _P in correlating block B ₁ of {S [P], S [ 2P], ···, S
This is a pattern obtained by cyclically shifting [2 ⁿ ]} rightward by one chip. The second second to correlation processing block B ₂
The first P-correlation processing unit U ₂ ~U _P, first to (P-1) of the first correlating block B ₁ correlation process unit U ₁
Each of the subsets stored in U to _(P-1) is sequentially stored.

Therefore, the second correlation processing block B
Each correlation processing unit U ₁ ~U _{P 2,} as a whole, the first correlation process unit U ₁ of the correlation processing block B ₁ ~U
_The despread pattern obtained by cyclically shifting the despread pattern stored in _P by one chip is stored. Thus, in this second correlating block B _2, so that the correlation between the despreading pattern is shifted by one chip phase of the fundamental despreading pattern is performed.

Similarly, the despreading pattern storage circuits 7 of the first to (i-1) th correlation processing units U _{1 to} U _(i-1) of the _i- th correlation processing block B _i respectively include are the (P-i + 2) subsets were ~ 1 chip cyclically shifted by respectively right stored once was the each subset to the P correlation processing unit stores the first correlation processing block B _1, also, the the i-correlating block B _i i to the first P-correlation processing unit U _i ~U _P, said first correlating block B ₁ first to i-correlation processing unit U ₁ ~U
Each subset stored in _{(P-i + 1)} is sequentially stored.

Therefore, the correlation processing units U _{1 to} U _P of the i-th correlation processing block B _i as a whole include the first
The despread pattern obtained by cyclically shifting the despread pattern stored in the correlation processing block B ₁ by (i−1) chips is stored. In the i-th correlation processing block B _i , the basic despread pattern is stored. The phase of (i−
1) Correlation processing with a despread pattern shifted by a chip is performed.

Then, the P-th correlation processing block B _P
In the first to (P-1) th correlation processing units U _{1 to} U
_(P-1), the second in the first correlating block B ₁
~ The P correlation processing unit stored in that each subset is a subset which only one chip cyclic shift to the right respectively are stored, the first P correlation processing unit U _P of the first correlating block B ₁ subset that has been stored in the first correlation processing unit U ₁ is stored. This allows
In the P-th correlation processing block, the basic despreading pattern is correlated with a despreading pattern shifted by (P-1) chips.

As described above, in the parallel correlation processing circuit of the present invention, in the P correlation processing blocks B _{1 to} B _P ,
Correlation processing is performed in parallel with the basic despreading pattern and the despreading pattern whose phase is shifted by one chip at a time.
Further, inside each of the correlation processing blocks B _{1 to} B _P ,
P correlation processing units U each performing partial correlation processing
₁ ~U _P is provided and so as to calculate the partial correlation between the sampled despread patterns selected for each received signal and P were. Therefore, by sequentially sampling and outputting the outputs from the correlation processing blocks B _{1 to BP} by the signal speed inverse conversion circuit 4, it is possible to output a correlation result in real time.

In the above description, the case where the period of the despreading pattern is 2 ⁿ has been described. However, the present invention is not limited to this. When a PN code having a period of 2 ⁿ -1 is used, Dummy data may be inserted at the 2 ^n- th chip S [2 ⁿ ]. Further, the present invention can be applied not only to the case of performing a correlation process with a PN signal having a period of 2 ⁿ or 2 ⁿ -1 but also to a case of performing matching with various data. That is, assuming that the number of data bits to be matched is N and N / P is an integer, the parallel correlation processing circuit of the present invention can be used similarly. Further, also in this case, the dummy bits can be used as in the case described above.

Next, with reference to FIG. 5, the operation of the parallel correlation processing circuit of the present invention configured as described above will be specifically described. The example shown in this figure shows a case where the number of parallels P = 4, and the despreading pattern is ｛a, b, c, d, e, f, g, h, i, j, k. , L,
FIG. 9 is a diagram showing a timing section of each signal in the case of 16 chips of m, n, o, p}.

In FIG. 5, (1) is an example of a PN signal included in the received signal, (2) is an output D1 to D4 of the signal speed conversion circuit 2, (3) is a clock for the PN signal, (4) shows the parallel signal clock.
Also, (5) shows a transition of the contents of the shift circuit 6 of each correlation processing unit U ₁ ~U ₄ in the respective correlating block B ₁ .about.B _4. (6) corresponds to the first to fourth correlation processing blocks U _{1 to} U ₄ in the correlation processing blocks B _{1 to} B ₄ .
5 shows the despreading patterns stored in the respective despreading pattern storage circuits 7, and stores the despreading patterns obtained by shifting the basic despreading patterns by the corresponding amounts as described above.

(7) corresponds to each of the correlation processing blocks B _{1 to} B _4.
(8) shows the correlation processing block B
The outputs of _{1 to} B ₄ are converted into the P
This is an output example sampled at N signal speeds, and a correlation output having the same speed as the input signal speed (PN signal speed) is obtained as shown in the figure.

In the example shown, the output shown by the broken line in the output of the shift circuit of (5) and the fourth output of (6)
The despreading pattern held in the correlation processing block B ₄ matches, and a peak of the correlation appears in the output of the fourth correlation processing block B ₄ as shown in the figure. This is sampled by the signal speed inverse conversion circuit 4 to obtain a real-time correlation output as shown in (8).

As described above, in the despreading pattern storage circuit 7 in the correlation processing unit, a subset of the corresponding despreading patterns is stored. the number of the pattern storage circuit 7) is ^two P. All of these can be prepared in advance and set in each of the despreading pattern storage circuits 7. However, in consideration of changing the PN signal to be received, such a despreading method is used. There is a problem that the storage capacity for storing patterns becomes very large. So, to solve these problems,
An embodiment in which the storage capacity for storing the despreading pattern can be reduced and the despreading pattern can be automatically set in the despreading pattern storage circuit 7 will be described.

FIG. 6 is a diagram for explaining the procedure executed in the parallel correlation processing coefficient generation unit for generating the despread pattern stored in the despread pattern storage circuit 7 in this embodiment. . In this embodiment, the parallel correlation processing coefficient to be assigned to the despreading pattern storage circuit 7 is automatically generated from a basic despreading pattern known in advance by determining the number of parallels P. It is made to be arranged.

[0045] As shown in FIG. 6, based on the determined number of parallel P, the basic code length 2 ⁿ PN code sequence 11 {S
[1], S [2], ..., S [2 ⁿ -1], S
Each code of [2 ⁿ ]} is sampled for each P from the top,
Allocated to group {1}, and shifted one chip further to P
For example, a sample sampled for each chip is assigned to the second group {2}. In this manner, samples are sequentially shifted by one chip for each P chip and assigned as a new despreading pattern. As a result, a spreading code length of (2 ⁿ / P) is obtained. , {P} are generated. Here, S [] indicates each code of the despread pattern 11, and [] indicates the order of the codes in the despread pattern. Specifically, each code S [i] (i = 1,...
, 2 ⁿ ) are arranged in the k-th group (k = 1,..., P) in Table 1.

[Table 1]

Next, for each of the groups from the P-th group {P} to the second group {2}, the codes of each group are sequentially shifted one by one such that the last part returns to the top ( P-1) groups {P + 1} to {2P
-1} is newly generated. Thus, a new (2 ⁿ / P) is added together with the P groups {1} to {P}.
A despreading pattern of a (2 × P−1) group having a spreading code length of can be prepared as a parallel correlation processing coefficient.
These are stored in the parallel correlation coefficient database 12.

Each code of the (2 × P−1) despread patterns obtained in this way is assigned to each group {1}.
{I} ... {P}, {P + 1} ... {j} ... {2 × P-1}
Table 2 shows how they are specifically arranged.

[Table 2]

Next, (2 × P-1) kinds of despread patterns of the parallel correlation coefficient database 12 storing the despread patterns of the groups generated in this manner are shown in Table 3 below. Are selected as shown and sent to the corresponding despreading pattern storage circuit 7.

[Table 3]

That is, the despreading pattern storage circuit of each correlation processing unit of the first correlation processing block has the first
From the correlation processing unit to the P-th correlation processing unit, the parallel correlation processing coefficient database is sequentially allocated from the first column to the P-th column. Next, regarding the despreading pattern storage circuit of each correlation processing unit of the second correlation processing block, first, the (P + 1) th column of the parallel correlation processing coefficient database is inserted into the despreading pattern storage circuit of the first correlation processing unit. The second and subsequent correlation processing units are sequentially allocated from the first column of the parallel correlation processing coefficient database.
Subsequently, regarding the despreading pattern preserving circuit of each correlation processing unit of the third correlation processing block, first, the (P + 1) th column of the parallel correlation coefficient database is assigned to the first correlation processing unit, and the (P + 2) th column is assigned to the (P + 2) th column. 2 is inserted into the despreading pattern storage circuit of the correlation processing unit, and the remaining third
After the correlation processing unit, the insertion sequence is sequentially increased up to the P-th correlation processing block, and the parallel correlation processing coefficient database is allocated, for example, sequentially from the first column of the parallel correlation processing coefficient database.

As described above, simply by specifying the parallel number P,
The setting of the parallel despreading pattern of the despreading pattern storage circuit of the square of the number of parallels (P ² ) can be automated. As a result, not only can the despread patterns corresponding to the despread pattern storage circuits 7 be easily set, but also the despread patterns to be set in the P × P despread pattern storage circuits are stored. Storage capacity can be reduced.

In the above description, the case where the parallel correlation processing circuit of the present invention is applied to the receiver of the spread spectrum communication system has been described. However, the parallel correlation processing circuit of the present invention is not limited to this. However, the present invention can be applied to various uses such as pattern matching in the same manner.

[0052]

As described above, according to the parallel correlation processing circuit of the present invention, a DSP (Digital Signal Processor) having an arithmetic processing speed lower than the signal speed of a pseudo random signal (PN signal) is used. Thus, it is possible to perform a high-speed PN signal correlation process in real time. Also,
Even a general correlation processing circuit can execute correlation processing on high-speed input data in real time.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of an embodiment of a parallel correlation processing circuit according to the present invention;

FIG. 2 is a diagram showing a configuration example of correlation processing blocks B _{1 to BP} in the parallel correlation processing circuit of the present invention.

3 is a diagram showing a configuration example of a correlation processing unit U ₁ ~U _P in the parallel correlation processing circuit of the present invention.

4 is a diagram for explaining an example of a despreading pattern correlation processing unit U within ₁ ~U _P in the parallel correlation processing circuit of the present invention.

FIG. 5 is a diagram for explaining the operation of the parallel correlation processing circuit of the present invention.

FIG. 6 is a diagram for explaining an operation of a parallel correlation processing coefficient generation unit according to the present invention.

FIG. 7 is a diagram illustrating a configuration example of a conventional correlation processing circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 A / D conversion circuit 2 signal speed conversion circuit 3, B _{1 to} B _P correlation processing block 4 signal speed inverse conversion circuit 5 parallel operation processing block 6 shift circuit 7 despreading pattern storage circuit 8 correlation detection circuit 9, U ₁ to _UP correlation processing unit 10 Unit addition circuit 11 Despreading pattern 12 Parallel correlation processing coefficient database 13 Memory circuit 14 Addition circuit 15 Multiplication circuit

Claims (5)

[Claims] 1. A parallel correlation processing circuit in a spread spectrum communication system receiving apparatus for receiving a pseudo random signal having a code length of N, wherein P signals (P is 2 A signal speed conversion unit for sequentially outputting to the output terminals of the above (integer) and converting it into P output signals of the signal speed (S / P); and a parallel operation processing block arranged at the subsequent stage of the signal speed conversion unit. A parallel processing block having P correlation processing blocks provided in parallel, to which P output signals from the signal rate conversion section are input; and P correlation processing blocks of the parallel processing block And a signal rate inverting unit having a function of sequentially selecting correlation outputs respectively output from the P and correlating them in series on the time axis. Each of the P correlation processing blocks has P correlation processing blocks. A unit is provided, and in each of the correlation processing units, a correlation process is performed using a despread pattern of (N / P) chips generated from a despread pattern of N chips required for despreading; In the P correlation processing blocks, correlation processing is performed in parallel on despread patterns having different phases for each chip of the N-chip despread pattern required for the despread. Characteristic parallel correlation processing circuit. 2. An analog-to-digital converter for converting the received signal into a digital signal is provided at a stage preceding the parallel processing block, and the parallel processing block is realized by a digital signal processor. 2. The parallel correlation processing circuit according to claim 1, wherein: 3. Each of the correlation processing blocks adds P correlation processing units provided corresponding to each output terminal of the signal speed conversion unit and output signals of the P correlation processing units. A unit addition unit, wherein each of the correlation processing units converts a signal output from a corresponding output terminal of the signal speed conversion unit into a parallel signal speed (S /
(P) a shift section of (N / P) stages for sequentially reading and shifting, a despread pattern storage section for storing a despread pattern of the spread code length (N / P), and the contents of the shift section and the despread pattern 2. The parallel correlation processing circuit according to claim 1, further comprising a correlation detection unit that outputs a product-sum operation result with the contents of the storage unit as a correlation signal. 4. A first despreading pattern of a code length (N / P) obtained by sampling a despreading pattern of a code length N required for the despreading for every P chips, and the code length N The code length (N / N) obtained by shifting the despread pattern of
P) the second to Pth despreading patterns;
Of the (P + 1) th to (2P-1) th despreading patterns obtained by sequentially shifting each code backward in the despreading pattern and moving the last code to the forefront. A database for processing coefficients is provided, and the despreading pattern storage circuits in the first to Pth correlation processing units of the first correlation processing block store the first to Pth despreading patterns from the parallel correlation processing coefficient database. Read out and set them respectively, and the first to (i-th)
1) The (P + i-1) -th to (P + 1) -th despreading patterns are read out from the parallel correlation processing coefficient database and set in each of the despreading pattern storage circuits in the correlation processing unit. To the despreading pattern storage circuits in the P-th correlation processing unit
2. The method according to claim 1, wherein the first to (P-i + 1) th despreading patterns are read and set.
A parallel correlation processing circuit as described. 5. A speed conversion circuit for sequentially switching input data input continuously to P (P is an integer of 2 or more) output terminals and outputting the data, and connected in parallel to an output of the speed conversion circuit. P correlation processing blocks, and a speed inverse conversion circuit for sequentially selecting and outputting the outputs of the P correlation processing blocks, the input data and an N-bit (N is an integer of 2 or more) pattern A parallel correlation processing circuit for performing the correlation processing, wherein each of the correlation processing blocks is provided corresponding to each of P outputs of the speed conversion circuit, and the output from the speed conversion circuit and the N bits P correlation processing units for performing a correlation process with an N / P bit pattern extracted every P bits, and a unit addition circuit for adding the outputs of the P correlation processing units,
A parallel correlation processing circuit for performing correlation processing on a pattern obtained by shifting the N-bit pattern by one bit in each of the P correlation processing blocks.