JP3922167B2 - Digital matched filter - Google Patents

Description

コードは左側から送られる。これを以下Ｃｉ（ｉ＝0 〜２５５）で表す。
この符号ａとの相関計算を行うには、図２に示すように、２段構成のマッチドフィルタが考えられる。この図２のマッチドフィルタは、８列の３２段シフトレジスタＳＨとＳＨの出力にｘ_i （＝±１）を乗算する乗算回路（ＭＸ）、ＭＸ出力の総和を取る加算回路を構成する６３個の１３〜１７ビットフルアダーＦＡが必要となる。
【０００６】
最終的にＣ_psc との相関計算を行うには、図３に示すように、５１２段（１３列、丸めが可能ならば８〜１２列）のシフトレジスタＳＨと１５個の（１３〜１８ｂｉｔ）フルアダーＦＡが必要である。
そこで、シフトレジスタとアダーを減らすために、シフトレジスタＳＨとアダーＦＡを再利用し、その数を１／ｍに減らすことが考えられている（例えば、特許文献１参照）。
【０００７】
すなわち、１チップ当たり１回のサンプリングを行う場合について説明すると、チップ周期で規格化された時間をｔとしたとき、マッチドフィルタ出力Ｘ_t は下記（１）式で表される。
【０００８】
【数３】

【０００９】
このマッチドフィルタ出力Ｘ_t は、時間Ｔ＝ｔ−１２７のときに、下記（２）式の計算を行ってメモリＭＲに蓄えておき、１２８チップ時間後に残りの下記（３）式の計算を行って、両者を加算器ＡＤで加算することにより得ることができる。
【００１０】
【数４】

【００１１】
この方式では、図４に示すように、シフトレジスタＳＨの段数および加算器ＦＡが分割される数ｍによって１／ｍとなる。図３の方式と比較するとシフトレジスタの段数が減っているので１／２チップ毎に変化していたフリップフロップが減って消費電力が減少する。
他の従来例として、Ａ／Ｄ変換後の時間ｔの受信信号をＲｘ(t) とすると、デジタルマッチドフィルタから出力される相関値Ｘ(t) は下記（４）式で表される。
【００１２】
【数５】

【００１３】
Ｗ−ＣＤＭＡの同期コードＣ_psc は上記のように階層構造となっており、それぞれ１６チップのコードＣ₁ (i) とＣ₂ (i) を用いて、Ｃ(i) ＝Ｃ₁(ｉ mod 16)×Ｃ₂([i/16]) と表され、これを利用すると上記（４）式は
【００１４】
【数６】

【００１５】
と変形することができ、上記（５）式及び（６）式から相関値演算を２段階に分割することが可能となる。
また、ｔ＝ｔ₁ とｔ＝ｔ₁ −１６のときには同じｘ(i) を計算しており、これを再計算するではなく、再利用することで大幅に演算量を削減する。さらに上記（５）式及び（６）式からｘ(i) は１６サイクル毎に用いられ、１６のグループに分けられることからシフトレジスタをメモリに置換することで、実装面積、消費電力の削減を可能としたＷ−ＣＤＭＡ用階層化デジタルマッチドフィルタも提案されている（例えば、非特許文献１参照）
【００１６】
【特許文献１】
米国特許第５９３３４４７号明細書
【非特許文献１】
電子情報通信学会 ２００１年８月２９日発行「2001年電子情報通信学会基礎・境界ソサエティ大会講演論文集 Ａ−１−７
【００１７】
【発明が解決しようとする課題】
しかしながら、上記特許文献１に記載された従来例にあっては、シフトレジスタの段数及び加算器が分割される数ｍによって１／ｍとなり、図３の方式に比較してシフトレジスタの段数が減少して１／２チップ毎に変化していたフリップフロップが減ることにより消費電力が減少するものである。そのかわり先に計算した結果を記憶するメモリが必要となり、シフトレジスタのフリップフロップもメモリと考えると全体としてのメモリ容量が減るわけではない。加算器の桁上がり分も記憶しなければならないのでむしろメモリ容量は増えている。加算器は分割された分だけ素子数は減らすことができるが、１チップ時間内に分割した数ｍだけ繰り返し演算を行わなければならず全体としての計算量は減らない。すなわち、加算器部分での消費電力は必要となる制御回路の分だけ増える傾向となる。
【００１８】
これをまとめると、シフトレジスタはシフトレジスタを一種の記憶回路と考えるとその素子数は減らないが消費電力を減らすことができ、また反対に加算器は素子数を減らすことができるが加算器での消費電力は若干増える傾向となるという未解決の課題がある。
また、上記非特許文献１に記載された従来例にあっては、２５６（５１２）段シフトレジスタでコード長２５６のコードと相関を取るときに比べてＷ−ＣＤＭＡではコードの構造が１６チップずつにまとめられる２層構造を取っているので、１６チップ毎に計算した値は再利用できて素子数が減るとしている。しかしながら、この従来例では、図２で計算した値を図３のシフトレジスタに代えてメモリに記憶させ、これを順次呼出して相関とるようにしているだけで、図２及び図３で相関計算を行う場合に比較して計算量は減少していないという未解決の課題がある。
【００１９】
そこで、本発明は、上記従来例の未解決の課題に着目してなされたものであり、一度計算した値を記憶手段に蓄えて再利用することにより、計算量を減少させると共に、消費電力を減少させるようにしたデジタルマッチドフィルタを提供することを目的としている。
【００２０】
【課題を解決するための手段】
〔発明１〕
上記目的を達成するために、発明１のデジタルマッチドフィルタは、拡散符号Ｃｉ＝｛ｃ_ｉ ｝（ｃ_ｉ ＝±１）によって拡散された信号ｘ_ｔ をチップ当たりｎ回サンプリングして逆拡散するために使用するＣＤＭＡ通信方式用のデジタルマッチドフィルタにおいて、受信信号列から拡散符号を構成する所定ビット数の部分符号を所定数並べた部分符号列の相関演算を行う部分符号列相関演算部と、該部分符号列相関演算部で演算された相関演算結果に基づいて前記部分符号列を整数個ずつ区切った分割符号の相関演算を行う分割符号相関演算部と、該分割符号相関演算部で演算した相関演算結果に基づいてフィルタ出力を算出するフィルタ出力演算部とを備え、前記部分符号列相関演算部は、少なくとも、受信信号列から隣接する信号の合算加算値Ｘ_{ｔ−ｎ−ｉ} ＋Ｘ_ｔ−ｉ を算出する加算手段及び受信信号列から隣接する信号の合算減算値Ｘ_{ｔ−ｎ−ｉ} −Ｘ_ｔ−ｉ を算出する減算手段と、前記加算手段２４の加算結果を順次記憶する第１の記憶手段と、前記減算手段の減算結果を順次記憶する第２の記憶手段と、前記部分符号を構成する所定数のビットを２ビットずつ分割して符号とし、その分割した符号のビットが同符号であるときに前記第１の記憶手段から記憶データを読出し、異符号であるときに前記第２の記憶手段から記憶データを読出し、読み出した記憶データを前記分割した符号の正負に応じて加減算する演算手段とを有することを特徴とする。
【００２１】
このような構成を採用することにより、部分符号列相関演算部の加算手段で受信号のうち隣り合うビットのうち同符号となる符号を算出し、減算手段で隣り合うビットのうち異符号となる符号を算出し、算出した同符号の符号及び異符号の符号を第１の記憶手段及び第２の記憶手段に記憶する。そして、拡散符号構成する部分符号の所定数のビットを２ビットずつ分割して符号とし、その分割した符号の両ビットが同符号であるときに第１の記憶手段から記憶データを読出し、異符号であるときに第２の記憶手段から記憶データを読出し、読み出した記憶データを演算手段で分割した符号の正負に応じて加減算することにより、部分符号相関値を算出する。
〔発明２〕
また、発明２のデジタルマッチドフィルタは、拡散符号Ｃｉ＝｛ｃ_ｉ ｝（ｃ_ｉ ＝±１）によって拡散された信号ｘ_ｔ をチップ当たりｎ回サンプリングして逆拡散するために使用するＣＤＭＡ通信方式用のデジタルマッチドフィルタにおいて、受信信号列から拡散符号を構成する所定ビット数の部分符号を所定数並べた部分符号列の相関演算を行う部分符号列相関演算部と、該部分符号列相関演算部で演算された相関演算結果に基づいて前記部分符号列を所定数で分割した分割符号の相関演算を行う分割符号相関演算部と、該分割符号相関演算部で演算した相関演算結果に基づいてフィルタ出力を算出するフィルタ出力演算部とを備え、前記部分符号列相関演算部は、少なくとも、受信信号列から下式に従って隣接する信号の合算値Ｘ_{ｔ−ｎ−ｉ} を算出する第１の加算手段と、
【００２２】
【数７】

【００２３】
受信信号列から下式に従って隣接する信号の合算値Ｘ_t-i を算出する第２の加算手段と、
【００２４】
【数８】

【００２５】
前記第１の加算器の加算結果と前記第２の加算器の加算結果とを加算して合算加算値Ｘ_{ｔ−ｎ−ｉ} ＋Ｘ_ｔ−ｉ を算出する第３の加算手段と、前記第１の加算器の加算結果から前記第２の加算器の加算結果を減算して合算減算値Ｘ_{ｔ−ｎ−ｉ} −Ｘ_ｔ−ｉ を算出する減算手段と、前記第３の加算手段の加算結果を順次記憶する第１の記憶手段と、前記減算手段の減算結果を順次記憶する第２の記憶手段と、前記部分符号を構成する所定数のビットを２ビットずつ分割して符号とし、その分割した符号のビットが同符号であるときに前記第１の記憶手段から記憶データを読出し、異符号であるときに前記第２の記憶手段から記憶データを読出し、読み出した記憶データを前記分割した符号の正負に応じて加減算する演算手段とを有することを特徴とする。
【００２６】
この構成を採用することにより、前記発明１の作用に加えて、第１の加算器で１チップ当たりのサンプリング数ｎに応じて前記〔数７〕を用いて合算値Ｘ_t-n-i を算出し、第２の加算器で同様にサンプリング数ｎに応じて前記〔数８〕を用いて合算値Ｘ_t-i を算出するので、サンプリング数ｎに応じた合算値Ｘ_t-n-i 及びＸ_t-i を算出することができる。
〔発明３〕
さらに、発明３のデジタルマッチドフィルタは、発明１又は発明２のデジタルマッチドフィルタにおいて、前記第１の記憶手段及び第２の記憶手段は、シフトレジスタで構成されていることを特徴とする。
【００２７】
この構成を採用することにより、シフトレジスタの段数を調整することにより、受信信号のサンプリング毎に加算器又は第３の加算器の加算結果及び減算器の減算結果を、順次シフトレジスタに入力するだけで、部分符号列を構成する同符号及び異符号の２ビット符号を弁別して演算手段での加減算を容易に行うことができる。
〔発明４〕
さらにまた、発明４のデジタルマッチドフィルタは、拡散符号Ｃｉ＝｛ｃ_i ｝（ｃ_i ＝±１）によって拡散された信号ｘ_t をチップ当たりｎ回サンプリングして逆拡散するためのＷ−ＣＤＭＡ通信方式用のデジタルマッチドフィルタにおいて、少なくとも、受信信号列から隣接する信号の合算加算値Ｘ_t-n-i ＋Ｘ_t-i を算出する加算手段及び受信信号列から隣接する信号の合算減算値Ｘ_t-n-i −Ｘ_t-i を算出する減算手段と、前記加算手段の加算結果を記憶する第１の記憶手段と、前記減算器の減算結果を記憶する第２の記憶手段と、前記拡散符号を２ビットずつ分割し、そのビットが同符号であるときに前記第１の記憶手段から記憶データを読出し、異符号であるときに前記第２の記憶手段から記憶データを読出し、読み出した記憶データを拡散符号に応じて加減算する演算手段と、前記演算手段の演算結果を記憶する第３の記憶手段と、該第３の記憶手段の所定位置から順次読み出した演算結果と、演算手段から直接入力される演算結果とに基づいて前記拡散符号を４つずつ区切った第１の分割符号列の部分相関演算を行う第１分割符号相関演算手段と、前記第３の記憶手段の所定位置から順次読み出した演算結果と、演算手段から直接入力される演算結果とに基づいて前記拡散符号を整数個ずつ区切った第２の分割符号列の部分相関演算を行う第２分割符号相関演算手段と、前記第１分割符号相関演算手段及び第２分割符号相関手段の演算結果に基づいてフィルタ出力を演算するフィルタ出力演算手段とを備えたことを特徴としている。
【００２８】
この構成を採用することにより、前述した発明１における演算手段から得られる部分符号列ａに基づいて第１分割符号相関演算手段で、部分符号列ａを所定形式で並べた第１の分割符号列例えば＜ａ，ａ，ａ，−ａ＞との相関演算を行い、同様に第２分割符号相関演算手段で、部分符号列を所定形式で並べた第２の分割符号列例えば＜−ａ，ａ，−ａ，−ａ＞との相関演算を行い、これら相関演算結果をフィルタ出力手段で拡散符号に対応させて演算処理することにより、フィルタ出力を得ることができる。
〔発明５〕
なおさらに、発明５のデジタルマッチドフィルタは、発明４のデジタルマッチドフィルタにおいて、前記フィルタ出力演算手段は、前記第１分割符号相関演算手段の演算結果を第１及び第２の所定値アドレスに書込む第１のメモリと、前記第２分割符号相関演算手段の演算結果を所定アドレスに書込む第２のメモリと、前記第１のメモリの第１及び第２の所定アドレスに記憶された演算結果と前記第２のメモリの所定アドレスに記憶された演算結果と、前記第２の部分相関演算手段の演算結果とに基づいてフィルタ出力を算出するフィルタ出力算出手段とを備えていることを特徴とする。
【００２９】
この構成を採用することにより、第１のメモリに記憶された第１分割符号相関演算手段の演算結果と、第２のメモリに記憶された第２分割符号相関演算手段の演算結果とを再利用することにより、拡散符号との相関値を表すフィルタ出力を算出する。
【００３０】
【発明の実施の形態】
以下、本発明の実施の形態を図面について説明する。
図１は、本発明の一実施形態を示すブロック図であり、図中、１はＷ−ＣＤＭＡ受信機に適用されるデジタルマッチドフィルタである。
このデジタルマッチドフィルタ１は、部分符号列ａの相関計算を行う部分符号列相関演算部２と、この部分符号列相関演算部２で演算された相関演算結果に基づいて分割符号の相関演算を行う分割符号相関演算部３と、この分割符号相関演算部３で演算した相関演算結果に基づいてフィルタ出力Ｘ_t を算出するフィルタ出力演算部４とを備えている。
【００３１】
部分符号列相関演算部２は、Ａ／Ｄ変換後の受信信号を１チップ当たり２サンプリングして時刻ｉの受信信号Ｒｘ(i) が入力される３段のシフトレジスタ２１と、時刻ｉでシフトレジスタ２１の第２段目の受信信号Ｒｘ(i-2) と第３段目の受信信号Ｒｘ(i-3) とを加算して合算値を算出する第１の加算器２２と、時刻ｉの受信信号Ｒｘ(i) とシフトレジスタ２の第１段目の受信信号Ｒｘ(i-1) とを加算して合算値を算出する第２の加算器２３と、第１の加算器２２の加算結果に第２の加算器２３の加算結果を加算して合算加算値を算出する第３の加算器２４と、第１の加算器２２の加算結果から第２の加算器２３の加算結果を減算して合算減算値を算出する減算器２５と、第３の加算器２４の加算結果が入力される第１の記憶手段としての２８段のシフトレジスタ２６と、減算器２５の減算結果が入力される第２の記憶手段としての１２段のシフトレジスタ２７と、減算器２５の減算結果Ｄ(i) と、シフトレジスタ２６の第２８段目、第２４段目、第２０段目及び第１６段目の加算結果Ｃ(i-28)、Ｃ(i-24)、Ｃ(i-20)及びＣ(i-16)と、シフトレジスタ２７の第１２段目、第８段目及び第４段目の減算結果Ｄ(i-12)、Ｄ(i-8) 及びＤ(i-4) とに基づいて下記（７）式の演算を行って部分符号列ａの相関演算を行う演算手段としての演算回路２８とを備えている。
【００３２】

分割符号相関演算部３は、部分符号列相関演算部２で算出された部分符号列ａの相関演算結果を所定アドレス即ち（i mod 96）番地に書込む９６ワードのランダムアクセスメモリ３１と、現在の部分符号列ａの相関演算結果と、ランダムアクセスメモリ３１に記憶されている９６Ｔｓ、６４Ｔｓ及び３２Ｔｓ前の相関演算結果ａ(i-96)、ａ(i-64)、ａ(i-32)とに基づいて下記（８）式の演算を行って分割符号Ａの相関演算を行う第１分割符号演算部３２と、同様に現在の部分符号列ａの相関演算結果と、ランダムアクセスメモリ３１に記憶されている９６Ｔｓ、６４Ｔｓ及び３２Ｔｓ前の相関演算結果ａ(i-96)、ａ(i-64)、ａ(i-32)とに基づいて下記（９）式の演算を行って分割符号Ｂの相関演算を行う第２分割符号演算部３３とを備えている。
【００３３】
Ａ(i) ＝ａ(i-96)＋ａ(i-64)＋ａ(i-32)−ａ(i) ……（８）
Ｂ(i) ＝−ａ(i-96)＋ａ(i-64)−ａ(i-32)−ａ(i) ……（９）
フィルタ出力演算部４は、第１分割符号演算部３２の相関演算結果が(i mod 384) 番地に書込まれる第１のメモリとしての３８４ワードのランダムアクセスメモリ４１と、第２分割符号演算部３３の相関演算結果が(i mod 256) 番地に書込まれる第２のメモリとしての２５６ワードのランダムアクセスメモリ４２と、現在の第２分割符号演算部３３の相関演算結果Ｂ(i) と、ランダムアクセスメモリ４１に記憶されている３８４Ｔｓ前及び１２８Ｔｓ前の相関演算結果Ａ(i mod 384) 及びＡ(i+128 mod 384) と、ランダムアクセスメモリ４２に記憶されている２５６Ｔｓ前の相関演算結果Ｂ(i mod 256) とに基づいて下記（１０）式の演算処理を行ってフィルタ出力Ｘ(i) を算出する出力演算回路４３とで構成されている。
【００３４】

次に、上記実施形態の動作を説明する。
第１同期コードＣ_psc は、前述したように、
Ｃ_psc ＝（１＋ｊ）×＜a,a,a,-a,-a,a,-a,-a,a,a,a,-a,a,-a,a,a ＞
で表され、コードは左側から送られる。
【００３５】
このうち部分符号列＜ａ，ａ，ａ，−ａ，−ａ，ａ，−ａ，−ａ，ａ，ａ，ａ，−ａ，ａ，−ａ，ａ，ａ ＞に注目すると、＜ａ，ａ，ａ，−ａ， ｜−ａ，ａ，−ａ，−ａ， ｜ａ，ａ，ａ，−ａ， ｜ａ，−ａ，ａ，ａ＞のように４つずつ区切って分割符号Ａ，Ｂで表すと、＜Ａ，Ｂ，Ａ，−Ｂ＞となっていることが分かる。但し、Ａ＝＜ａ，ａ，ａ，−ａ＞、Ｂ＝＜−ａ，ａ，−ａ，−ａ＞である。
そのため、部分符号列ａが１６チップで構成されるので、分割符号Ａ及びＢは１２８チップ前に計算した部分相関がそのまま使えて再計算の必要がなく低電力化を図ることができる。
【００３６】
次に、部分符号列ａ＝＜x_1, x_2, x_3, …, ｘ₁₆＞＝＜1,1,1,1,1,1,-1,-1,1,-1,1,-1,1,-1,-1,1 ＞に注目し、＜1,1,｜1,1,｜1,1,｜-1,-1,｜1,-1, ｜1,-1, ｜1,-1, ｜-1,1＞のように２つずつに分けると＜Ｃ，Ｃ，Ｃ，−Ｃ，Ｄ，Ｄ，Ｄ，−Ｄ＞、但しＣ＝＜１，１＞、Ｄ＝＜１，−１＞で表されることが分かる。
【００３７】
ここで、チップ期間をＴｃ、サンプリング期間をＴｓとしたときに、両者の関係が、１チップ期間Ｔｃに２回サンプリングして（サンプリング数ｎ＝２）、１Ｔｃ＝２Ｔｓとなるように設定されている。
そして、Ｃ＝＜１，１＞に対応するＸ_t-n-i ＋Ｘ_t-i とＤ＝＜１，−１＞に対応するＸ_t-n-i −Ｘ_t-i を予め計算し、それを再利用することを考えると、前述した図２の構成を有するデジタルマッチドフィルタに対して加算器及び計算量とも半減させることができる。
【００３８】
ここで、Ｘ_t-n-i は下記（１１）式で算出され、Ｘ_t-i は下記（１２）式で算出される。
【００３９】
【数９】

【００４０】
この実施形態では、サンプリング数ｎが２であるので、時点ｔ−ｉを時点ｉとおくと、Ｘ_i-2 ＝ｘ_i-2 ＋ｘ_i-3 、Ｘ_i ＝ｘ_i ＋ｘ_i-1 となる。このため、３段のシフトレジスタ１１を適用し、このシフトレジスタ１１にＡ／Ｄ変換後の時刻ｉで受信信号Ｒｘ(i) が入力されたときには、第１段目に受信信号Ｒｘ(i-1) 、第２段目に受信信号Ｒｘ(i-2) 、第３段目に受信信号Ｒｘ(i-3) が格納されている。
【００４１】
そして、第１の受信信号加算器２２ではＸ_i-2 に対応するＲｘ(i-3) ＋Ｒｘ(i-2) が計算され、第２の受信信号加算器２３ではＸ_i に対応するＲｘ(i-1) ＋Ｒｘ(i) が計算される。
そして、第３の加算器２４で第１の加算器２２の加算結果Ｒｘ(i-3) ＋Ｒｘ(i-2) に第２の加算器２３の加算結果Ｒｘ(i-1) ＋Ｒｘ(i) を加算して前述した符号Ｃの相関演算値（Ｒｘ(i-3) ＋Ｒｘ(i-2) ＋Ｒｘ(i-1) ＋Ｒｘ(i))を算出すると共に、減算器２５で第１の加算器２２の加算結果Ｒｘ(i-3) ＋Ｒｘ(i-2) から第２の加算器２３の加算結果Ｒｘ(i-1) ＋Ｒｘ(i) を減算して前述した符号Ｄの相関演算値（Ｒｘ(i-3) ＋Ｒｘ(i-2) −Ｒｘ(i-1) −Ｒｘ(i))を算出し、第１の加算器２４の加算結果である相関計算値をシフトレジスタ２１と同時にシフトされるシフトレジスタ２６の第４段目に格納すると共に、減算器２５の減算結果である相関計算値をシフトレジスタ２１と同時にシフトされるシフトレジスタ２７の第４段目に格納する。
【００４２】
その後、シフトレジスタ２６及び２７を１サンプリング周期Ｔｓ毎にシフトし、第３の加算器２４及び減算器２５の相関演算値を順次シフトレジスタ２６及び２７に格納する。
このようにして、順次４サンプリング周期４Ｔｓ毎に、符号Ｃ及びＤの相関演算値がシフトレジスタ２６及び２７の第１段目に格納することを７回繰り返して３２サンプル周期３２Ｔｓとなると、最初の符号Ｃの相関計算値がシフトレジスタ２６の第２８段目にシフトされ、シフトレジスタ２７には５回目に入力された符号Ｄの相関演算値が第１２段目にシフトされる。この段階で、演算回路２８の各入力端子に相関演算値が入力されることになり、この演算回路２８から最初の部分符号列ａ（＝＜Ｃ，Ｃ，Ｃ，−Ｃ，Ｄ，Ｄ，Ｄ，−Ｄ＞）との下記（１３）式で表される部分符号列相関演算値Ｘ_a が算出される。
【００４３】
【数１０】

【００４４】
そして、この部分符号列相関演算値Ｘ_a が部分符号列相関演算部３のランダムアクセスメモリ３１の(i mod 96)番地例えば“０”番地に書込まれる。その後、３２サンプリング周期３２Ｔｓが経過する毎に部分相関演算部３の演算回路２８から順次部分相関値ａ₂ 、ａ₃ が入力され、これらがランダムアクセスメモリ３１の(i+32 mod 96) 番地、(i+64 mod 96) 番地に書込まれ、続いて３２サンプリング周期３２Ｔｓが経過して部分符号列相関演算部３の演算回路２８から部分相関値ａ₄ が出力されると、演算回路３２で分割符号Ａ（＝＜ａ，ａ，ａ，−ａ＞）との下記（１４）式で表される部分相関演算値Ｘ_A が算出されると共に、演算回路３３で分割符号Ｂ（＝＜−ａ，ａ，−ａ，−ａ＞）との下記（１５）式で表される部分相関演算値Ｘ_B が算出される。
【００４５】
【数１１】

【００４６】
このように部分相関演算値Ｘ_B が算出されると、これが演算回路４３に入力されることにより、この演算回路４３で、今入力された部分相関演算値Ｘ_B (i) と、ランダムアクセスメモリ４１から読み出した３８４Ｔｓ前の分割符号Ａの部分相関演算値Ｘ_A (i mod 384) 及び１２８Ｔｓ前の分割符号Ａの部分相関演算値Ｘ_A (i+128 mod 384) と、ランダムアクセスメモリ４２から読み出した２５６Ｔｓ前の分割符号Ｂの部分相関演算値Ｘ_B (i mod 256) とに基づいて下記（１６）式で表される相関値Ｘ_t が算出され、これがデジタルマッチドフィルタ１のフィルタ出力として出力される。
【００４７】
【数１２】

【００４８】
そして、演算回路４３でフィルタ出力が算出されると、分割符号相関演算部３で算出された部分相関演算値Ｘ_A がフィルタ出力演算部４のランダムアクセスメモリ４１の(i mod 384) 番地即ち“０”番地に書込むと共に、部分相関演算値Ｘ_B がランダムアクセスメモリ４２の(i mod 256) 番地に書込み、その後の再利用に備える。
【００４９】
このように、上記実施形態によると、部分符号列相関演算部２によって部分符号列ａの部分相関演算を行い、分割符号列相関演算部３によって分割符号Ａ及びＢの相関演算を行い、フィルタ出力演算部４で、分割符号Ａ及びＢの相関演算結果に基づいてフィルタ出力となる相関値Ｘ_t を算出する。
ここで、部分符号列相関演算部２では、Ａ／Ｄ変換後の受信信号Ｒｘ(i) が入力される３段のシフトレジスタ２１と受信信号加算器２２，２３とで、部分符号列ａ（＝＜ｘ_1,ｘ_2,ｘ_3,…… _,ｘ₁₆＞）の隣り合う符号ｘ_t-n-i 及びｘ_t-i に対応する演算を行い、加算器２４及び減算器２５とでｘ_t-n-i ＋ｘ_t-i 及びｘ_t-n-i −ｘ_t-i の演算を行うことにより、部分符号列ａを構成する符号Ｃ及びＤを計算する。その計算結果をシフトレジスタ２６及び２７に順次格納し、演算回路２８で、シフトレジスタ２６に記憶されている２８Ｔｓ、２４Ｔｓ、２０Ｔｓ及び１６Ｔｓ前の符号Ｃを使用して部分符号列ａ（＝＜Ｃ，Ｃ，Ｃ，−Ｃ，Ｄ，Ｄ，Ｄ，−Ｄ＞）の前半の＜Ｃ，Ｃ，Ｃ，−Ｃ＞との部分相関演算を行うことができ、同様に演算回路２８で、シフトレジスタ２７に記憶されている１２Ｔｓ、８Ｔｓ、４Ｔｓ前の符号Ｄと減算器２５の今回の出力（Ｒｘ(i-3) ＋Ｒｘ(i-2) −Ｒｘ(i-1) −Ｒｘ(i))とに基づいて部分符号列ａの後半の＜Ｄ，Ｄ，Ｄ，−Ｄ＞との部分相関演算を行うことができる。したがって、段数の少ない３つのシフトレジスタ２１，２６，２７と、３つの加算器２２〜２４と、１つの減算器２５と、２つの演算回路２８とで、第１同期コードＣ_psc を構成する部分符号列ａを演算することができ、加算器数を半減できると共に、計算回数も半減することができ、消費電力を大幅に低減することができる。
【００５０】
また、分割符号列相関演算部３では、部分符号列ａに基づいて分割符号Ａ及びＢに応じた相関演算を行い、フィルタ出力演算部４で、分割符号Ａ及びＢの相関演算結果をランダムアクセスメモリ４１及び４２に記憶することにより、記憶された分割符号Ａ及びＢの相関演算結果を使用して演算回路４３でフィルタ出力となる相関値Ｘ_t を算出することができ、少ない回路数及び演算数でフィルタ出力となる相関値Ｘ_t を算出することができる。
【００５１】
因みに、本実施形態の構成によるデジタルマッチドフィルタ１と前述した特許文献１及び非特許文献１に記載された従来例とを実際に組み立て、これらについて消費電力を測定したところ、本実施形態によるデジタルマッチドフィルタ１の消費電力は２．４４ｍＷであったのに対して、特許文献１の従来例の消費電力は５．０９ｍＷ、非特許文献１の従来例の消費電力は３．２４ｍＷとなり、本実施形態の構成によるデジタルマッチドフィルタによって消費電力が大幅に低減されたことが実証された。
【００５２】
なお、上記実施形態においては、Ｗ−ＣＤＭＡでのセルサーチに使用する第１同期コードＰＳＣを例にとって説明したが、これに限定されるものではなく、一般的には、第１同期コードＰＳＣのように都合の良いコードでなく計算結果の再利用ができないのではないかと考えられるが、一般にＣＤＭＡのコードはなるべくランダムになるように作られるため、隣り合うコードの符号が同じ場合と異なる場合の数がそれぞれ半々となる場合が多く、ゆえに上記実施形態のように、Ｘ_t-n-i ＋Ｘ_t-i 及びＸ_t-n-i −Ｘ_t-i の演算を予め行って、それを再利用すれば加算器の数及び計算の回数を半減させることができる。
【００５３】
ここで、１チップ当たりｎ回サンプリングするものとすると、第１の加算器２２では、受信信号列から下記（１７）式の演算を行ってＸ_t-n-i を算出し、第２の加算器２３では、受信信号列から下記（１８）式の演算を行ってｘ_t-i を算出することにより、１チップ当たりのサンプル数ｎに応じたＸ_t-n-i 及びＸ_t-i を正確に算出することができる。
【００５４】
【数１３】

【００５５】
【発明の効果】
以上説明したように、発明１のデジタルマッチドフィルタによれば、受信信号列からＸ_t-n-i ＋Ｘ_t-i を算出する加算手段及びＸ_t-n-i −Ｘ_t-i を算出する減算手段と、前記加算手段の加算結果を記憶する第１の記憶手段と、前記減算器の減算結果を記憶する第２の記憶手段と、前記拡散符号を２ビットずつ分割し、そのビットが同符号であるときに前記第１の記憶手段から記憶データを読出し、異符号であるときに前記第２の記憶手段から記憶データを読出し、読み出した記憶データを拡散符号に応じて加減算する演算手段とを設けるだけで、従来例に比較して拡散符号Ｃｉの部分符号列ａを加算器数及び計算回数を半減させることができ、消費電力を大幅に低減することができるという効果が得られる。
【００５６】
また、発明２のデジタルマッチドフィルタによれば、受信信号列からＸ_t-n-i を算出する第１の加算器と、受信信号列からＸ_t-i を算出する第２の加算器とを有し、第１及び第２の加算器の加算結果を第３の加算器で加算してＸ_t-n-i ＋Ｘ_t-i を算出し、第１の加算器の加算結果から第２の加算器の加算結果を減算器で減算してＸ_t-n-i −Ｘ_t-i を算出するようにしており、発明１のデジタルマッチドフィルタと同様の効果が得られる。
【００５７】
さらに、発明３のデジタルマッチドフィルタによれば、前記第１の記憶手段及び第２の記憶手段を、シフトレジスタで構成したので、シフトレジスタの段数を調整することにより、受信信号のサンプリング毎に加算器又は第３の加算器の加算結果及び減算器の減算結果を、順次シフトレジスタに入力するだけで、部分符号列を構成する同符号及び異符号の２ビット符号を弁別して演算手段での加減算を容易に行うことができ、部分符号列の相関演算を簡易な構成で容易に行うことができるという効果が得られる。
【００５８】
さらにまた、発明４のデジタルマッチドフィルタによれば、発明１又は２のデジタルマッチドフィルタの構成に加えて、部分符号列から拡散符号を４つずつ分割した第１の分割符号及び第２の分割符号の相関演算を行い、その演算結果に基づいてフィルタ出力手段で、相関値でなるフィルタ出力を算出するので、デジタルマッチドフィルタの全体構成を簡易化することができると共に、消費電力を大幅に低減することができるという効果が得られる。
【００５９】
なおさらに、発明５のデジタルマッチドフィルタによれば、フィルタ出力演算手段を、前記第１部分相関演算手段の演算結果を第１及び第２の所定値アドレスに書込む第１のメモリと、前記第２部分相関演算手段の演算結果を所定アドレスに書込む第２のメモリと、前記第１のメモリの第１及び第２の所定アドレスの演算結果と前記第２のメモリの所定アドレスの演算結果と、前記第２の部分相関演算手段の演算結果とに基づいてフィルタ出力を算出するフィルタ出力算出手段とで構成したので、加算器やシフトレジスタを使用することなく、フィルタ手段の構成を簡易化して、消費電力を軽減することができるという効果が得られる。
【図面の簡単な説明】
【図１】 本発明の一実施形態を示すブロック図である。
【図２】 従来例の部分符号列演算回路を示すブロック図である。
【図３】 従来例のデジタルマッチドフィルタを示すブロック図である。
【図４】 特許文献１の方式を適用したデジタルマッチドフィルタを示すブロック図である。
【符号の説明】
１ デジタルマッチドフィルタ、２ 部分符号列相関演算部、３ 分割符号相関演算部、４ フィルタ出力演算部、２１ シフトレジスタ、２２，２３ 第１，第２の加算器、２４ 第３の加算器、２５ 減算器、２６，２７ シフトレジスタ、２８ 演算回路、３１ ランダムアクセスメモリ、３２，３３ 演算回路、４１，４２ ランダムアクセスメモリ、４３ 演算回路[0001]
BACKGROUND OF THE INVENTION
In the present invention, the spread code Ci = {c_i} (C_i= ± 1) spread signal x_tThe present invention relates to a digital matched filter for a CDMA communication system used for sampling and despreading n times per chip.
[0002]
[Prior art]
In general, in a code division multiple access (CDMA) communication system, a correlation between a spread code and a received signal is calculated and demodulated. Therefore, it is necessary to synchronize the received signal with the spreading code string. If a digital matched filter (dmf) is used in this part, high-speed synchronization acquisition is possible, but the number of elements constituting the digital matched filter is large, and it is difficult to put it into practical use from the viewpoint of configuration and power consumption. A CDMA communication system is also used for a mobile phone system in recent years, and in particular, a wideband code division multiple access (W-CDMA) communication system is expected to be widely used as a third-generation mobile phone system.
[0003]
In this W-CDMA communication system, when a terminal is switched on, synchronization acquisition is required to perform a search for which cell the terminal belongs to first. This cell search is performed periodically and always manages the cell in which the current terminal exists. For this reason, it is important to shorten the cell search time by acquiring synchronization at high speed in order to reduce the power consumption of the entire terminal and to increase the standby time. For this reason, the W-CDMA standard recommends the use of a matched filter for correlation with the 256-chip first synchronization code (PSC) for cell search.
[0004]
When the matched filter of the W-CDMA communication system is configured simply, in the case of 2 samples per chip, 8 512-stage shift registers and 511 full adders (8 to 17 bits) of 8 bits or more are required, and the number of elements and power consumption Both become very large.
Here, the code of the first synchronization code PSC has a two-stage configuration and is configured as follows.
[0005]

The code is sent from the left side. This is represented by Ci (i = 0 to 255) below.
In order to perform the correlation calculation with the code a, a matched filter having a two-stage configuration can be considered as shown in FIG. The matched filter shown in FIG. 2 is connected to the outputs of eight columns of 32-stage shift registers SH and SH._iA multiplication circuit (MX) for multiplying (= ± 1) and 63 13 to 17-bit full adders FA constituting an addition circuit for taking the sum of MX outputs are required.
[0006]
Finally C_pscAs shown in FIG. 3, a 512-stage (13 columns, 8-12 columns if rounding is possible) shift register SH and 15 (13-18 bit) full adders FA are required. is there.
Therefore, in order to reduce shift registers and adders, it is considered that the shift registers SH and adders FA are reused and the number thereof is reduced to 1 / m (for example, see Patent Document 1).
[0007]
That is, a case where sampling is performed once per chip will be described. When the time normalized by the chip period is t, the matched filter output X_tIs represented by the following formula (1).
[0008]
[Equation 3]

[0009]
This matched filter output X_tWhen time T = t-127, the following equation (2) is calculated and stored in the memory MR, and after 128 chip time, the remaining equation (3) is calculated, and both are added to the adder. It can be obtained by adding with AD.
[0010]
[Expression 4]

[0011]
In this method, as shown in FIG. 4, the ratio is 1 / m depending on the number of stages of the shift register SH and the number m into which the adder FA is divided. Compared with the method of FIG. 3, since the number of stages of the shift register is reduced, the number of flip-flops changed every 1/2 chip is reduced, and the power consumption is reduced.
As another conventional example, assuming that the received signal at time t after A / D conversion is Rx (t), the correlation value X (t) output from the digital matched filter is expressed by the following equation (4).
[0012]
[Equation 5]

[0013]
W-CDMA synchronization code C_pscHas a hierarchical structure as described above, and each of the 16-chip codes C₁(i) and C₂Using (i), C (i) = C₁(i mod 16) x C₂([i / 16]) and using this, the above equation (4) is
[0014]
[Formula 6]

[0015]
Thus, the correlation value calculation can be divided into two stages from the above equations (5) and (6).
T = t₁And t = t₁When -16, the same x (i) is calculated, and this is not recalculated, but is re-used, and the amount of calculation is greatly reduced. Furthermore, from the above formulas (5) and (6), x (i) is used every 16 cycles and is divided into 16 groups. Therefore, replacing the shift register with a memory reduces the mounting area and power consumption. A layered digital matched filter for W-CDMA that has been made possible has also been proposed (for example, see Non-Patent Document 1).
[0016]
[Patent Document 1]
US Pat. No. 5,933,447
[Non-Patent Document 1]
The Institute of Electronics, Information and Communication Engineers August 29, 2001 "2001 IEICE Basic and Boundary Society Conference Proceedings A-1-7
[0017]
[Problems to be solved by the invention]
However, in the conventional example described in Patent Document 1, the number of shift register stages is reduced to 1 / m depending on the number of shift register stages and the number m divided by the adder. As a result, the number of flip-flops that have changed every 1/2 chip is reduced, thereby reducing the power consumption. Instead, a memory for storing the calculation result is required, and if the flip-flop of the shift register is also considered as a memory, the memory capacity as a whole is not reduced. Since the carry of the adder must also be stored, the memory capacity is rather increased. In the adder, the number of elements can be reduced by the divided number, but it is necessary to repeatedly perform the calculation for the number m divided within one chip time, and the overall calculation amount is not reduced. That is, the power consumption in the adder portion tends to increase by the amount of control circuit required.
[0018]
To summarize, the shift register is considered as a kind of memory circuit, the number of elements is not reduced, but the power consumption can be reduced. On the other hand, the adder can reduce the number of elements. There is an unresolved problem that the power consumption tends to increase slightly.
Further, in the conventional example described in Non-Patent Document 1, the code structure is 16 chips in W-CDMA as compared with the case of correlating with a code having a code length of 256 in a 256 (512) stage shift register. Therefore, the value calculated every 16 chips can be reused and the number of elements is reduced. However, in this conventional example, the value calculated in FIG. 2 is stored in a memory instead of the shift register in FIG. 3, and this is sequentially called to obtain the correlation. There is an unsolved problem that the amount of calculation is not reduced as compared with the case where it is performed.
[0019]
Therefore, the present invention has been made paying attention to the unsolved problems of the above conventional example, and by storing the value once calculated in the storage means and reusing it, the calculation amount is reduced and the power consumption is reduced. An object of the present invention is to provide a digital matched filter that is reduced.
[0020]
[Means for Solving the Problems]
[Invention 1]
In order to achieve the above object, the digital matched filter according to the first aspect of the invention includes a spreading code Ci = {c_i } (C_i = ± 1) spread signal x_t In a digital matched filter for a CDMA communication system used for sampling and despreading n times per chip, correlation of partial code sequences in which a predetermined number of partial codes constituting a spread code are arranged from a received signal sequence A partial code string correlation calculation unit that performs calculation, and a divided code correlation calculation unit that performs correlation calculation of a divided code obtained by dividing the partial code string by an integer number based on a correlation calculation result calculated by the partial code string correlation calculation unit And a filter output calculation unit that calculates a filter output based on the correlation calculation result calculated by the division code correlation calculation unit, and the partial code sequence correlation calculation unit adds at least the adjacent signals from the received signal sequence Addition value X_t-n-i + X_ti Adding means for calculating the sum and subtraction value X of adjacent signals from the received signal sequence X_t-n-i -X_ti Subtracting means for calculating the first subtracting means, first storage means for sequentially storing the addition result of the adding means 24, second storage means for sequentially storing the subtraction result of the subtracting means, and a predetermined number constituting the partial code When the divided bits are the same sign, the stored data is read from the first storage means, and when the divided bits are different signs, the second storage means Computation means for reading stored data and adding / subtracting the read stored data in accordance with the sign of the divided code.
[0021]
By adopting such a configuration, the adder of the partial code string correlation calculation unit calculates the code having the same sign among the adjacent bits of the received signal, and the subtractor obtains a different code among the adjacent bits. The code is calculated, and the calculated code of the same code and the code of the different code are stored in the first storage unit and the second storage unit. Then, a predetermined number of bits of the partial code constituting the spread code is divided into two bits to obtain a code, and when both bits of the divided code have the same code, the stored data is read from the first storage means, The partial code correlation value is calculated by reading the stored data from the second storage means and adding / subtracting the read stored data according to the sign of the code divided by the calculation means.
[Invention 2]
The digital matched filter according to the second aspect of the invention includes a spreading code Ci = {c_i } (C_i = ± 1) spread signal x_t In a digital matched filter for a CDMA communication system used for sampling and despreading n times per chip, correlation of partial code sequences in which a predetermined number of partial codes constituting a spread code are arranged from a received signal sequence A partial code string correlation calculation unit that performs calculation, and a divided code correlation calculation unit that performs correlation calculation of a divided code obtained by dividing the partial code string by a predetermined number based on a correlation calculation result calculated by the partial code string correlation calculation unit And a filter output calculation unit that calculates a filter output based on the correlation calculation result calculated by the division code correlation calculation unit, and the partial code string correlation calculation unit is adjacent to at least the received signal sequence according to the following equation: Total signal value X_t-n-i First addition means for calculating
[0022]
[Expression 7]

[0023]
Total value X of adjacent signals from the received signal sequence according to the following formula_tiA second adding means for calculating
[0024]
[Equation 8]

[0025]
  The addition result of the first adder and the addition result of the second adder are added to obtain a total addition value X_t-n-i + X_ti Subtracting the addition result of the second adder from the addition result of the first adder and a third addition means for calculating_t-n-i -X_ti A subtracting means for calculating the first subtracting means; a first storage means for sequentially storing the addition result of the third adding means; a second storage means for sequentially storing the subtraction result of the subtracting means; and the partial code. A predetermined number of bits are divided into two bits to form a code, and when the divided code bits have the same code, the stored data is read from the first storage means, and when the code has a different code, the second storage And an arithmetic means for reading the stored data from the means and adding / subtracting the read stored data in accordance with the sign of the divided code.
[0026]
By adopting this configuration, in addition to the operation of the first aspect of the invention, the total value X is calculated by using the [Equation 7] according to the sampling number n per chip in the first adder._tniAnd the second adder similarly uses the above [Equation 8] according to the sampling number n to calculate the sum X_tiTherefore, the total value X corresponding to the sampling number n_tniAnd X_tiCan be calculated.
[Invention 3]
Furthermore, the digital matched filter of the invention 3 is the digital matched filter of the invention 1 or 2, wherein the first storage means and the second storage means are constituted by a shift register.
[0027]
By adopting this configuration, by adjusting the number of stages of the shift register, the addition result of the adder or the third adder and the subtraction result of the subtracter are simply input to the shift register every time the received signal is sampled. Thus, 2-bit codes of the same code and different codes constituting the partial code string can be discriminated and addition / subtraction by the calculation means can be easily performed.
[Invention 4]
Furthermore, the digital matched filter of the invention 4 has a spreading code Ci = {c_i} (C_i= ± 1) spread signal x_tIn a digital matched filter for a W-CDMA communication system for sampling and despreading n times per chip, at least a total addition value X of adjacent signals from the received signal sequence_tni+ X_tiAdding means for calculating the sum and subtraction value X of adjacent signals from the received signal sequence X_tni-X_tiSubtracting means for calculating, a first storage means for storing the addition result of the adding means, a second storage means for storing the subtraction result of the subtractor, and dividing the spread code by 2 bits, When the bits have the same sign, the stored data is read from the first storage means, and when the bits have a different sign, the stored data is read from the second storage means, and the read stored data is added or subtracted according to the spreading code. Based on the calculation means, the third storage means for storing the calculation result of the calculation means, the calculation result sequentially read out from the predetermined position of the third storage means, and the calculation result directly inputted from the calculation means From the first divided code correlation calculation means for performing partial correlation calculation of the first divided code string obtained by dividing the spread code by four, the calculation result sequentially read from the predetermined position of the third storage means, and the calculation means Directly A second divided code correlation calculating means for performing a partial correlation calculation of a second divided code string obtained by dividing the spread code by an integer number based on the calculated calculation result; the first divided code correlation calculating means; Filter output calculation means for calculating the filter output based on the calculation result of the divided code correlation means is provided.
[0028]
By adopting this configuration, the first divided code string in which the partial code string a is arranged in a predetermined format by the first divided code correlation calculating means based on the partial code string a obtained from the calculating means in the first aspect described above. For example, correlation calculation with <a, a, a, -a> is performed, and the second divided code sequence in which the partial code sequences are arranged in a predetermined format by the second divided code correlation calculation unit, for example, <-a, a , -A, -a>, and these correlation calculation results are processed by the filter output means in association with the spreading code, thereby obtaining a filter output.
[Invention 5]
Still further, the digital matched filter according to the fifth aspect is the digital matched filter according to the fourth aspect, wherein the filter output calculation means writes the calculation result of the first divided code correlation calculation means to the first and second predetermined value addresses. A first memory; a second memory for writing a calculation result of the second divided code correlation calculation means to a predetermined address; and a calculation result stored in the first and second predetermined addresses of the first memory; Filter output calculation means for calculating a filter output based on a calculation result stored at a predetermined address of the second memory and a calculation result of the second partial correlation calculation means. .
[0029]
By adopting this configuration, the calculation result of the first division code correlation calculation means stored in the first memory and the calculation result of the second division code correlation calculation means stored in the second memory are reused. As a result, a filter output representing a correlation value with the spread code is calculated.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of the present invention, in which 1 is a digital matched filter applied to a W-CDMA receiver.
The digital matched filter 1 performs a correlation calculation of a divided code based on a partial code string correlation calculation unit 2 that performs correlation calculation of the partial code string a and a correlation calculation result calculated by the partial code string correlation calculation unit 2. The division code correlation calculation unit 3 and the filter output X based on the correlation calculation result calculated by the division code correlation calculation unit 3_tAnd a filter output calculation unit 4 for calculating
[0031]
The partial code string correlation calculation unit 2 shifts the received signal after A / D conversion into a three-stage shift register 21 to which the received signal Rx (i) at time i is input by sampling twice per chip, and at time i A first adder 22 that adds the second-stage received signal Rx (i-2) and the third-stage received signal Rx (i-3) of the register 21 to calculate a sum value; and a time i Received signal Rx (i) and the first-stage received signal Rx (i−1) of the shift register 2 are added together to calculate a sum value, The addition result of the second adder 23 is calculated from the addition result of the third adder 24 and the addition result of the first adder 22 by adding the addition result of the second adder 23 to the addition result. A subtracter 25 that calculates a subtracted value by subtraction, and a 28-stage system as a first storage means to which the addition result of the third adder 24 is input. Register 26, a 12-stage shift register 27 as a second storage means to which the subtraction result of the subtractor 25 is inputted, a subtraction result D (i) of the subtractor 25, the 28th stage of the shift register 26, The addition results C (i-28), C (i-24), C (i-20) and C (i-16) of the 24th stage, the 20th stage and the 16th stage, and the shift register 27 The following equation (7) is calculated based on the subtraction results D (i-12), D (i-8) and D (i-4) in the 12th, 8th and 4th stages. And an arithmetic circuit 28 as arithmetic means for performing a correlation operation on the partial code string a.
[0032]

The divided code correlation calculation unit 3 is a 96-word random access memory 31 for writing the correlation calculation result of the partial code sequence a calculated by the partial code sequence correlation calculation unit 2 at a predetermined address, that is, (i mod 96), And the correlation calculation results a (i-96), a (i-64), and a (i-32) before 96Ts, 64Ts, and 32Ts stored in the random access memory 31. Based on the above, the first divided code calculation unit 32 that performs the calculation of the following equation (8) to perform the correlation calculation of the divided code A, the correlation calculation result of the current partial code string a, and the random access memory 31 Based on the stored correlation calculation results a (i-96), a (i-64), and a (i-32) before 96Ts, 64Ts, and 32Ts, the following equation (9) is calculated to divide the code And a second divided code calculation unit 33 that performs B correlation calculation.
[0033]
A (i) = a (i-96) + a (i-64) + a (i-32) -a (i) (8)
B (i) =-a (i-96) + a (i-64) -a (i-32) -a (i) (9)
The filter output calculation unit 4 includes a 384-word random access memory 41 as a first memory in which the correlation calculation result of the first division code calculation unit 32 is written at the address (i mod 384), and a second division code calculation unit 33 random calculation memory 42 as a second memory in which the correlation calculation result of 33 is written at the address (i mod 256), the correlation calculation result B (i) of the current second divided code calculation unit 33, The correlation calculation results A (i mod 384) and A (i + 128 mod 384) before 384 Ts and 128 Ts stored in the random access memory 41 and the correlation calculation result before 256 Ts stored in the random access memory 42 The output calculation circuit 43 calculates the filter output X (i) by performing the calculation process of the following equation (10) based on B (i mod 256).
[0034]

Next, the operation of the above embodiment will be described.
First synchronization code C_pscAs mentioned above,
C_psc= (1 + j) × <a, a, a, -a, -a, a, -a, -a, a, a, a, -a, a, -a, a, a>
The code is sent from the left side.
[0035]
  Of these, the partial code string <a, a, a, -a, -a, a, -a, -a, a, a, a, -a, a, -a, a, a> , A, a, -a, | -a, a, -a, -a, | a, a, a, -a, | a, -a, a, a> When represented by A and B, it can be seen that <A, B, A, -B>. However, A = <a, a, a, −a> and B = <− a, a, −a, −a>.
  For this reason, since the partial code string a is composed of 16 chips, the divided codes A and B can use the partial correlation calculated before 128 chips as they are, and need not be recalculated, thereby reducing power consumption.
[0036]
Next, the partial code string a = <x_1,x_2,x_3,…, X₁₆> = <1,1,1,1,1,1, -1, -1,1, -1,1, -1,1, -1, -1,1> | 1,1, | 1,1, | -1, -1, | 1, -1, | 1, -1, | 1, -1, | -1,1> It can be seen that <C, C, C, -C, D, D, D, -D>, where C = <1,1> and D = <1, -1>.
[0037]
Here, when the chip period is Tc and the sampling period is Ts, the relationship between the two is set such that the sampling is performed twice in one chip period Tc (sampling number n = 2) and 1Tc = 2Ts. Yes.
And X corresponding to C = <1,1>_tni+ X_tiAnd X corresponding to D = <1, -1>_tni-X_ti2 and the amount of calculation can be halved with respect to the digital matched filter having the configuration of FIG. 2 described above.
[0038]
Where X_tniIs calculated by the following equation (11), and X_tiIs calculated by the following equation (12).
[0039]
[Equation 9]

[0040]
In this embodiment, since the sampling number n is 2, if the time point ti is set to the time point i, X_i-2= X_i-2+ X_i-3, X_i= X_i+ X_i-1It becomes. Therefore, when the three-stage shift register 11 is applied and the reception signal Rx (i) is input to the shift register 11 at time i after A / D conversion, the reception signal Rx (i− 1) The received signal Rx (i-2) is stored in the second stage, and the received signal Rx (i-3) is stored in the third stage.
[0041]
In the first received signal adder 22, X_i-2Rx (i−3) + Rx (i−2) corresponding to the second received signal adder 23 is calculated._iRx (i-1) + Rx (i) corresponding to is calculated.
Then, in the third adder 24, the addition result Rx (i-1) + Rx (i) of the second adder 23 is added to the addition result Rx (i-3) + Rx (i-2) of the first adder 22. Is added to calculate the correlation calculation value (Rx (i-3) + Rx (i-2) + Rx (i-1) + Rx (i)) of the above-mentioned code C, and the subtracter 25 uses the first adder. The addition result Rx (i-1) + Rx (i) of the second adder 23 is subtracted from the addition result Rx (i-3) + Rx (i-2) of 22, and the correlation operation value (Rx (i-3) + Rx (i-2) −Rx (i−1) −Rx (i)) is calculated, and the correlation calculation value, which is the addition result of the first adder 24, is shifted simultaneously with the shift register 21. And the correlation calculation value as the subtraction result of the subtracter 25 is stored in the fourth stage of the shift register 27 that is shifted simultaneously with the shift register 21.
[0042]
Thereafter, the shift registers 26 and 27 are shifted every sampling period Ts, and the correlation calculation values of the third adder 24 and the subtracter 25 are sequentially stored in the shift registers 26 and 27.
In this manner, when the correlation calculation values of the codes C and D are sequentially stored in the first stage of the shift registers 26 and 27 every 4 sampling periods 4Ts, when the 32 sample periods 32Ts are obtained, The correlation calculation value of the code C is shifted to the 28th stage of the shift register 26, and the correlation calculation value of the code D inputted to the shift register 27 for the fifth time is shifted to the 12th stage. At this stage, a correlation calculation value is input to each input terminal of the arithmetic circuit 28, and the first partial code string a (= <C, C, C, −C, D, D, D, −D>) and a partial code string correlation calculation value X represented by the following equation (13):_aIs calculated.
[0043]
[Expression 10]

[0044]
And this partial code string correlation calculation value X_aIs written in the address (i mod 96) of the random access memory 31 of the partial code string correlation calculation unit 3, for example, “0”. Thereafter, each time the 32 sampling periods 32Ts elapse, the partial correlation value a₂, A_ThreeAre written in the (i + 32 mod 96) address and (i + 64 mod 96) address of the random access memory 31, and then the partial sampling sequence correlation unit 3 passes after 32 sampling periods 32Ts. Of the partial correlation value a_FourIs output by the arithmetic circuit 32 with the divided code A (= <a, a, a, −a>) and the partial correlation calculation value X expressed by the following equation (14):_AIs calculated, and the partial correlation calculation value X represented by the following equation (15) with the divided code B (= <− a, a, −a, −a>) is calculated by the calculation circuit 33._BIs calculated.
[0045]
## EQU11 ##

[0046]
Thus, the partial correlation calculation value X_BIs input to the arithmetic circuit 43, and the arithmetic circuit 43 then inputs the partial correlation calculation value X that has just been input._B(i) and the partial correlation calculation value X of the division code A before 384 Ts read from the random access memory 41_A(i mod 384) and the partial correlation calculation value X of the divided code A before 128 Ts_A(i + 128 mod 384) and the partial correlation calculation value X of the divided code B before 256 Ts read from the random access memory 42_BCorrelation value X expressed by the following equation (16) based on (i mod 256)_tIs calculated and output as the filter output of the digital matched filter 1.
[0047]
[Expression 12]

[0048]
When the filter output is calculated by the calculation circuit 43, the partial correlation calculation value X calculated by the divided code correlation calculation unit 3 is obtained._AIs written to the address (i mod 384) of the random access memory 41 of the filter output calculation unit 4, that is, “0”, and the partial correlation calculation value X_BIs written in the address (i mod 256) of the random access memory 42 and is prepared for subsequent reuse.
[0049]
Thus, according to the above embodiment, the partial code sequence correlation calculation unit 2 performs partial correlation calculation of the partial code sequence a, the divided code sequence correlation calculation unit 3 performs correlation calculation of the divided codes A and B, and outputs the filter. In the calculation unit 4, the correlation value X that becomes the filter output based on the correlation calculation result of the divided codes A and B_tIs calculated.
Here, in the partial code string correlation calculation unit 2, the partial code string a (() includes the three-stage shift register 21 to which the received signal Rx (i) after A / D conversion is input and the received signal adders 22 and 23. = <X_1,x_2,x_3,......_,x₁₆>) Adjacent code x_tniAnd x_tiAnd an adder 24 and a subtracter 25_tni+ X_tiAnd x_tni-X_tiBy calculating the above, the codes C and D constituting the partial code string a are calculated. The calculation results are sequentially stored in the shift registers 26 and 27, and the arithmetic circuit 28 uses the code C 28Ts, 24Ts, 20Ts, and 16Ts before stored in the shift register 26 to generate the partial code string a (= <C , C, C, -C, D, D, D, -D>) can be partially correlated with the first half of <C, C, C, -C>. 12Ts, 8Ts, 4Ts previous sign D stored in the register 27 and the current output of the subtractor 25 (Rx (i-3) + Rx (i-2) -Rx (i-1) -Rx (i)) Based on the above, it is possible to perform a partial correlation calculation with <D, D, D, -D> in the latter half of the partial code string a. Therefore, the first synchronization code C is composed of the three shift registers 21, 26, 27 having a small number of stages, the three adders 22 to 24, the one subtracter 25, and the two arithmetic circuits 28._pscCan be calculated, the number of adders can be halved, the number of calculations can be halved, and the power consumption can be greatly reduced.
[0050]
The divided code string correlation calculation unit 3 performs a correlation calculation corresponding to the divided codes A and B based on the partial code string a, and the filter output calculation unit 4 randomly accesses the correlation calculation results of the divided codes A and B. By storing in the memories 41 and 42, the correlation value X that is the filter output in the arithmetic circuit 43 using the stored correlation calculation results of the divided codes A and B is stored._tThe correlation value X that becomes a filter output with a small number of circuits and operations can be calculated._tCan be calculated.
[0051]
Incidentally, when the digital matched filter 1 having the configuration of the present embodiment and the conventional examples described in Patent Document 1 and Non-Patent Document 1 described above are actually assembled and the power consumption is measured for these, the digital matched filter according to the present embodiment is obtained. While the power consumption of the filter 1 is 2.44 mW, the power consumption of the conventional example of Patent Document 1 is 5.09 mW, and the power consumption of the conventional example of Non-Patent Document 1 is 3.24 mW. It was proved that the power consumption was greatly reduced by the digital matched filter with the configuration.
[0052]
In the above embodiment, the first synchronization code PSC used for cell search in W-CDMA has been described as an example. However, the present invention is not limited to this, and in general, the first synchronization code PSC It is thought that the calculation result cannot be reused because it is not a convenient code, but in general, since the CDMA code is made as random as possible, the code of the adjacent code is different from the same case In many cases, the number is halved, and therefore, as in the above embodiment, X_tni+ X_tiAnd X_tni-X_tiIf the above calculation is performed in advance and reused, the number of adders and the number of calculations can be halved.
[0053]
Here, assuming that sampling is performed n times per chip, the first adder 22 performs an operation of the following equation (17) from the received signal sequence to obtain X_tniIn the second adder 23, the following equation (18) is calculated from the received signal sequence to obtain x_tiBy calculating X according to the number of samples n per chip._tniAnd X_tiCan be calculated accurately.
[0054]
[Formula 13]

[0055]
【The invention's effect】
As described above, according to the digital matched filter of aspect 1, X_tni+ X_tiAdding means for calculating X and X_tni-X_tiSubtracting means for calculating, a first storage means for storing the addition result of the adding means, a second storage means for storing the subtraction result of the subtractor, and dividing the spread code by 2 bits, When the bits have the same sign, the stored data is read from the first storage means, and when the bits have a different sign, the stored data is read from the second storage means, and the read stored data is added or subtracted according to the spreading code. Only by providing the calculation means, it is possible to halve the number of adders and the number of calculations of the partial code string a of the spread code Ci as compared with the conventional example, and the effect that the power consumption can be greatly reduced is obtained. It is done.
[0056]
Further, according to the digital matched filter of the second aspect, X_tniAnd a first adder for calculating X from the received signal sequence_tiAnd a second adder that calculates the sum of the addition results of the first and second adders by a third adder._tni+ X_tiAnd subtracting the addition result of the second adder from the addition result of the first adder by the subtractor X_tni-X_tiThus, the same effect as that of the digital matched filter of the first aspect can be obtained.
[0057]
Further, according to the digital matched filter of the invention 3, since the first storage means and the second storage means are constituted by shift registers, the number of stages of the shift registers is adjusted so that the addition is performed every time the received signal is sampled. By simply inputting the addition result of the adder or the third adder and the subtraction result of the subtracter sequentially to the shift register, the 2-bit code of the same code and the different code constituting the partial code string is discriminated and the addition / subtraction in the arithmetic means is performed. Thus, it is possible to easily perform the correlation calculation of the partial code string with a simple configuration.
[0058]
Furthermore, according to the digital matched filter of the invention 4, in addition to the configuration of the digital matched filter of the invention 1 or 2, the first divided code and the second divided code obtained by dividing the spreading code by four from the partial code string Since the filter output comprising the correlation value is calculated by the filter output unit based on the calculation result, the overall configuration of the digital matched filter can be simplified and the power consumption can be greatly reduced. The effect that it can be obtained.
[0059]
Still further, according to the digital matched filter of the fifth aspect of the invention, the filter output calculation means includes a first memory for writing the calculation results of the first partial correlation calculation means to first and second predetermined value addresses, and the first A second memory for writing a calculation result of the two-part correlation calculation means to a predetermined address; a calculation result of the first and second predetermined addresses of the first memory; and a calculation result of the predetermined address of the second memory; Since the filter output calculating means calculates the filter output based on the calculation result of the second partial correlation calculating means, the structure of the filter means can be simplified without using an adder or a shift register. The effect that power consumption can be reduced is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a conventional partial code string arithmetic circuit.
FIG. 3 is a block diagram illustrating a conventional digital matched filter.
FIG. 4 is a block diagram showing a digital matched filter to which the method of Patent Document 1 is applied.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Digital matched filter, 2 Partial code sequence correlation calculating part, 3 division | segmentation code correlation calculating part, 4 Filter output calculating part, 21 Shift register, 22, 23 1st, 2nd adder, 24 3rd adder, 25 Subtractor, 26, 27 Shift register, 28 arithmetic circuit, 31 random access memory, 32, 33 arithmetic circuit, 41, 42 random access memory, 43 arithmetic circuit

Claims (5)

Spread code Ci = {c _i } (C _i = ± 1) spread signal x _t In a digital matched filter for a CDMA communication system used to sample and despread n times per chip,
A partial code sequence correlation calculation unit for performing a correlation calculation of a partial code sequence in which a predetermined number of partial codes having a predetermined number of bits constituting a spread code are arranged from a received signal sequence, and a correlation calculation result calculated by the partial code sequence correlation calculation unit A divided code correlation calculation unit for performing a correlation calculation of divided codes obtained by dividing the partial code string by integers based on the filter, and a filter output calculation for calculating a filter output based on a correlation calculation result calculated by the divided code correlation calculation unit With
The partial code string correlation calculation unit at least adds a sum X _{xn−i of} adjacent signals from the received signal string. + X _ti And a subtracting value X _{t−n−i of} adjacent signals from the received signal sequence -X _ti Subtracting means for calculating the subtraction means, first storage means for sequentially storing the addition results of the adding means 24, second storage means for sequentially storing the subtraction results of the subtraction means, and a predetermined number constituting the partial code Is divided into two bits to form a code, and when the divided code bits have the same sign, the stored data is read from the first storage means, and when the bits have different signs, the second storage means A digital matched filter, comprising: an operation means for reading stored data and adding / subtracting the read stored data according to the sign of the divided code. Spread code Ci = {c_i } (C_i = ± 1) spread signal x_t In a digital matched filter for a CDMA communication system used to sample and despread n times per chip,
  A partial code sequence correlation calculation unit for performing a correlation calculation of a partial code sequence in which a predetermined number of partial codes having a predetermined number of bits constituting a spread code are arranged from a received signal sequence, and a correlation calculation result calculated by the partial code sequence correlation calculation unit A divided code correlation calculation unit for performing a correlation calculation of a divided code obtained by dividing the partial code string by a predetermined number based on the filter, and a filter output calculation for calculating a filter output based on a correlation calculation result calculated by the divided code correlation calculation unit And the partial code string correlation calculating section includes at least a sum value X of adjacent signals from the received signal string according to the following equation:_t-n-i First addition means for calculating

  Total value X of adjacent signals from the received signal sequence according to the following formula_ti A second adding means for calculating

  The addition result of the first adder and the addition result of the second adder are added to obtain a total addition value X_t-n-i + X_ti A third adding means for calculating
  Subtracting the addition result of the second adder from the addition result of the first adder and adding the subtraction value X_t-n-i -X_ti Subtracting means for calculating
  First storage means for sequentially storing the addition results of the third addition means;
  Second storage means for sequentially storing the subtraction results of the subtraction means;
  When a predetermined number of bits constituting the partial code are divided into two bits to obtain a code, and when the divided code bits have the same code, the stored data is read from the first storage means and the code has a different code The digital matched filter further comprises arithmetic means for reading stored data from the second storage means and adding / subtracting the read stored data according to the sign of the divided code. 3. The digital matched filter according to claim 1, wherein the first storage unit and the second storage unit include a shift register. Spread code Ci = {c _i } (C _i = ± 1) spread signal x _t In a digital matched filter for a CDMA communication system used to sample and despread n times per chip,
At least the total addition value X _{t−n−i of} adjacent signals from the received signal sequence + X _ti And a subtracting value X _{t−n−i of} adjacent signals from the received signal sequence -X _ti Subtracting means for calculating the first subtracting means; first storage means for storing the addition result of the adding means; second storage means for storing the subtraction result of the subtractor; When the divided code bits have the same sign, the stored data is read from the first storage means, and when the divided code bits have the same sign, the stored data is read from the second storage means. From the calculation means for adding / subtracting according to the sign of the divided code, the third storage means for storing the calculation result of the calculation means, the calculation result sequentially read from the predetermined position of the third storage means, and the calculation means First division code correlation calculation means for performing correlation calculation of a first divided code string obtained by dividing the spreading code by an integer number based on the calculation result directly input, and sequentially from a predetermined position of the third storage means Read Second divided code correlation calculating means for performing a correlation calculation of a second divided code string obtained by dividing the spreading code by an integer number based on the calculated result and a calculation result directly input from the calculating means, and the first A digital matched filter comprising: filter output calculation means for calculating a filter output based on the calculation results of the divided code correlation calculating means and the second divided code correlation means. The filter output calculation means has a first memory for writing the calculation result of the first division code correlation calculation means to first and second predetermined value addresses, and a calculation result of the second division code correlation calculation means. A second memory to be written to the address, a calculation result stored in the first and second predetermined addresses of the first memory, a calculation result stored in the predetermined address of the second memory, and the second 5. The digital matched filter according to claim 4, further comprising: filter output calculation means for calculating a filter output based on a calculation result of the divided code correlation calculation means.

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