JPH10307982A5 - - Google Patents

Info

Publication number
JPH10307982A5
JPH10307982A5 JP1998066438A JP6643898A JPH10307982A5 JP H10307982 A5 JPH10307982 A5 JP H10307982A5 JP 1998066438 A JP1998066438 A JP 1998066438A JP 6643898 A JP6643898 A JP 6643898A JP H10307982 A5 JPH10307982 A5 JP H10307982A5
Authority
JP
Japan
Prior art keywords
test
data
context data
storing
context
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998066438A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10307982A (ja
Filing date
Publication date
Priority claimed from US08/821,972 external-priority patent/US5953684A/en
Application filed filed Critical
Publication of JPH10307982A publication Critical patent/JPH10307982A/ja
Publication of JPH10307982A5 publication Critical patent/JPH10307982A5/ja
Pending legal-status Critical Current

Links

JP10066438A 1997-03-17 1998-03-17 テスト環境情報の統合記憶方法及び装置 Pending JPH10307982A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US821,972 1997-03-17
US08/821,972 US5953684A (en) 1997-03-17 1997-03-17 Methods and apparatus for integrated storage of test environment context information

Publications (2)

Publication Number Publication Date
JPH10307982A JPH10307982A (ja) 1998-11-17
JPH10307982A5 true JPH10307982A5 (enExample) 2005-06-02

Family

ID=25234750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10066438A Pending JPH10307982A (ja) 1997-03-17 1998-03-17 テスト環境情報の統合記憶方法及び装置

Country Status (2)

Country Link
US (1) US5953684A (enExample)
JP (1) JPH10307982A (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19839121A1 (de) * 1998-08-27 2000-03-02 Rohde & Schwarz Anordnung zum kontinuierlichen und unterbrechungsfreien Einlesen einer großen Datenmenge eines elektronischen Meßgerätes in einen Speicher
US7296060B2 (en) * 1998-12-24 2007-11-13 Intel Corporation System and method for automatically identifying and attaching related documents
JP3522662B2 (ja) * 1999-07-23 2004-04-26 シャープ株式会社 半導体集積回路の検査装置及びその検査方法並びにその検査プログラムを記録した記憶媒体
US7409531B1 (en) * 1999-10-29 2008-08-05 Hewlett-Packard Development Company, L.P. Integrated micro-controller and programmable device
US6904389B2 (en) 2001-03-06 2005-06-07 Hewlett-Packard Development Company, L.P. Remote computer testing
US7401272B1 (en) * 2001-03-09 2008-07-15 Pmc-Sierra, Inc. Apparatus and method for high speed sampling or testing of data signals using automated testing equipment
US6975955B1 (en) 2001-07-26 2005-12-13 Ciena Corporation Method and system for managing manufacturing test stations
US20060167947A1 (en) * 2003-03-01 2006-07-27 Dunkle Mark V Communications interface database for electronic diagnostic apparatus
US20050149569A1 (en) * 2003-12-03 2005-07-07 Forest Laboratories, Inc. Electronic lab notebook
US7158907B1 (en) * 2004-08-04 2007-01-02 Spirent Communications Systems and methods for configuring a test setup
WO2006120853A1 (ja) * 2005-05-09 2006-11-16 Advantest Corporation 試験装置、試験方法、および半導体デバイス
US7555639B2 (en) * 2006-01-31 2009-06-30 Verigy (Singapore) Pte. Ltd. Method for configuring a data formatting process using configuration values of a highest priority for each of a number of configuration keys storing in several configuration layers
EP3686609A1 (en) * 2019-01-25 2020-07-29 Rohde & Schwarz GmbH & Co. KG Measurement system and method for recording context information of a measurement

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5771240A (en) * 1996-11-14 1998-06-23 Hewlett-Packard Company Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin
US5751735A (en) * 1996-11-14 1998-05-12 Hewlett-Packard Company Integrated debug trigger method and apparatus for an integrated circuit

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