JPH10303328A - Manufacture of semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of improper connection and circuit formation caused by adhesion of solder resist or prepreg resin. SOLUTION: A metallic layer 2 of a first substrate 4 is first subjected to a patterning process to form a circuit 5. Next, a protective film 6 is formed on the circuit 5. Thereafter, the first substrate 4 is coated with solder resist 7 and then the protective film 6 is removed from the circuit 5. Gold plating is carried out over the circuit 5 to form a gold plated layer 8 thereon. Next, the protective film 6 is formed on the gold plated layer 8 of the circuit 5 and on a metallic layer 3 of the first substrate 4. A window hole is made in a second substrate, and a protective film is formed on a metallic layer of the second substrate. The second substrate is next bonded to the first substrate 1 through a prepreg. Next, the gold plated layer 8 of the circuit 5 as well as the respective protective films 6 of the metallic layer 3 of the first substrate 4 and the metallic layer of the second substrate are removed. Thereafter, the metallic layer 3 of the first substrate 4 and the metallic layer of the second substrate are subjected to a patterning process to form the circuit part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package used for manufacturing a semiconductor device by mounting a semiconductor element.

[0002]

2. Description of the Related Art FIGS. 6 to 8 show an example of a conventional method for manufacturing a semiconductor package. First, a metal layer 2 is formed on both sides of an insulating plate 1 such as a copper-clad laminate as shown in FIG. 3A, a window hole 20 is formed at a predetermined position on the first substrate 4 as shown in FIG. 6B, and a via hole (not shown) is formed as necessary. Processing). Next, metal plating such as copper plating is applied to the entire surface of the first substrate 4, and metal plating 21 is formed on the surfaces of the metal layers 2 and 3, the inner periphery of the window hole 20, and the inner periphery of the via hole. One substrate 4
The metal layer 2 on one surface (upper surface) is patterned to form a circuit portion 5 on the periphery of the window hole 20 as shown in FIG.

[0006] Next, as shown in FIG. 6 (d), a solder resist 7 is applied to a predetermined portion of one surface (upper surface) of the first substrate 4 except for the circuit portion 5, and the other surface of the first substrate 4 is The gold-plated dry film 22 is adhered to the entire surface (lower surface), the first substrate 4 is plated with gold, and then the gold-plated dry film 22 is peeled off. As shown in FIG. 6E, the gold plating 8 is not covered with the solder resist 7 or the gold-plated dry film 22 and is exposed.
And the surface of the metal plating 21 on the inner periphery of the window hole 20.

On the other hand, a second substrate 11 formed by providing a metal layer 10 on one surface (upper surface) of an insulating plate 9 such as a copper-clad laminate as shown in FIG. As shown in FIG. 7B, a window hole 12 is formed at a predetermined position, and a via hole (not shown) is formed and copper plating is performed as necessary. The window hole 12 is formed to have a size larger than the window hole 20 of the first substrate 4. Further, using a prepreg 13 as shown in FIG.
A window hole 23 having the same size as that of the above or a size larger by about 0.1 to 0.5 mm is machined as shown in FIG.

[0005] The prepreg 13 is placed on the first substrate 4.
The second substrate 11 is stacked on the first substrate 4 via the adhesive layer 13a of the prepreg 13 as shown in FIG.
Are laminated and formed. Next, the other surface (lower surface) of the first substrate 4
The metal layers 3 and the metal layer 10 on one surface (upper surface) of the second substrate 11 are patterned to form circuit portions 14 and 15 as shown in FIG. Thereafter, through-hole processing and copper plating processing are performed (both not shown), and the other surface (lower surface) of the first substrate 4 and one of the second substrate 11 as shown in FIG. Circuit on the surface (upper surface) of
A solder resist 7 is applied to portions other than 15, and gold plating 8 is applied to the surfaces of the circuit portions 14 and 15.

A semiconductor package can be manufactured in this manner. A semiconductor element such as an IC is mounted in the window holes 20 and 12 of the first substrate 4 and the second substrate 11, and the first package is manufactured. Circuit portions 5 and 1 of substrate 4 and second substrate 11
The semiconductor device can be manufactured by bonding a semiconductor element with the inner lead portion 5 and performing sealing molding or the like.

[0007]

However, in manufacturing the semiconductor package as described above, FIG.
When the solder resist 7 is applied to one surface (upper surface) of the first substrate 4 as shown in (d), the ink of the solder resist 7 is scattered and adheres to the surface of the circuit portion 5 or FIG.
When laminating and forming the second substrate 11 on the first substrate 4 as in (a), there is a possibility that the resin of the prepreg 13 may scatter and adhere to the gold plating 8 on the surface of the circuit portion 5. In some cases, connection failure occurs when bonding the circuit portion 5.

When the second substrate 11 is laminated and formed on the first substrate 4 as shown in FIG. 8A, the other surface (lower surface) of the first substrate 4 and the second substrate 11 The resin of the prepreg 13 may be scattered and adhere to the surface of the metal layers 3 and 10 on one surface (upper surface). When the resin adheres to the metal layers 3 and 10 in this manner, the metal layers 3 and 10 are patterned. In this case, an etching failure occurs, and a failure occurs in the formation of the circuit portions 14 and 15.

These adhering resins can be removed by buffing, brushing, scrubbing or the like after circuit formation. However, in a semiconductor package having an inner lead portion for bonding a semiconductor element, a surface of the inner lead portion is formed. However, there is also a problem that during the removing operation, the surface is roughened and a bonding failure occurs. The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor package which can prevent a connection failure or a circuit formation failure due to adhesion of a solder resist or a prepreg resin from occurring. It is the purpose.

[0010]

According to the method of manufacturing a semiconductor package according to the present invention, a metal layer on one surface of a first substrate formed by providing metal layers on both surfaces of an insulating plate is provided. Forming a circuit portion 5 by patterning the substrate, forming a protective film 6 on the surface of the circuit portion 5, a first substrate 4
After the solder resist 7 is applied to the one surface except for the circuit portion 5, the protective film 6 is removed from the surface of the circuit portion 5.
Removing the surface of the circuit portion 5 that is not covered with the solder resist 7; and applying the gold plating 8 to the surface of the gold plating 8 of the circuit portion 5 and the metal layer 3 on the other surface of the first substrate 4. Forming a protective film 6 on each surface, forming a window hole 12 in a second substrate 11 formed by providing a metal layer 10 on at least one surface of the insulating plate 1, and forming one surface of the second substrate 11; Protective coating 6 on the surface of metal layer 10
Forming the second substrate 11 on the one surface of the first substrate 4 so that the circuit portion 5 is located in the window hole 12 on the surface opposite to the surface on which the protective coating 6 is formed. 13
Bonding and laminating via the gold plating 8 of the circuit portion 5
Surface, the surface of the metal layer 3 of the first substrate 4 and the second substrate 1
Removing each protective coating 6 on the surface of the first metal layer 10;
The metal layer 3 on the other surface of the first substrate 4 and the second substrate 1
1 wherein the metal layer 10 on one side is patterned to form circuit portions 14 and 15, respectively.

The invention according to claim 2 is characterized in that a dry film is used as the protective coating 6. The invention according to claim 3 is characterized in that the thickness of the protective coating 6 is 30 μm or more. According to a fourth aspect of the present invention, the outer dimensions of the protective film 6 formed on the surface of the gold plating 8 of the circuit portion 5 of the first substrate 4 are 0.3 mm from the size of the window holes 12 of the second substrate 11. The feature is that the dimensions are small as described above.

According to a fifth aspect of the present invention, when the protective film 6 is formed on the surface of the metal layer 3 on the other surface of the first substrate 4 and the surface of the metal layer 10 on the second substrate 11, respectively. The protective film 6 is formed on each whole surface.

[0013]

Embodiments of the present invention will be described below. First, a metal layer 2 or 3 formed of copper foil or the like is provided on both surfaces of an insulating plate 1 formed of a resin laminate or the like, such as a copper-clad laminate as shown in FIG. Using the substrate 4, a window hole 20 is formed at a predetermined position of the first substrate 4 as shown in FIG. The window hole 20 can be formed in an arbitrary shape such as a square, a rectangle, a circle, and an ellipse. However, such a window hole 20 is not provided depending on a design. At this time, a via hole (not shown) is formed as necessary.

Next, metal plating such as copper plating is applied to the entire surface of the first substrate 4, and metal plating 21 is formed on the surfaces of the metal layers 2 and 3, the inner periphery of the window hole 20, and the inner periphery of the via hole. Further, patterning is performed on the metal layer 2 on one surface (upper surface) of the first substrate 4 to form a circuit portion 5 around the window hole 20 as shown in FIG. (Omitted). The patterning can be performed by a conventionally well-known method including steps such as application of an etching resist, exposure, development, etching with an etching solution, and stripping of the etching resist.
The peripheral circuit portion 5 becomes an inner lead portion for bonding a semiconductor element.

Next, as shown in FIG. 1D, a protective film 6 is formed on the surface of the circuit portion 5 provided on the first substrate 4.
A dry film can be used as the protective film 6, and the protective film 6 can be formed on the surface of the circuit section 5 by attaching the dry film. After forming the protective film 6 on the surface of the circuit portion 5 in this manner, as shown in FIG. 1E, a solder resist 7 is formed on a predetermined portion of one surface (upper surface) of the first substrate 4 except for the circuit portion 5.
Is applied. After the solder resist 7 is applied to one surface (upper surface) of the first substrate 4 as described above, the protective film 6 on the surface of the circuit section 5 is removed. When a dry film is used as the protective film 6, the protective film 6 can be removed with a dry film stripper. Here, when the solder resist 7 is applied, since the surface of the circuit portion 5 is covered with the protective film 6 and protected, the solder resist 7 may be scattered and adhere to the surface of the circuit portion 5. This is not the case, and the solder resist 7 attached to the surface of the protective film 6 is removed when the protective film 6 is removed.

Thereafter, as shown in FIG.
A gold-plated dry film 22 is attached to the entire surface of the other surface (lower surface) of the substrate. Next, after gold plating is performed on the first substrate 4, the gold-resistant dry film 22 is peeled off. As shown in FIG. 1 (g), the gold plating 8 is not covered with the solder resist 7 or the gold-resistant plating dry film 22 and is exposed to the surface of the circuit portion 5 and the metal plating 21 on the inner periphery of the window hole 20. Attaches to surface.

After applying the gold plating 8 in this manner, FIG.
As shown in (g), a protective film 6 is formed on the gold plating 8 on the surface of the circuit portion 5 and the protective film 6 is formed on the entire surface of the metal layer 3 on the other surface (lower surface) of the first substrate 1. To form
As the protective film 6, a dry film can be used. On the other hand, a second metal plate 10 made of a copper foil or the like is provided on one surface (upper surface) of an insulating plate 9 made of a resin laminate or the like, such as a copper-clad laminate as shown in FIG. Using the second substrate 11, a predetermined position on the second substrate 11 is used as shown in FIG.
The window hole 12 is machined as shown in FIG. The window hole 12 can be formed in any shape such as a square, a rectangle, a circle, and an ellipse. The window hole 12 is formed to have a size larger than the window hole 20 of the first substrate 4. . At this time,
A via hole (not shown) is processed and copper plating is performed as necessary. The second substrate 11 can use a double-sided board or a multilayer board in addition to the single-sided board as described above.
In the case of a single-sided plate, it is not necessary to form a via hole.

After processing the window holes 12 in the second substrate 11 in this manner, as shown in FIG. 2C, the entire surface of the metal layer 10 provided on one surface (upper surface) of the second substrate 11 is formed. Protective coating 6
To form As the protective film 6, a dry film can be used. Also, using a prepreg 13 as shown in FIG. 3A, a window hole 23 having the same size as the window hole 12 of the second substrate 11 or a size of about 0.1 to 0.5 mm.
Is processed as shown in FIG.

The prepreg 13 is superimposed on the other surface (lower surface) of the second substrate 4 by aligning the window holes 12 and 23, and the second substrate 4 is laid on one surface (upper surface) of the first substrate 4 via the prepreg 13. The substrate 11 is placed on the first substrate 4 via an adhesive layer 13a of a prepreg 13 as shown in FIG.
Are laminated and formed. As described above, the first substrate 2 and the second substrate 11 can be formed in a two-stage structure.
By repeating the above steps, a structure having three or more stages can be formed. Here, in laminating in this manner, one surface (upper surface) of the first substrate 1
The surface of the gold plating 8 of the circuit portion 5, the surface of the metal layer 3 on the other surface (lower surface) of the first substrate 1, and the surface of the metal layer 10 on one surface (upper surface) of the second substrate 11 Are covered with the protective coating 6 and are protected, so that there is no possibility that the resin of the prepreg 13 will scatter and adhere to the surface of the gold plating 8 and the surfaces of the metal layers 3 and 10 of these circuit portions 5. .

2 (a) to 2 (c) and 3 (a) to 3 (a).
2B, the second substrate 11 as shown in FIG. 2A is processed with via holes and plated with copper as necessary, and then the other surface of the second substrate 11 Top) metal layer 10
The protective film 6 is formed on the entire surface of the second substrate 11, and a prepreg 13 as shown in FIG. 3A is temporarily bonded to the other surface (lower surface) of the second substrate 11 (the B-stage state of the prepreg 13 is maintained). Next, window holes 12 and 23 may be simultaneously formed in the temporarily bonded second substrate 11 and prepreg 13. Thereafter, lamination molding can be performed as shown in FIG.

As described above, the first substrate 2 and the second substrate 1
After laminating the first and second substrates 1 and 2, as shown in FIG. 4B, the surface of the gold plating 8 of the circuit portion 5 of the first substrate 4, the surface of the metal layer 3 of the first substrate 4, Each protective film 6 on the surface of the metal layer 10 of the second substrate 11 is removed. Protective coating 6
When a dry film is used, the protective film 6 can be removed by a dry film stripper. The resin adhering to the surface of the protective coating 6 is
Will be removed when removing.

Next, after processing the through-holes and performing copper plating as necessary, the metal layer 3 on the other surface (lower surface) of the first substrate 4 and one surface of the second substrate 11 are formed. By patterning the metal layer 10 (upper surface), FIG.
As shown in (c), the circuit portion 14 is formed on the other surface (lower surface) of the first substrate 4, and the circuit portion 15 is formed on one surface (upper surface) of the second substrate 11. The patterning can be performed by a conventionally well-known method including steps such as application of an etching resist, exposure, development, etching with an etching solution, and stripping of the etching resist. Circuit part 1 around window hole 12
Reference numeral 5 denotes an inner lead portion for bonding a semiconductor element.

Thereafter, as shown in FIG. 4D, if necessary, the other surface (lower surface) of the first substrate 4 and the second substrate 1
A solder resist 7 is applied to a portion of one surface (upper surface) of the device 1 except for the circuits 14 and 15, and a gold plating 8 is applied to the surfaces of the circuit portions 14 and 15. Thus, a semiconductor package can be manufactured, and the first substrate 4
And a semiconductor element such as an IC is mounted in the window holes 20 and 12 of the second substrate 11, and the semiconductor element is bonded by using the circuit portions 5 and 14 of the first substrate 4 and the second substrate 11 as inner lead portions. Further, a semiconductor device can be manufactured by performing sealing molding and the like.

Here, it is preferable to use a dry film having a thickness of 30 μm or more as the protective film 6. When the thickness is less than 30 μm, the effect of removing the solder resist 7 and the resin of the prepreg 13 adhered on the circuit portion 5 and the metal layers 3 and 10 may be insufficient. Although the upper limit of the thickness of the protective coating 6 is not particularly set, the thickness of the protective coating 6 exceeding 60 μm is considered in view of the workability of the application of the solder resist 7 and the workability of lamination molding.
Is not preferred.

In forming the protective film 6 on the surface of the circuit portion 5 of the first substrate 4 as shown in FIG. 1H, the protective film 6 is formed around the square window hole 20 of the first substrate 4. Is formed in a rectangular frame shape along the line. And when the inner dimension of the square window hole 12 of the second substrate 11 which is laminated on the first substrate 4 and L _1, as shown by hatching in FIG. 5, outer dimensions of the protective coating 6 L _It is preferable to form the protective coating 6 so that ₂ is smaller than L ₁ by 0.3 mm or more (that is, L ₂ ≦ L ₁ −0.3 mm). This takes into account a general interlayer displacement of 0.3 mm or less so that the protective coating 6 does not remain between the layers when the position is displaced during lamination molding. The lower limit of the outside dimension L ₂ of the protective coating 6 is not particularly set, it is preferable to set so as to cover the portion of performing at least bonding in accordance with the circuit design. Also, when the inner dimension of the window hole 20 of the first substrate 4 and L _3, inner dimensions L ₄ of the protective film 6 is preferably formed to be equal to or greater than the same dimensions as the L ₃ (i.e. L ₄ ≧ L ₃ ). The upper limit of the inner dimensions L ₄ of the protective film 6 is not particularly set, to obtain a sufficient effect of preventing the resin of the prepreg 13 is attached is the upper limit of L ₄ are set to L ₃ + 0.4 mm Is preferred.

As described above, the protective film 6 has the outer dimensions L ₂
Is 0.3 m from the inner dimension L ₁ of the window hole 12 of the second substrate 11.
m by making it smaller than m.
As shown in (a), when the second substrate 11 is laminated and formed on the first substrate 4, even if a slight displacement occurs between the first substrate 4 and the second substrate 11, the protective film 6 is not removed. This eliminates the possibility of being left between the first substrate 4 and the second substrate 11.

Next, the thickness and dimensions of the protective film 6 provided on the circuit portion 5 of the first substrate 4 in FIG. 1H, and the thickness and dimensions of the protective film 6 provided on the metal layer 3 of the first substrate 4 in FIG. Thickness of protective coating 6, FIG.
Table 1 shows the evaluation results of the case (c) in which the thickness of the protective film 6 provided on the metal layer 10 of the second substrate 11 was variously set. Table 2 shows the dimensions of the protective coating 6 provided on the circuit section 5.

[0028]

[Table 1]

[0029]

[Table 2]

[0030]

As described above, according to the present invention, a circuit portion is formed by patterning a metal layer on one surface of a first substrate formed by providing metal layers on both surfaces of an insulating plate. Forming a protective film on the surface of the circuit portion, applying a solder resist except for the circuit portion on the one surface of the first substrate, and then removing the protective film from the surface of the circuit portion; Applying gold plating on the surface of the circuit portion not covered with, a step of forming a protective coating on the surface of the gold plating of the circuit portion and the surface of the metal layer on the other surface of the first substrate, at least an insulating plate A step of opening a window hole in a second substrate formed by providing a metal layer on one side and forming a protective coating on the surface of the metal layer on one surface of the second substrate, wherein the circuit portion is in the window hole; Above one of the first substrate to be located A step of laminating and bonding the second substrate to the surface of the second substrate via a prepreg on the surface opposite to the surface on which the protective coating is formed, the surface of the gold plating of the circuit portion, the surface of the metal layer of the first substrate, and the second Removing the respective protective coatings on the surface of the metal layer of the substrate, patterning the metal layer on the other surface of the first substrate and the metal layer on the one surface of the second substrate to form a circuit portion. Since it is characterized by comprising the step of forming, it is possible to protect the circuit portion formed by patterning the metal layer on one surface of the first substrate with a protective film,
When applying the solder resist, it is possible to prevent the solder resist from adhering to the surface of the circuit portion, and to form the metal layer on the other surface of the first substrate and the metal layer on one surface of the second substrate. The surface can be protected with a protective coating,
It can prevent prepreg resin from adhering to these metal layers when laminating and molding the first substrate and the second substrate, and can prevent connection failure and circuit formation due to adhesion of solder resist or prepreg resin. It is possible to prevent a defect from occurring.

According to the second aspect of the present invention, since a dry film is used as the protective film, the protective film can be easily formed by sticking the dry film. According to the third aspect of the present invention, since the protective film having a thickness of 30 μm or more is used, the effect of preventing the adhesion of the solder resist or the resin of the prepreg can be enhanced.

According to a fourth aspect of the present invention, the outer dimensions of the protective film formed on the gold plating surface of the circuit portion of the first substrate are smaller than the dimensions of the window holes of the second substrate by at least 0.3 mm. When the first substrate and the second substrate are laminated and formed, even if there is a slight displacement between the two substrates, the protective film remains between the two substrates. Such a thing disappears.

According to a fifth aspect of the present invention, when the protective film is formed on the surface of the metal layer on the other surface of the first substrate and the surface of the metal layer on the second substrate, respectively, Is formed, so that the solder resist and the resin of the prepreg can be securely prevented from adhering to these metal layers.

[Brief description of the drawings]

FIGS. 1A to 1H show respective steps of an example of an embodiment of the present invention, and FIGS. 1A to 1H are cross-sectional views.

FIGS. 2A to 2C show steps of an example of an embodiment of the present invention, and FIGS. 2A to 2C are cross-sectional views.

FIGS. 3A and 3B show steps of an example of the embodiment of the present invention, and FIGS. 3A and 3B are cross-sectional views.

FIGS. 4A to 4D show respective steps of an example of the embodiment of the present invention, and FIGS. 4A to 4D are cross-sectional views.

FIG. 5 shows an example of an embodiment of the present invention,
(A) is a sectional view, and (b) is a plan view.

FIGS. 6A to 6E show steps of a conventional example, and FIGS. 6A to 6E are cross-sectional views.

FIGS. 7A to 7D show steps of a conventional example, and FIGS. 7A to 7D are cross-sectional views.

FIGS. 8A to 8C show steps of a conventional example, and FIGS. 8A to 8C are cross-sectional views.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 insulating plate 2 metal layer 3 metal layer 4 first substrate 5 circuit portion 6 protective film 7 solder resist 8 gold plating 9 insulating plate 10 metal layer 11 second substrate 12 window hole 13 prepreg 14 circuit portion 15 circuit portion

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Jun Tateda 1048 Kazuma Kadoma, Kadoma City, Osaka Inside Matsushita Electric Works, Ltd.

Claims (5)

[Claims] 1. A step of patterning a metal layer on one surface of a first substrate formed by providing a metal layer on both surfaces of an insulating plate to form a circuit portion, and applying a protective coating on the surface of the circuit portion. Forming, applying a solder resist to the one surface of the first substrate except for the circuit portion, and then removing a protective film from the surface of the circuit portion, the surface of the circuit portion not covered with the solder resist A step of applying a gold plating to, a step of forming a protective coating on the surface of the gold plating of the circuit portion and the surface of the metal layer on the other surface of the first substrate, respectively.
A step of forming a window hole in a second substrate formed by providing a metal layer on at least one surface of the insulating plate and forming a protective coating on the surface of the metal layer on one surface of the second substrate, A step of laminating and bonding a second substrate to the one surface of the first substrate via a prepreg on the surface opposite to the surface on which the protective film is formed, so that the circuit portion is located, gold plating of the circuit portion Removing the protective coating on the surface of the first substrate metal layer and the surface of the second substrate metal layer, the above-mentioned metal layer on the other surface of the first substrate and the second substrate A method of manufacturing a semiconductor package, comprising: forming a circuit portion by patterning a metal layer on one surface. 2. The method according to claim 1, wherein a dry film is used as the protective film. 3. The method according to claim 1, wherein the thickness of the protective coating is 30 μm or more. 4. A method according to claim 1, wherein an outer dimension of the protective coating formed on the surface of the gold plating of the circuit portion of the first substrate is smaller than a dimension of a window hole of the second substrate by at least 0.3 mm. The method of manufacturing a semiconductor package according to claim 1. 5. A method for forming a protective film on the surface of the metal layer on the other surface of the first substrate and the surface of the metal layer on the second substrate, wherein the protective film is formed on the entire surface. The method of manufacturing a semiconductor package according to claim 1.