JPH10303314A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an electrostatic destruction of an input circuit and an increase in pattern area, by connecting a power source side input protection circuit between an input terminal and a power source line or an earth line, while connecting an inter-power source protection circuit between the power source line and the earth line. SOLUTION: To a power source line L1 and an earth line L2, an input circuit 12 wherein a signal is supplied from an input terminal 11 for signal processing is connected. Then, between the input terminal 11 and the power source line L1, an input protection circuit 21 wherein the input terminal 11 is applied with a surge voltage toward a power source voltage Vcc and the electric charge caused by the surge voltage is by-passed to the power source line L1 is connected. Further, between the input terminal 11 and the earth line 2, an input protection circuit 22 wherein the input terminal 11 is applied with a surge voltage toward an earth voltage and such electric charge as caused by the surge voltage is by-passed to the earth line L2 is connected. Further, inter-power source protection circuits 23 and 24 for by-passing the electric charge caused by the surge voltage are connected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a protection circuit for preventing an input circuit in a semiconductor device from being damaged by electrostatic discharge.

[0002]

2. Description of the Related Art A semiconductor device is often provided with a protection circuit to prevent an input circuit connected to an input terminal from being electrostatically damaged when an excessive surge voltage is applied to the input terminal. . FIG. 6 shows the configuration of a conventional protection circuit together with the configuration of an input circuit. A P-channel MOS transistor PT11 and an N-channel MOS transistor connected in series between a power supply voltage Vcc terminal and a ground terminal are provided at an input portion of the semiconductor device.
CMOS type input circuit 1 including transistor NT11
2 are provided. Transistors PT11 and NT1
One of the gates is connected to the input terminal 11, and a signal input from the input terminal 11 is supplied to these gates.

An input protection circuit 21 on the power supply voltage Vcc side is connected between the input terminal 11 and the power supply voltage Vcc terminal, and an input protection circuit 2 on the ground side is connected between the input terminal 11 and the ground terminal.
2 are connected. When a positive-side surge voltage exceeding the power supply voltage Vcc is applied to the input terminal 11, electric charges due to the surge voltage pass through the protection circuit 21 and flow to the power supply line L1 as indicated by an arrow P1. Conversely, when a negative surge voltage lower than the ground voltage Vss is applied to the input terminal 11, the charges due to this surge voltage pass through the protection circuit 22 and flow to the ground line L2 as indicated by an arrow P2. As described above, conventionally, the surge voltage forms the transistor PT constituting the input circuit 12.
11 and NT11 were prevented from being destroyed.

[0004]

However, the conventional protection circuit has the following problems. The charge bypassed to the power supply line L1 or the ground line L2 does not enter the gates of the transistors PT11 and NT11, so that no gate breakdown occurs. However, the charge bypassed to the power supply line L1 enters the source region of the transistor PT11, and the charge bypassed to the ground line L2 enters the source region of the transistor NT11. As a result, the input circuit 12 may cause electrostatic breakdown.

As a method for preventing such a problem, a power supply line L1 to which the input protection circuit 21 is connected and an input protection circuit 2
2 is connected to the power supply line and the ground line to which the input circuit 12 is connected.
It is also conceivable to keep them out. But,
In this case, the number of power supply lines and ground lines increases, so that the area where the wiring is routed increases, which leads to an increase in pattern area and cost.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit capable of reliably preventing electrostatic breakdown of an input circuit and preventing an increase in a pattern area. I do.

[0007]

A semiconductor integrated circuit according to the present invention is connected to a power supply line and a ground line, receives an input signal from an input terminal and processes the signal, an input circuit and the power supply. When a first surge voltage in a power supply voltage direction is input to the input terminal, the first
A power-supply-side input protection circuit for bypassing the electric charge due to the surge voltage of the power supply line to the power supply line, and a first power-supply-side protection circuit connected between the power supply line and the ground line and bypassed to the power supply line by the power supply-side input protection circuit. An inter-power supply protection circuit for bypassing a charge caused by a surge voltage to the ground line.

Further, the semiconductor integrated circuit of the present invention is connected between the input circuit, the input terminal and the ground line, and receives a second surge voltage in a ground voltage direction at the input terminal. A ground-side input protection circuit that bypasses the electric charge due to the second surge voltage to the ground line, and is connected between the power supply line and the ground line, and is bypassed to the ground line by the ground-side input protection circuit. An inter-power supply protection circuit for bypassing the electric charge due to the second surge voltage to the power supply line.

Alternatively, the semiconductor integrated circuit according to the present invention is connected to the input circuit, the power-supply-side input protection circuit, the ground-side input protection circuit, and between the power supply line and the ground line. A charge due to a first surge voltage bypassed to the power supply line by a side input protection circuit is bypassed to the ground line, and a charge due to a second surge voltage bypassed to the ground line by the ground side input protection circuit is transferred to the ground line. An inter-power supply protection circuit that bypasses the power supply line.

The power supply protection circuit includes a first N-channel MOS transistor having a gate connected to the ground line and one terminal connected to the power supply line, and a power supply line connected to the other terminal. Is connected to the gate and one terminal,
A first P-channel MOS transistor having the other terminal connected to the ground line may be provided.

The power supply-side input protection circuit includes a second N-channel MOS transistor having a gate connected to the ground line, one terminal connected to the power supply line, and the other terminal connected to the input terminal. A third N-channel MOS transistor having a gate connected to the ground line, one terminal connected to the ground line, and the other terminal connected to the input terminal. It may have a transistor.

Alternatively, the power-supply-side input protection circuit has a second P-channel type in which a gate is connected to the ground line, one terminal is connected to the power line, and the other terminal is connected to the input terminal. A second N-channel having a MOS transistor, wherein the ground-side input protection circuit has a gate connected to the ground line, one terminal connected to the ground line, and the other terminal connected to the input terminal; It may have a MOS transistor.

[0013] The semiconductor integrated circuit of the present invention is connected to a first wiring to which a first voltage is supplied and a second wiring to which a second voltage lower than the first voltage is supplied. An input circuit that receives a signal from a terminal to process the signal, is connected between the input terminal and the first wiring, and receives a first positive surge voltage in the input terminal. A first input protection circuit for bypassing the charge caused by the first surge voltage to the first wiring, a second input protection circuit connected between the input terminal and the second wiring, and a second negative terminal connected to the input terminal; Of the second surge voltage, the charge generated by the second surge voltage is bypassed to the second wiring.
And a charge caused by a first surge voltage connected between the first wiring and the second wiring and bypassed to the first wiring by the first input protection circuit. A power supply protection circuit for bypassing to the second wiring, and for bypassing to the first wiring the charge due to the second surge voltage bypassed to the second wiring by the second input protection circuit. .

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a protection circuit according to the first embodiment of the present invention. The difference from the protection circuit shown in FIG. 6 is that inter-power supply protection circuits 23 and 24 are connected between the power supply line L1 and the ground line L2, respectively. The same elements as those in the other circuits of FIG. 6 are denoted by the same reference numerals, and description thereof is omitted.

When a positive-side surge voltage exceeding the power supply voltage Vcc is applied to the input terminal 11, the electric charge due to the surge voltage flows through the protection circuit 21 to the power supply line L1. Alternatively, when a negative surge voltage lower than the ground voltage Vss is applied to the input terminal 11, the charge due to the surge voltage flows to the ground line L <b> 2 via the protection circuit 22. In the protection circuit shown in FIG. 6, as described above, the charge released to the power supply line L1 enters the source region of the transistor PT11 of the input circuit 12, or the charge released to the ground line L2 enters the source region of the transistor NT11. Had entered and destroyed.

On the other hand, in the present embodiment, the power supply line L
The charge bypassed to 1 further passes through the power supply protection circuit 24 as shown by the arrow P11 and flows to the ground line L2, and the charge bypassed by the ground line L2 further passes through the power supply protection circuit 23 as shown by the arrow P12. Then, it flows to the power supply line L1. For this reason, the transistor PT11 or NT of the input circuit 12
Static electricity does not enter the source region 11 and electrostatic breakdown is prevented.

Further, since the power supply line L1 and the ground line L2 are branched only between the input protection circuits 21 and 22 and the power supply protection circuits 23 and 24, an increase in the pattern area is prevented.

The second embodiment of the present invention has the configuration shown in FIG. This embodiment corresponds to those in which the input protection circuits 21 and 22 and the inter-power supply protection circuits 23 and 24 in the first embodiment are represented by specific circuit elements. That is, as the input protection circuit 21, an N-channel type MO having one terminal connected to the power supply line L1, the other terminal connected to the input terminal 11, the back gate and the gate connected to the ground line L2.
The S-transistor NT21 is used. As the input protection circuit 22, an N-channel MOS transistor NT22 having one terminal connected to the input terminal 11, the other terminal, a back gate, and a gate connected to the ground line L2 is used. Further, as an inter-power supply protection circuit 23, a P-channel MOS transistor PT having one terminal, a back gate, and a gate connected to a power supply line L1 and the other terminal connected to a ground line L2.
As an inter-power supply protection circuit 24, an N-channel MOS transistor NT23 having one terminal connected to the power supply line L1 and the other terminal, back gate and gate connected to the ground line L2 is used.

The operation when an excessive surge voltage occurs at the input terminal 11 is the same as that of the first embodiment.
When a positive surge voltage is applied to the input terminal 11, as shown by an arrow P21, the charges due to the surge voltage are bypassed to the power supply line L1 via the transistor NT21 and further to the ground line L2 via the transistor NT23. Is done. When a negative-side surge voltage is applied to the input terminal 11, the charges due to the surge voltage are bypassed to the ground line L2 via the transistor NT22 and to the power supply line L1 via the transistor PT21 as shown by an arrow P22. . Thereby, the transistor P of the input circuit 12
Static electricity does not enter the source regions of T11 and NT11,
Electrostatic breakdown is prevented.

The equivalent circuit of the second embodiment is shown in FIG.
As shown in FIG. The transistor NT22 included in the protection circuit 22 is electrically equivalent to the diode D1 connected between the input terminal 11 and the ground line L2. Therefore, the operation when a surge voltage is applied is the same as that of the second embodiment.

FIG. 4 shows a third embodiment of the present invention.
This will be described with reference to FIG. The difference from the second embodiment shown in FIG. 2 is that the transistors constituting the input protection circuit 21 are replaced by N-channel MOS transistors NT21 to P-channel MOS transistors PT31. In the transistor PT31, one terminal and a back gate are connected to the power supply line L1, the gate is connected to the ground line L2, and the other terminal is connected to the input terminal 11.

When a positive surge voltage is applied to the input terminal 11, electric charges flow to the power supply line L1 via the transistor PT31 as shown by an arrow P31, and furthermore, the transistor NT
23 to the ground line L2. When a negative surge voltage is applied to the input terminal 11, as in the second embodiment, the ground line L2 is connected via the transistor NT22.
To the power supply line L via the transistor PT21.
Flow to 1. As a result, charges due to the surge voltage do not flow into the input circuit 12 and are protected from electrostatic breakdown.

FIG. 5 shows the third embodiment as an electrically equivalent circuit. That is, the transistor PT31 operates as a diode D2 connected between the input terminal 11 and the power supply line L1. The transistor NT22 operates as a diode D1 connected between the input terminal 11 and the ground line L2.

A comparison between FIG. 5 in which the third embodiment is represented by an equivalent circuit and FIG. 3 in which the second embodiment is represented by an electrically equivalent circuit indicates that the circuit in FIG. A diode D2 is connected between the power supply line 11 and the power supply line L1, whereas the circuit of FIG. 3 is different in that the diode D2 is not provided. Due to such a configuration difference,
It is desirable that the protection circuit according to the second embodiment and the protection circuit according to the third embodiment be properly used depending on the application.

For example, the power supply voltage Vcc is 5 V like a level shifter, but the product in which a voltage of 10 V exceeding this is input to the input terminal 11 is used in the second embodiment. It is suitable. That is, when 10 V is input to the input terminal 11, no current flows from the input terminal 11 to the power supply line L1 because the diode D2 does not exist, and the protection circuit does not affect the circuit characteristics. On the other hand, in the third embodiment, since the diode D2 exists, the input terminal 1
A current flows from 1 to the power supply line L1, and the characteristics deteriorate. Conversely, in a device in which a voltage exceeding the power supply voltage Vcc is not applied to the input terminal 11, the third terminal in which the diode D2 exists
In the third embodiment, the excessive surge voltage on the positive side can be more reliably released to the power supply line L1. Therefore, it is desirable to apply the third embodiment.

The above-described embodiments are merely examples, and do not limit the present invention. For example, those in which the input protection circuits 21 and 22 and the inter-power supply protection circuits 23 and 24 in the first embodiment are specifically configured using MOS transistors correspond to the second and third embodiments. However, the present invention is not limited to these configurations, and when a surge voltage is applied to the input terminal, the power supply line or the ground line is bypassed.
Anything that can be bypassed to the ground line or the power line before entering the input circuit may be used.

[0027]

As described above, in the semiconductor integrated circuit of the present invention, when a surge voltage is applied to an input terminal, when a bypass is made to a power supply line, a bypass is further made to a ground line,
When bypassing to the ground line, bypassing to the power supply line can prevent charges from entering the input circuit due to surge voltage, preventing electrostatic breakdown without increasing the pattern area It is.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration in a case where the semiconductor integrated circuit according to the second embodiment is replaced with an electrically equivalent circuit.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration in a case where the semiconductor integrated circuit according to the third embodiment is replaced with an electrically equivalent circuit.

FIG. 6 is a circuit diagram showing a configuration of a conventional protection circuit together with a configuration of an input circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Input terminal 12 Input circuit 21, 22 Input protection circuit 23, 24 Power supply protection circuit L1 Power supply line L2 Ground line PT11, PT21, PT31 P-channel type MOS transistor NT11, NT21 to NT23 N-channel type MOS transistor D1, D2 Diode

Claims (8)

[Claims] An input circuit connected to a power supply line and a ground line, receiving a signal from an input terminal to process the signal, connected between the input terminal and the power supply line, and connected to the input terminal. When a first surge voltage in a power supply voltage direction is input, the power supply-side input protection circuit is configured to bypass a charge caused by the first surge voltage to the power supply line, and is connected between the power supply line and the ground line; And a power supply protection circuit that bypasses, to the ground line, a charge caused by a first surge voltage that is bypassed to the power supply line by the power supply side input protection circuit. 2. An input circuit connected to a power supply line and a ground line and receiving a signal from an input terminal to process the signal, connected between the input terminal and the ground line, and connected to the input terminal. When a second surge voltage in the direction of the ground voltage is input, a ground-side input protection circuit that bypasses the electric charge due to the second surge voltage to the ground line, and is connected between the power supply line and the ground line; A power supply protection circuit for bypassing, to the power supply line, a charge due to a second surge voltage bypassed to the ground line by the ground side input protection circuit. 3. An input circuit connected to a power supply line and a ground line and receiving a signal from an input terminal to process the signal, connected between the input terminal and the power supply line, and connected to the input terminal. When a first surge voltage in a power supply voltage direction is input, the power supply side input protection circuit is configured to bypass a charge caused by the first surge voltage to the power supply line, and is connected between the input terminal and the ground line; When a second surge voltage in the direction of the ground voltage is input to the input terminal, a ground-side input protection circuit that bypasses a charge caused by the second surge voltage to the ground line, between the power supply line and the ground line. A second surge bypassed to the ground line by the first surge voltage connected to the power supply line by the power supply side input protection circuit, and bypassed to the ground line by the ground side input protection circuit. Sa The semiconductor integrated circuit comprising: the power supply between the protected circuit for bypassing the charge due to surge voltages on the power line, the. 4. A power supply protection circuit, comprising: a first N-channel MOS transistor having a gate and one terminal connected to the ground line, and having the other terminal connected to the power supply line;
A first P-channel MOS having a gate and one terminal connected to the power supply line, and the other terminal connected to the ground line;
4. The semiconductor integrated circuit according to claim 3, comprising a transistor. 5. The power supply side input protection circuit is a second N-channel type having a gate connected to the ground line, one terminal connected to the power supply line, and the other terminal connected to the input terminal. A third N-channel having a MOS transistor, wherein the ground-side input protection circuit has a gate connected to the ground line, one terminal connected to the ground line, and the other terminal connected to the input terminal; MOS
5. A transistor having a transistor.
A semiconductor integrated circuit as described in the above. 6. The second P-channel type power supply side input protection circuit, wherein a gate is connected to the ground line, one terminal is connected to the power supply line, and the other terminal is connected to the input terminal. A second N-channel having a MOS transistor, wherein the ground-side input protection circuit has a gate connected to the ground line, one terminal connected to the ground line, and the other terminal connected to the input terminal; MOS
5. A transistor having a transistor.
A semiconductor integrated circuit as described in the above. 7. An input circuit connected to a power supply line and a ground line and receiving a signal from an input terminal to process the signal, connected between the input terminal and the power supply line, and connected to the input terminal. When a first surge voltage in a power supply voltage direction is input, the power supply side input protection circuit is configured to bypass a charge caused by the first surge voltage to the power supply line, and is connected between the input terminal and the ground line; When a second surge voltage in the direction of the ground voltage is input to the input terminal, a ground-side input protection circuit that bypasses a charge due to the second surge voltage to the ground line; and a gate and one terminal are connected to the ground line. A first N-channel MOS connected to the power supply line and the other terminal connected to the power supply line
A transistor, a first P-gate having a gate and one terminal connected to the power supply line, and a second terminal connected to the ground line;
A semiconductor integrated circuit, comprising: a power supply protection circuit having a channel type MOS transistor. 8. A first wiring to which a first voltage is supplied and a second wiring to which a second voltage lower than the first voltage is supplied, wherein a signal is supplied from an input terminal to the first wiring. An input circuit for processing a signal; a charge connected between the input terminal and the first wiring, wherein a first surge voltage in the positive direction is input to the input terminal, and A first input protection circuit that bypasses the first wiring to the first wiring, and a second surge voltage in a negative direction is input to the input terminal between the input terminal and the second wiring. A second input protection circuit for bypassing the electric charge due to the second surge voltage to the second wiring; a first input protection circuit connected between the first wiring and the second wiring; The first surge voltage bypassed to the first wiring A power supply protection circuit for bypassing to the first wiring, a charge by a second surge voltage bypassed to the second wiring by the second input protection circuit. A semiconductor integrated circuit, comprising: