JPH10290005A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the defocus margin for lithography for securing flatness, by suppressing the fluctuation in the threshold voltage when the gate length is shortened by providing a shallow junction. SOLUTION: A semiconductor device is provided with a gate electrode 30 arranged from a channel forming region through the intermediary of a gate insulating film 20 and source drain regions 12 arranged in a trench inside a semiconductor substrate 10 through the intermediary of the gate insulating film 20 to be connected to the channel forming region. Besides, the film thickness of the source drain regions 12 is specified equivalent to that of the gate electrode 30 or less. Through these procedures, a field effect transistor capable of running a current in the source drain regions 12 passing through the channel region formed in the channel forming region can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a field effect transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the recent trend toward higher integration and miniaturization of semiconductor devices, insulated gate field effect transistors such as MOS
FET (Metal Oxide Semiconductor Field Effect Tra)
nsistor) gate length has been reduced.

FIG. 11 shows an example of a cross-sectional view of a conventionally used MOSFET structure. A gate electrode 30 made of, for example, polysilicon containing an n-type impurity is formed on an active region of, for example, a p-type semiconductor substrate 10 separated by an element isolation insulating film (not shown) via a gate insulating film 20 made of, for example, silicon oxide. LDD sidewall insulating film 2 made of, for example, silicon oxide on both sides thereof
1 is formed. A source / drain diffusion layer 12 containing, for example, a high concentration of n-type impurities is formed in the semiconductor substrate 10 on both sides of the gate electrode, and an LDD (for example, containing a low concentration of n-type impurities) is formed inside the semiconductor substrate 10. Lightly
Doped Drain) A diffusion layer is formed.

In the above-mentioned MOSFET, a voltage is applied to the gate electrode 30 and charges of the opposite polarity to the substrate are charged to the semiconductor substrate 10.
A channel which is induced on the surface and forms a current path on the surface of the semiconductor substrate 10 between the source / drain diffusion layers 12 is formed, and charges injected from the source diffusion layers are taken out as a current by a voltage applied to the drain diffusion layers.

When the voltage applied to the gate electrode is lower than the threshold voltage Vth required to induce an inversion layer on the surface of the semiconductor substrate 10, the source diffusion layer and the drain diffusion layer are separated from each other. No drain current flows. On the other hand, when the voltage applied to the gate electrode is equal to or higher than the threshold voltage Vth, the induced inversion layer becomes a channel, and current can flow from the source diffusion layer to the drain diffusion layer.

[0006]

However, in the above-mentioned MOSFET, the gate length is shortened with the increase in the degree of integration and miniaturization of the semiconductor device, and the threshold voltage tends to decrease rapidly below a certain gate length. appear. This is called roll-off and has been known for a relatively long time as a typical phenomenon of the short channel effect.

In the roll-off, when the gate length becomes shorter, not only the charge of the gate electrode but also the charge of the source / drain diffusion layers contribute to the formation of the inversion layer below the gate electrode. The channel region is formed not only in the portion immediately below the gate electrode but also in the depth direction of the side portions of the source / drain diffusion layers, so that a current flows two-dimensionally. As a result, less gate charge, That is, an inversion layer is formed at a lower gate voltage,
The threshold voltage Vth shifts to the smaller one.

The above-described roll-off means that the threshold voltage Vth changes when the gate length changes, and
In addition, MOSFE with a short gate length often used in high integration
The variation of the threshold voltage Vth becomes larger as T becomes larger.
This is a problem in achieving predetermined characteristics.

In order to suppress the roll-off, it is known that it is effective to reduce the junction depth. This is because the amount of the source / drain depletion layer protruding toward the channel can be reduced. For example, an n-channel MOSF having a channel length of 0.25 μm
In ET, it is said that the depth of the source / drain diffusion layer must be reduced to 0.1 μm or less.

In the above-described conventional MOSFET structure, an LDD diffusion layer containing a conductive impurity at a lower concentration than that of the source / drain diffusion layer is formed at the center of the gate between the source / drain diffusion layers. I have. The LDD diffusion layer is provided to increase hot carrier resistance, but also has the effect of reducing the junction depth. However, in order to further increase the degree of integration of a semiconductor device, it is necessary to further reduce the junction depth.

Further, in the above-mentioned conventional MOSFET structure, since the gate electrode portion is located above the source / drain electrode outlet, the flatness has already been lost since the transistor was formed. However, there is a problem that a large defocus margin is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is therefore an object of the present invention to suppress a variation in threshold voltage when the gate length is reduced by having a shallow junction, and to reduce the gate length. MOSFET that can be used up to a short area of the gate electrode, and the heights of the gate electrode and the outlet of the source / drain electrode can be made uniform
And a method of manufacturing the same.

[0013]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate having a channel forming region, and a semiconductor substrate disposed from the channel forming region via a gate insulating film. A gate electrode formed in a trench shape therein, and a source / drain region disposed in a semiconductor substrate on both sides of the gate electrode via an insulating film and connected to the channel formation region; The thickness of the drain region is substantially equal to or less than the thickness of the gate electrode, and a predetermined voltage is applied to the gate electrode to pass through the channel region formed in the channel formation region to the source / drain region. It has a field-effect transistor through which current can flow.

The semiconductor device of the present invention has a gate electrode buried in a semiconductor substrate, unlike the conventional field effect transistor, and has source / drain regions in the semiconductor substrate on both sides of the gate electrode. Since the thickness of the source / drain region is substantially equal to or less than the thickness of the gate electrode, the junction depth of the field effect transistor can be made very shallow. Therefore, it is possible to prevent the channel region from being formed not only immediately below the gate electrode but also in the depth direction of the side portion of the source / drain region so that a current flows two-dimensionally. It is possible to suppress the roll-off in which the threshold voltage is rapidly reduced. That is, it is possible to suppress the fluctuation of the threshold voltage when the gate length is shortened, and to use even a region where the gate length is short.

The semiconductor device of the present invention is preferably
The surface of the gate electrode, the source / drain region, and the surface of the semiconductor substrate have substantially the same height. Thereby, the height of the gate electrode and the height of the source / drain electrode take-out openings are made uniform, so that the flatness is obtained, and the defocus margin for lithography can be reduced.

The semiconductor device according to the present invention is preferably
The source / drain region has a thickness smaller than that of the gate electrode, and has a channel formation region below and on both sides of the gate electrode. By embedding the gate electrode in the semiconductor substrate, the junction depth can be reduced and roll-off can be suppressed. In addition, the side surface of the gate electrode can be a channel formation region. Even in a transistor having a short gate length, the effective channel length can be increased, which is advantageous for miniaturization and high integration of the device.

The semiconductor device according to the present invention is preferably
It is formed on an insulating film formed on a semiconductor substrate. SOI (Silicon On Ins) having a semiconductor layer on the insulating film
ulator) structure. A complete element isolation structure that can reduce the parasitic capacitance of the device can be obtained, which is advantageous in increasing the speed of the device.

The semiconductor device of the present invention is preferably
A lower gate insulating film in a lower layer of the channel forming region below the gate electrode, a lower gate electrode in a lower layer of the lower gate insulating film, and a channel in both sides of the lower gate electrode; There is a lower source / drain region connected to the formation region and having a thickness substantially equal to or less than the thickness of the lower gate electrode. This makes it possible to form a field effect transistor having a double gate structure forming a pair up and down. It is possible to provide a transistor whose operation can be easily controlled, for example, in which the upper gate electrode and the lower gate electrode handle a change in drain current and a steady current, respectively.

In the above-described semiconductor device of the present invention, more preferably, the gate electrode, the source / drain region and the surface of the semiconductor substrate have substantially the same height. Thus, the height of the gate electrode and the height of the source / drain electrode outlet can be made uniform to reduce the margin of defocus for lithography. More preferably, the thickness of the source / drain region is smaller than the thickness of the gate electrode, and a channel formation region is provided below and on both sides of the gate electrode. The side surface of the gate electrode can also be a channel formation region. The effective channel length can be increased even in a transistor having a short gate length. More preferably, it is formed on an insulating film formed on a semiconductor substrate. Complete element isolation structure (SO
I structure).

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a trench-shaped recess for a gate electrode in a semiconductor substrate, and a step of forming a gate insulating film on an inner wall surface of the recess for a gate electrode. Forming a gate electrode by embedding a conductor in the gate electrode recess, and forming a film having a thickness substantially equal to or less than the film thickness of the gate electrode in the semiconductor substrate on both sides of the gate electrode. Forming source / drain regions having the following.

The method of manufacturing a semiconductor device according to the present invention is as follows.
The gate electrode is formed by embedding the gate electrode in a recess formed in a trench shape in the semiconductor substrate, and the junction depth can be reduced. The channel region is formed not only in the portion immediately below the gate electrode but also in the source / drain region. A field-effect transistor that can be formed over the depth direction of the side and can suppress the current from flowing two-dimensionally, and can suppress the roll-off in which the threshold voltage drops sharply when the gate length becomes less than a certain gate length. A semiconductor device having the same can be manufactured. Since the fluctuation of the threshold voltage when the gate length is shortened can be suppressed, it is possible to use even a region where the gate length is short.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, the step of forming a gate electrode by embedding a conductor in the recess for the gate electrode includes the step of forming a gate electrode having substantially the same height as the surface of the semiconductor substrate. By making the heights of the gate electrode and the source / drain electrode outlets uniform, a transistor having flatness can be formed, so that a defocus margin for lithography can be reduced.

The method of manufacturing a semiconductor device of the present invention described above
Preferably, after the step of forming the gate insulating film, before the step of forming the gate electrode, a step of forming an insulating film thicker than the gate insulating film on the side wall of the recess for the gate electrode is provided. By making the insulating film between the gate electrode and the source / drain region thicker than the gate insulating film, the withstand voltage between the adjacent gate electrode and the source / drain electrode can be increased.

The method for manufacturing a semiconductor device of the present invention described above
Preferably, the step of forming the source / drain region is a step of forming the source / drain region with a smaller thickness than the gate electrode. The side surface of the gate electrode can also be a channel formation region, so that a semiconductor device including a field-effect transistor that can have a long effective channel length even in a transistor having a short gate length can be manufactured.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, before the step of forming a recess for a gate electrode in the semiconductor substrate, a step of forming a laminate of an insulating film and a semiconductor layer to form the semiconductor substrate is provided. Complete element isolation structure (SO
A semiconductor device having a field-effect transistor having an I structure) can be manufactured. As a method of forming a stacked body of an insulating film and a semiconductor layer, a method of depositing a semiconductor layer such as polysilicon on the insulating film by a CVD method or the like, a method of bonding the insulating film and the semiconductor layer, A method of forming an insulating film by ion implantation, a method of forming a semiconductor layer on the insulating film by epitaxial growth, or the like.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, prior to the step of forming the gate electrode recess in the semiconductor substrate, a step of forming a trench-shaped lower gate electrode recess in the semiconductor layer, and a step of forming a lower portion on the inner wall surface of the lower gate electrode recess. Forming a lower gate insulating film, forming a lower gate electrode by embedding a conductor in the lower gate electrode recess, and forming the lower gate in a semiconductor substrate on both sides of the lower gate electrode. Forming a lower source / drain region having a thickness substantially equal to or less than the thickness of the electrode, and forming an insulating film on a surface on which the lower gate electrode is formed on the semiconductor layer; And the step of Thus, it is possible to manufacture a semiconductor device having a field effect transistor having a double gate structure which is paired up and down. The upper gate electrode and the lower gate electrode handle the change amount and the steady state amount of the drain current, respectively, so that the transistor can be easily controlled.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, the step of forming a lower gate electrode by embedding a conductor in the lower gate electrode recess includes a step of forming a lower gate electrode having substantially the same height as the surface of the semiconductor substrate. By making the heights of the gate electrode and the source / drain electrode outlets uniform, a transistor having flatness can be formed, so that a defocus margin for lithography can be reduced.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, before the step of forming a recess for a gate electrode in the semiconductor substrate, a step of forming a lower gate electrode on an insulating film, and forming a lower gate insulating film on an upper layer of the lower gate electrode Forming a lower source / drain region having a thickness substantially equal to or less than the thickness of the lower gate electrode on both sides of the lower gate electrode; and forming the lower gate insulating film; and Forming a semiconductor layer on the entire surface by covering the lower source / drain region to form the semiconductor substrate. Thus, it is possible to manufacture a semiconductor device having a field effect transistor having a double gate structure which is paired up and down. The upper gate electrode and the lower gate electrode handle the change amount and the steady state amount of the drain current, respectively, so that the transistor can be easily controlled.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor device according to the present invention will be described below by way of examples with reference to the drawings.

Embodiment 1 FIG. 1 is a sectional view of a semiconductor device according to this embodiment. On the n-type silicon semiconductor substrate 10, a LO (not shown)
There is a region separated by a COS element isolation film, and a well 11 containing a p-type impurity is provided. It is surrounded by a gate insulating film 20 made of, for example, silicon oxide.
For example, it has a gate electrode 30 made of polysilicon.
On both sides of the gate electrode 30, a first insulating film 21 made of, for example, silicon oxide, which is thicker than the gate insulating film 20, is provided. On both sides thereof, a source / drain containing a high concentration of n-type impurities is provided. It has a diffusion layer 12. The source / drain diffusion layer 12 is connected to the active region of the well 11, and has a thickness substantially equal to that of the gate electrode 30. The surfaces of the gate electrode 30, the source / drain diffusion layer 12, and the semiconductor substrate 10 are at substantially the same height and are flattened.

In the semiconductor device having such a structure, the junction depth of the field effect transistor can be made very shallow, and the channel region is formed not only in the portion immediately below the gate electrode but also in the portion below the gate electrode.
Since it is possible to suppress the current from flowing two-dimensionally by being formed in the depth direction of the side portion of the source / drain diffusion layer, it is possible to suppress the roll-off in which the threshold voltage is sharply reduced when the gate length is shorter than a certain gate length. be able to. That is,
Suppress the fluctuation of the threshold voltage when shortening the gate length,
It is possible to use a region having a short gate length. Also, since the surface of the gate electrode, the source / drain diffusion layer and the surface of the semiconductor substrate are almost the same height, the gate electrode and the source / drain electrode take-out openings have the same height so that they have flatness, and the It is possible to reduce the defocus margin.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 2A, an element isolation insulating film (not shown) is formed on an n-type silicon semiconductor substrate 10 by a LOCOS method or the like, and a p-type impurity is ion-implanted to form a p-type well 11. .

Next, as shown in FIG. 2B, a resist is patterned and used as a mask, and etching such as RIE (reactive ion etching) is performed to form a trench T in the center of the well 11. After that, the resist is removed.

Next, as shown in FIG. 2C, a gate insulating film 20 made of silicon oxide is formed on the inner wall surface of the trench T by thermal oxidation or the like.

Next, as shown in FIG. 3D, for example, oxygen ions are implanted into the semiconductor substrate 10 at an oblique angle to form a silicon oxide layer, and gates are formed on both side walls of the trench T. A first insulating film 21 thicker than the insulating film 20 is formed.

Next, as shown in FIG.
Polysilicon is deposited by the VD method, and the CMP (Chemic
The gate electrode 30 is formed by burying polysilicon in the trench T by flattening polishing such as al mechanical polishing or etching back.

Next, as shown in FIG. 1, a resist is patterned and used as a mask, n-type impurities are ion-implanted at a high concentration, source / drain diffusion layers 12 are formed, and a field effect transistor is formed. At this time, in the ion implantation for forming the source / drain diffusion layers 12, the thickness of the source / drain diffusion layers 12 is controlled to be substantially the same as the thickness of the gate electrode 30. Source / drain diffusion layer 12
After the formation of the resist, the resist is removed.

According to the above-described method of manufacturing a semiconductor device, the junction can be made shallow, the channel region is formed only in the portion immediately below the gate electrode, and the channel region is formed in the source / drain region. A field effect transistor that is formed in the depth direction of the side portion of the diffusion layer, can suppress the current from flowing two-dimensionally, and can suppress the roll-off in which the threshold voltage decreases rapidly when the gate length is less than a certain gate length. A semiconductor device having the same can be manufactured.
Since the fluctuation of the threshold voltage when the gate length is shortened can be suppressed, it is possible to use even a region where the gate length is short. In addition, a semiconductor device having a flat field-effect transistor capable of reducing a defocus margin for lithography by making the heights of gate and source / drain electrode outlets uniform can be manufactured.

Embodiment 2 FIG. 4 is a sectional view of a semiconductor device according to this embodiment. On the n-type silicon semiconductor substrate 10, a LO (not shown)
There is a region separated by a COS element isolation film, and a well 11 containing a p-type impurity is provided. It is surrounded by a gate insulating film 20 made of, for example, silicon oxide.
For example, it has a gate electrode 30 made of polysilicon.
Source / drain diffusion layers 12 containing an n-type impurity at a high concentration are provided on both sides of the gate electrode 30. The source / drain diffusion layer 12 is connected to the active region of the well 11 and has a thickness smaller than that of the gate electrode 30. The surfaces of the gate electrode 30, the source / drain diffusion layer 12, and the semiconductor substrate 10 are at substantially the same height and are flattened. The surface of the semiconductor substrate 10 is covered with a second insulating film 22, and a gate electrode outlet G and a source / drain electrode outlet SD are opened in the second insulating film 22.

In the semiconductor device having such a structure, the junction depth of the field-effect transistor can be made very shallow, roll-off can be suppressed, and fluctuation of the threshold voltage when the gate length is shortened. Is suppressed, and it is possible to use a region having a short gate length. Furthermore, since the side surface of the gate electrode can also be a channel formation region,
Even in a transistor having a short gate length, the effective channel length can be increased, which is advantageous for miniaturization and high integration of the device. In addition, since the surfaces of the gate electrode, the source / drain diffusion layers, and the surface of the semiconductor substrate have substantially the same height, they have flatness, so that a margin of defocus for lithography can be reduced.

The method of manufacturing the semiconductor device of the present embodiment is almost the same as the method of manufacturing the semiconductor device of the first embodiment. However, a step of forming the first insulating film by obliquely implanting oxygen ions into the n-type silicon semiconductor substrate 10 is omitted, and a step of forming the source / drain diffusion layers 12 by ion-implanting n-type impurities. In this case, the thickness of the source / drain diffusion layer 12 is controlled to be smaller than that of the gate electrode 30.

According to the above-described method for manufacturing a semiconductor device, by making the junction depth shallow, it is possible to suppress roll-off in which the threshold voltage is rapidly lowered when the gate length becomes less than a certain gate length.
Further, since the side surface of the gate electrode can also be used as a channel formation region, the effective channel length can be increased even in a transistor having a short gate length, and a field effect transistor which is advantageous for miniaturization and high integration of a device can be obtained. A semiconductor device having the same can be manufactured. Further, it is possible to manufacture a semiconductor device having a field-effect transistor having flatness capable of reducing a defocus margin for lithography.

Embodiment 3 FIG. 5 is a sectional view of a semiconductor device according to this embodiment. On a semiconductor substrate 10 having a p-type silicon semiconductor layer S as an upper layer of the insulating substrate I, there is a region separated from the substrate by a LOCOS element isolation film (not shown). A gate electrode 30 made of, for example, polysilicon, which is surrounded by a gate insulating film 20 made of, for example, silicon oxide, is embedded in the active region. On both sides of the gate electrode 30, a first insulating film 21 made of, for example, silicon oxide, which is thicker than the gate insulating film 20, is provided. On both sides thereof, a source / drain containing a high concentration of n-type impurities is provided. It has a diffusion layer 12. The source / drain diffusion layer 12 is connected to the active region of the p-type silicon semiconductor layer S, and has a thickness substantially equal to that of the gate electrode 30. The surfaces of the gate electrode 30, the source / drain diffusion layer 12, and the semiconductor substrate 10 are at substantially the same height and are flattened.

The semiconductor device having such a structure has an SOI structure having a semiconductor layer on an insulating film, and can have a complete element isolation structure capable of reducing the parasitic capacitance of the device. In addition, by reducing the depth of the junction, a semiconductor device including a field-effect transistor that can suppress roll-off in which the threshold voltage rapidly decreases when the gate length becomes equal to or less than a certain gate length can be manufactured. Also,
It is possible to manufacture a semiconductor device including a field-effect transistor having flatness capable of reducing a margin of defocus with respect to lithography.

The method of manufacturing the semiconductor device of the present embodiment is almost the same as the method of manufacturing the semiconductor device of the first embodiment. However, a stacked body of the insulating substrate I and the p-type silicon semiconductor layer S is used as the semiconductor substrate 10. Insulating substrate I
And a p-type silicon semiconductor layer S may be formed by depositing a semiconductor layer such as polysilicon on an insulating film by a CVD method or the like, a method of laminating an insulating film and a semiconductor layer, a method of SIMOX. A method of forming an insulating film on a semiconductor layer by ion implantation, a method of forming a semiconductor layer on an insulating film by epitaxial growth, or the like can be used.

According to the above-described method for manufacturing a semiconductor device, the semiconductor device has an SOI structure capable of achieving a complete element isolation structure capable of reducing the parasitic capacitance of the device, and the junction depth is reduced. Accordingly, it is possible to manufacture a semiconductor device having a field-effect transistor capable of suppressing roll-off in which the threshold voltage is rapidly reduced when the gate length is shorter than a certain gate length. Further, it is possible to manufacture a semiconductor device having a field-effect transistor having flatness capable of reducing a defocus margin for lithography.

Embodiment 4 FIG. 6 is a sectional view of a semiconductor device according to this embodiment. On a semiconductor substrate 10 having a p-type silicon semiconductor layer S as an upper layer of the insulating substrate I, there is a region separated from the substrate by a LOCOS element isolation film (not shown). A gate electrode 30 made of, for example, polysilicon, which is surrounded by a gate insulating film 20 made of, for example, silicon oxide, is buried in the active region. Source / drain diffusion layers 12 containing an n-type impurity at a high concentration are provided on both sides of the gate electrode 30. The source / drain diffusion layer 12 is connected to the active region of the p-type silicon semiconductor layer S, and has a thickness smaller than that of the gate electrode 30. Gate electrode 30, source / drain diffusion layer 12, and semiconductor substrate 10
Are approximately at the same height and are flattened.

The semiconductor device having such a structure has an SOI structure having a semiconductor layer on an insulating film, and can have a complete element isolation structure capable of reducing the parasitic capacitance of a device. In addition, by making the depth of the junction shallow, the roll-off in which the threshold voltage sharply drops below a certain gate length can be suppressed, and the side surface of the gate electrode can also be used as a channel formation region. This is a semiconductor device having a field-effect transistor which can increase the effective channel length even with a transistor having a short structure and is advantageous for miniaturization and high integration of the device.
Further, the present invention is a semiconductor device including a field-effect transistor having flatness capable of reducing a defocus margin for lithography.

The method of manufacturing the semiconductor device of the present embodiment is almost the same as the method of manufacturing the semiconductor device of the second embodiment. However, a stacked body of the insulating substrate I and the p-type silicon semiconductor layer S is used as the semiconductor substrate 10. Insulating substrate I
And a p-type silicon semiconductor layer S may be formed by depositing a semiconductor layer such as polysilicon on an insulating film by a CVD method or the like, a method of laminating an insulating film and a semiconductor layer, a method of SIMOX. A method of forming an insulating film on a semiconductor layer by ion implantation, a method of forming a semiconductor layer on an insulating film by epitaxial growth, or the like can be used.

According to the method of manufacturing a semiconductor device described above, the semiconductor device has an SOI structure capable of achieving a complete element isolation structure capable of reducing the parasitic capacitance of the device, and the junction depth is reduced. This makes it possible to suppress the roll-off in which the threshold voltage drops sharply below a certain gate length, and furthermore, the side surface of the gate electrode can also be used as a channel formation region, so that the effective channel length can be reduced even in a transistor having a short gate length. And a semiconductor device having a field-effect transistor that is advantageous for miniaturization and high integration of the device can be manufactured. Further, it is possible to manufacture a semiconductor device having a field-effect transistor having flatness capable of reducing a defocus margin for lithography.

Embodiment 5 FIG. 7 is a sectional view of a semiconductor device of this embodiment. On a semiconductor substrate 10 having a p-type silicon semiconductor layer S as an upper layer of the insulating substrate I, there is a region separated from the substrate by a LOCOS element isolation film (not shown). A gate electrode 30 made of, for example, polysilicon, which is surrounded by a gate insulating film 20 made of, for example, silicon oxide, is embedded in the active region. On both sides of the gate electrode 30, a first insulating film 21 made of, for example, silicon oxide, which is thicker than the gate insulating film 20, is provided. It has a diffusion layer 12. The source / drain diffusion layer 12 is connected to the active region of the p-type silicon semiconductor layer S, and has a thickness substantially equal to that of the gate electrode 30. The surfaces of the gate electrode 30, the source / drain diffusion layer 12, and the semiconductor substrate 10 are at substantially the same height and are flattened.

Further, the semiconductor device of the present embodiment has a lower gate insulating film 20 ′ made of, for example, silicon oxide in a layer below a channel forming region (p-type silicon semiconductor layer) below the gate electrode 30. A lower gate electrode 30 'made of, for example, polysilicon is provided in a lower layer, and a lower first insulating film 21' made of, for example, silicon oxide, which is thicker than the gate insulating film 20 ', is formed on both sides of the lower gate electrode 30'. And a lower source / drain diffusion layer 12 ′ connected to a channel forming region containing an n-type impurity at a high concentration on both sides thereof.

The above-described semiconductor device of this embodiment has a field effect transistor having a double gate structure which is paired up and down. It is possible to provide a transistor whose operation can be easily controlled, for example, in which the upper gate electrode and the lower gate electrode handle a change in drain current and a steady current, respectively.

Further, the semiconductor device of this embodiment has an SOI structure having a semiconductor layer on an insulating film, and has a complete element isolation structure capable of reducing the parasitic capacitance of the device. it can. In addition, the present invention is a semiconductor device including a field-effect transistor that can suppress roll-off in which a threshold voltage is sharply reduced when a gate length becomes equal to or less than a certain gate length by reducing a junction depth. Further, the present invention is a semiconductor device including a field-effect transistor having flatness capable of reducing a defocus margin for lithography.

A method for manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 8A, a lower gate electrode 30 'and a lower gate insulating film 20' are formed in a p-type silicon semiconductor layer S by a method similar to the method of manufacturing the semiconductor device of the first embodiment. , Lower first insulating film 21 ′, and lower source / drain diffusion layer 1 containing n-type impurities at a high concentration
2 ′ is formed to form a lower field-effect transistor embedded in the p-type silicon semiconductor layer S. Next, the surface on which the field effect transistor is formed is polished by, for example, the CMP method or the like, and is planarized.

Next, as shown in FIG. 8B, the insulating substrate I is adhered by heat treatment so as to cover the surface on which the above-mentioned field-effect transistor is formed, so that the SOI structure is formed. Form. Next, the surface of the p-type silicon semiconductor layer S is polished by a CMP method or the like, or is etched back so that the thickness of the p-type silicon semiconductor layer S becomes a desired thickness.

Next, the p-type silicon semiconductor layer S is formed on the surface of the p-type silicon semiconductor layer S opposite to the surface on which the insulating substrate I is bonded by the same method as the method of manufacturing the semiconductor device of the first embodiment. Inside the gate electrode 30, the gate insulating film 20, the first
An insulating film 21 and a source / drain diffusion layer 12 containing an n-type impurity at a high concentration are formed, and the lower gate electrode 30 ′ and the lower electrode 30 ′ of the previously formed lower field effect transistor are opposed to each other. A field effect transistor buried in the p-type silicon semiconductor layer S is formed to form the semiconductor device shown in FIG.

According to the above-described method for manufacturing a semiconductor device, there is provided a field effect transistor having a double gate structure which is paired up and down. It is possible to manufacture a semiconductor device having a transistor whose operation is easy to control, such that the upper gate electrode and the lower gate electrode take charge of a change in drain current and a steady component, respectively. In addition, it has an SOI structure that can be a complete element isolation structure that can reduce the parasitic capacitance of the device, etc., and by reducing the depth of the junction, the threshold voltage sharply drops below a certain gate length. It is possible to manufacture a semiconductor device including a field-effect transistor having flatness capable of suppressing the roll-off to be reduced and reducing the margin of defocus for lithography.

Embodiment 6 FIG. 9 is a sectional view of a semiconductor device according to this embodiment. On a semiconductor substrate 10 having a p-type silicon semiconductor layer S as an upper layer of the insulating substrate I, there is a region separated from the substrate by a LOCOS element isolation film (not shown). A gate electrode 30 made of, for example, polysilicon, which is surrounded by a gate insulating film 20 made of, for example, silicon oxide, is embedded in the active region. Source / drain diffusion layers 12 containing an n-type impurity at a high concentration are provided on both sides of the gate electrode 30. The source / drain diffusion layer 12 is connected to the active region of the p-type silicon semiconductor layer S, and has a thickness smaller than that of the gate electrode 30. The surfaces of the gate electrode 30, the source / drain diffusion layer 12, and the semiconductor substrate 10 are at substantially the same height and are flattened.

Further, the semiconductor device of this embodiment has a lower gate insulating film 20 ′ made of, for example, silicon oxide below the channel forming region (p-type silicon semiconductor layer) below the gate electrode 30. A lower gate electrode 3 made of, for example, polysilicon is formed below the lower gate insulating film 20 '.
0 ′, and a lower source / drain diffusion layer 12 ′ connected to a channel forming region containing a high concentration of n-type impurities on both sides of the lower gate electrode 30 ′.

The semiconductor device of this embodiment has a double gate type field effect transistor which is paired up and down, and the change in the drain current and the steady state are determined by the upper gate electrode and the lower gate electrode. A transistor whose operation can be easily controlled, for example, can be provided. In addition, the semiconductor device has an SOI structure in which a semiconductor layer is provided above the insulating film, so that a complete element isolation structure in which parasitic capacitance of a device can be reduced can be obtained. In addition, by making the depth of the junction shallow, the roll-off in which the threshold voltage sharply drops below a certain gate length can be suppressed, and the side surface of the gate electrode can also be used as a channel formation region. This is a semiconductor device having a field-effect transistor which can increase the effective channel length even with a transistor having a short structure and is advantageous for miniaturization and high integration of the device. Further, the present invention is a semiconductor device including a field-effect transistor having flatness capable of reducing a defocus margin for lithography.

A method for manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 10A, a polysilicon layer is deposited on the upper layer of the insulating substrate I by, for example, a CVD method, and is patterned to form a lower gate electrode 30 ′.
To form Next, a lower gate insulating film 20 'made of silicon oxide is formed by covering the lower gate electrode by, for example, thermal oxidation. Next, for example, polysilicon is deposited on the entire surface by a CVD method and patterned by etching to form a lower source / drain diffusion layer 12 ′ containing an n-type impurity at a high concentration. Form the lower field effect transistor.

Next, as shown in FIG. 10B, a polysilicon containing a p-type impurity is deposited on the entire surface by, for example, a CVD method to cover the field effect transistor.
Type silicon semiconductor layer S is formed to have an SOI structure. A p-type silicon semiconductor layer can also be formed by epitaxial growth. Next, the surface of the p-type silicon semiconductor layer S is polished by a CMP method or the like, or is etched back so that the p-type silicon semiconductor layer S has a desired thickness.

Next, a gate electrode 30, a gate insulating film 20, and a gate insulating film 20 are formed in the p-type silicon semiconductor layer S on the deposited p-type silicon semiconductor layer S in the same manner as in the method of manufacturing the semiconductor device of the second embodiment. And a source / drain diffusion layer 12 containing a high concentration of n-type impurities. At this time, the lower gate electrode 3 of the previously formed lower field effect transistor is formed.
0 ′ and the gate electrode 30 are positioned so as to face each other.
A field effect transistor embedded in the silicon semiconductor layer S is formed to form the semiconductor device shown in FIG.

According to the above-described method of manufacturing a semiconductor device, a field effect transistor having a double-gate structure vertically paired is provided. It is possible to manufacture a semiconductor device having a transistor whose operation is easy to control, such that the upper gate electrode and the lower gate electrode take charge of a change in drain current and a steady component, respectively. In addition, it has an SOI structure that can be a complete element isolation structure that can reduce the parasitic capacitance of the device, etc., and by reducing the depth of the junction, the threshold voltage sharply drops below a certain gate length. The roll-off that decreases can be suppressed, and the side surface of the gate electrode can also be used as a channel formation region, so that the effective channel length can be increased even in a transistor having a short gate length, so that the device can be miniaturized and highly integrated. A semiconductor device having a field-effect transistor that is advantageous for fabrication can be manufactured. Further, it is possible to manufacture a semiconductor device having a field-effect transistor having flatness capable of reducing a defocus margin for lithography.

When the semiconductor device of the present invention is applied to a TFT structure, it can be applied to a normal TFT structure in which an amorphous silicon layer or a polysilicon layer is formed on an insulating film. In addition, the semiconductor device and the method for manufacturing the same of the present invention can be applied to any semiconductor device having a field effect transistor.
The present invention can be applied to a semiconductor storage device such as a RAM, an FRAM, and a ROM, a semiconductor device such as a logic A / D converter, and other semiconductor devices.

The semiconductor device and the method of manufacturing the same according to the present invention
It is not limited to the above embodiment. For example, in this embodiment, a semiconductor device having an n-channel field effect transistor structure is described. However, instead of a p-substrate or p-well, a p-channel type electric field effect transistor is formed in an n-substrate or an n-well in a p-substrate. An effect transistor structure may be used. In a semiconductor device having an n-channel transistor structure and a semiconductor device having a p-channel transistor structure, n-type impurities and p-type impurities may be exchanged. In addition, as the source / drain region, a metal electrode or the like can be used in addition to a diffusion layer in which a conductive impurity is diffused in a silicon semiconductor layer.

The gate electrode and the lower gate electrode in the double gate structure have a single-layer structure, but may have two or more layers such as polycide. In the present embodiment,
Although the structure and the manufacturing method of the silicon semiconductor according to the embodiment have been described, the present invention can be similarly applied to germanium and a compound semiconductor. In addition, various changes can be made without departing from the spirit of the present invention.

[0069]

According to the semiconductor device of the present invention, the junction depth of the field-effect transistor can be made very shallow, and the roll-off in which the threshold voltage drops sharply below a certain gate length can be suppressed. Therefore, fluctuation of the threshold voltage when the gate length is shortened can be suppressed, and it is possible to use even a region where the gate length is short. In addition, since the surface of the gate electrode, the source / drain diffusion layer and the surface of the semiconductor substrate can be made substantially the same height, the height of the source / drain electrode outlets is made uniform to have flatness and defocus for lithography. Can be reduced.

Further, according to the method of manufacturing a semiconductor device of the present invention, by making the junction depth shallow, it is possible to suppress the roll-off in which the threshold voltage drops sharply below a certain gate length, thereby reducing the gate length. Since the fluctuation of the threshold voltage at the time of formation can be suppressed, a semiconductor device having a field-effect transistor that can be used up to a region having a short gate length can be manufactured. In addition, a semiconductor device having a flat field-effect transistor capable of reducing a defocus margin for lithography by making the heights of gate and source / drain electrode outlets uniform can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention. FIG. 2A is a diagram illustrating a process of forming a well, FIG. 2B is a diagram illustrating a process of forming a trench, and FIG. The steps up to the step of forming a gate insulating film are shown.

FIG. 3 shows a step that follows the step shown in FIG. 2;
(E) shows up to the step of forming an insulating film and up to the step of forming a gate electrode.

FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

8A and 8B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention. FIG. 8A is a diagram illustrating a process of forming a lower field-effect transistor, and FIG. 8B is a diagram illustrating an insulating film and a semiconductor layer. Up to the step of bonding together.

FIG. 9 is a sectional view of a semiconductor device according to a sixth embodiment of the present invention.

FIGS. 10A and 10B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention. FIG. 10A is a diagram illustrating a process of forming a lower field-effect transistor, and FIG. Up to

FIG. 11 is a sectional view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 11 ... Well, 12 ... Source / drain diffusion layer, 12 '... Lower source / drain diffusion layer, 2
0: gate insulating film, 20 ′: lower gate insulating film, 21:
1st insulating film, 21 '... lower 1st insulating film, 22 ... 2nd insulating film, 30 ... gate electrode, 30' ... lower gate electrode, T ...
Gate trench, G: Gate electrode outlet, SD ...
Source / drain electrode outlet, I ... insulating substrate, S
... Semiconductor layer.

Claims (19)

[Claims] A semiconductor substrate having a channel forming region; a gate electrode disposed in the semiconductor substrate from the channel forming region via a gate insulating film; and a gate electrode formed in a trench shape in the semiconductor substrate; A source / drain region disposed in the semiconductor substrate via an insulating film and connected to the channel formation region, wherein the thickness of the source / drain region is substantially equal to or less than the thickness of the gate electrode; A semiconductor device having a field-effect transistor capable of flowing a current to the source / drain region through a channel region formed in the channel formation region by applying a predetermined voltage to the gate electrode. 2. The semiconductor device according to claim 1, wherein said gate electrode, said source / drain region and said semiconductor substrate have substantially the same height. 3. The semiconductor device according to claim 1, wherein the thickness of the source / drain region is smaller than the thickness of the gate electrode, and a channel formation region is provided below and on both sides of the gate electrode. 4. The semiconductor device according to claim 1, wherein the semiconductor device is formed on an insulating film formed on the semiconductor substrate. 5. A lower gate insulating film under the channel forming region below the gate electrode, a lower gate electrode under the lower gate insulating film, 2. The semiconductor device according to claim 1, further comprising lower source / drain regions connected to said channel forming region on both sides and having a thickness substantially equal to or less than a thickness of said lower gate electrode. 6. The semiconductor device according to claim 5, wherein said gate electrode, said source / drain region and said semiconductor substrate have substantially the same height. 7. The semiconductor device according to claim 5, wherein the thickness of the source / drain region is smaller than the thickness of the gate electrode, and a channel formation region is provided below and on both sides of the gate electrode. 8. The semiconductor device according to claim 5, wherein the semiconductor device is formed on an insulating film formed on the semiconductor substrate. 9. A step of forming a trench-shaped recess for a gate electrode in a semiconductor substrate, a step of forming a gate insulating film on an inner wall surface of the recess for a gate electrode, and embedding a conductor in the recess for a gate electrode. Forming a gate electrode; and forming source / drain regions having a thickness substantially equal to or less than the thickness of the gate electrode in the semiconductor substrate on both sides of the gate electrode. Production method. 10. The semiconductor according to claim 9, wherein said step of forming a gate electrode by embedding a conductor in said gate electrode recess includes forming a gate electrode having substantially the same height as the surface of said semiconductor substrate. Device manufacturing method. 11. A step of forming an insulating film thicker than the gate insulating film on the side wall of the recess for the gate electrode after the step of forming the gate insulating film and before the step of forming the gate electrode. A method for manufacturing a semiconductor device according to claim 9. 12. The method of manufacturing a semiconductor device according to claim 9, wherein said step of forming said source / drain region is a step of forming said source / drain region with a smaller thickness than said gate electrode. 13. The method of manufacturing a semiconductor device according to claim 9, further comprising a step of forming a laminated body of an insulating film and a semiconductor layer to form the semiconductor substrate before the step of forming the concave portion for the gate electrode in the semiconductor substrate. Method. 14. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming a stacked body of the insulating film and the semiconductor layer is a step of bonding the insulating film and the semiconductor layer. 15. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming a stacked body of the insulating film and the semiconductor layer is a step of forming an insulating film by ion implantation into the semiconductor layer. 16. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming a stacked body of the insulating film and the semiconductor layer is a step of forming a semiconductor layer on the insulating film by epitaxial growth. 17. A step of forming a trench-shaped lower gate electrode recess in a semiconductor layer before the step of forming a gate electrode recess in the semiconductor substrate; and forming an inner wall surface of the lower gate electrode recess in the semiconductor layer. Forming a lower gate insulating film; forming a lower gate electrode by embedding a conductor in the lower gate electrode recess; and forming the lower gate electrode in a semiconductor substrate on both sides of the lower gate electrode. Forming a lower source / drain region having a thickness substantially equal to or less than the thickness of the gate electrode, and forming an insulating film on a surface on which the lower gate electrode is formed on the semiconductor layer; The method for manufacturing a semiconductor device according to claim 9, further comprising: forming a substrate. 18. The step of forming a lower gate electrode by embedding a conductor in the lower gate electrode recess includes forming a lower gate electrode having substantially the same height as the surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 17. 19. A step of forming a lower gate electrode on an insulating film before the step of forming a recess for a gate electrode in the semiconductor substrate; and forming a lower gate insulating film on an upper layer of the lower gate electrode. Forming a lower source / drain region having a thickness substantially equal to or less than the thickness of the lower gate electrode on both sides of the lower gate electrode; and 10. The method of manufacturing a semiconductor device according to claim 9, further comprising: forming a semiconductor layer on the entire surface by covering the lower source / drain region to form the semiconductor substrate.