JPH10290001A - Gate turn-off thyristor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase in processing cost and to obtain a large capacitance element having large interruption strength by a method wherein the region where an N-emitter region, which comes in contact with a cathode electrode, is projected on anode surface, is prevented from overlapping on a P-emitter region which comes in contact with an anode electrode. SOLUTION: The ninth ring segment 49 has a P-emitter layer 11 overlapping on the region where an N-emitter layer 8 is projected on anode surface, and the region other than the tenth ring has the same structure as the ninth ring. On the other hand, in the tenth ring segment 410, an N<+> layer 12 is provided instead of having no P-emitter layer on the region where the N-emitter layer 8 is projected on the anode surface. In this element, the P-emitter layer is not provided, and the tenth ring is not thyristor-operated. As a result, current concentration is not generated on the tenth ring even when the difference in pressure in the ring is large. As the difference in pressure is small in the ninth ring, the degree of current concentration becomes small, and an operation locus comes to a standstil in a safety region, and the element is not broken.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate turn-off thyristor (hereinafter, abbreviated as GTO), and more particularly to a GTO suitable for a large-capacity application.

[0002]

2. Description of the Related Art In the fields of transportation, industry, electric power, and the like, there is a strong demand for a GTO as a key device to have a large capacity and a high frequency. Of these, operating at higher frequencies is severely limited by the heat generated during switching of the elements.
A GTO that solves this problem and enables high-frequency operation is described in Japanese Patent Application Laid-Open No. 7-22609.

[0003] Generally, the GTO has a disk shape, and a gate electrode having a circular pattern is arranged at the center of the circle. The segments, which are unit units for supplying a load current, are arranged on a plurality of concentric circles sharing the center with the element. A set of many segments on one concentric circle is hereinafter called a ring. The segment has a cathode electrode on one side,
An anode electrode is provided on the opposite surface. To apply a load current, the element is sandwiched between a cathode electrode plate and an anode electrode plate that are in contact with each electrode, and the element and the electrode plate are sandwiched between a pair of external electrode blocks, and are supported in a pressurized contact state. In the above-mentioned Japanese Patent Application No. Hei 7-22609, it is described that the diameter of the block-shaped external electrode is smaller than that of each electrode plate in order to prevent stress concentration on the semiconductor substrate when pressurized. . If the diameter of the block-shaped external electrode is larger than each electrode plate, the pressure from the peripheral portion of the block-shaped external electrode is concentrated on the outermost ring, and the contact pressure on the outermost periphery is increased. The peripheral pressure is dispersed around the electrode plate, eliminating the problem of stress concentration. However, since the diameter of the block electrode is small, the heat radiation effect is low around the element. As a feature of this conventional technique, the outer diameter of the p-emitter layer is smaller than the outer diameter of the n-emitter layer, and the current density in the periphery of the element is smaller than that in the inner periphery. Thus,
Heat generation in the peripheral portion of the element was suppressed, and turn-off failure in the peripheral portion was eliminated even when the frequency was increased.

[0004]

It has been found that when the element is increased in capacity or area by using the prior art, stress concentration due to factors other than those described in connection with the prior art becomes dominant. . This will be described below.

[0005] The two surfaces, front and back, which receive the pressure of the electrode plate in contact with the electrodes of the element, are not completely parallel due to processing errors. Due to this parallelism error, the thickness of the electrode plate is different at each position, the thickness is maximum at a certain position on the periphery of the electrode plate, and is minimum at another position on the periphery. become. When the element is pressurized, the stress increases at a portion where the position of the electrode plate is thick, and the stress increases at a portion where the electrode plate is thin. Therefore, when the element is pressurized, the pressure difference tends to increase in the segment in the outermost ring that is pressed through the outermost peripheral portion of the electrode plate. Also, the pressure tends to be the highest in the segment in the outermost ring. Actually, such stress non-uniformity is caused not only by the electrode plate but also by the parallelism error of the pressing surfaces of the external electrodes and the elements, etc., but only the parallelism error of the electrode plate is considered. The idea is the same as in the case.

When the element is energized, the segment with a small pressure has a small amount of carriers inside the element and the turn-off is fast, whereas the segment with a large pressure has a large amount of carriers inside the element and the turn-off is slow. Since the outermost ring is farthest from the gate, the off-gate current hardly flows at the time of turn-off, and the turn-off is delayed most, that is, the current concentration is apt to occur. Current concentration occurs and turn-off failure occurs. This current concentration has limited the blocking withstand capability of the entire device. As the element has a larger area, the difference in thickness at the outermost peripheral portion of the surface caused by an error in the parallelism of the pressing surface increases, and the pressure difference inside the outermost peripheral ring also increases. Increasing the accuracy of the parallelism between the electrode plate and the external electrode block can further improve the blocking resistance of the element, but this increases the processing cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a large-capacity element having a large blocking resistance while allowing a larger error in the parallelism of the pressurized surface and suppressing the processing cost.

[0008]

In order to achieve the above object, in the segment of the outermost ring, a region where an n emitter region in contact with a cathode electrode is projected on an anode surface does not overlap with a p emitter region in contact with the anode electrode. To do.

Particularly, in the intermediate ring gate element having a ring-shaped gate electrode, the above-described positional relationship between the n emitter region and the p emitter region may be applied to the segment of the innermost ring.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments. FIG. 1 shows a first embodiment of the present invention. It is a 6 kV, 6 kA class device. (A), (b), (c)
Shows a plan view of the entire device, a cross-sectional view and a plan view near the outermost peripheral ring, and a cross-sectional view of a state where the device is incorporated in a package. 1 is an element and 2 is a gate electrode. It is a center gate type device having a gate electrode 2 at the center of the device. Reference numeral 3 denotes a ring formed by arranging a large number of segments radially, and this element has ten rings. Hereinafter, the rings near the center are referred to as a first ring, a second ring,..., A tenth ring.

The segments in these rings are operated in parallel to supply a large current of 6 kA. 49 is a segment of the ninth ring, and 410 is a segment of the tenth ring. The dimension of the segment is about 3 mm in the longitudinal direction and about 0.2 mm in the direction perpendicular to the longitudinal direction. Reference numeral 5 denotes a cathode electrode, reference numeral 6 denotes an anode electrode, reference numeral 7 denotes a gate wiring layer, which is provided so as to surround the segment, and is connected to the gate electrode at the center of the device. Although not shown in the figure, ap + layer for providing an ohmic contact to the gate wiring layer 7 is provided in contact with the gate wiring layer 7. 8 is an n-emitter layer for injecting electrons, 9 and 10 are p-base and n-base layers for blocking anode voltage, 11 is a p-emitter layer for injecting holes, and 12 is for obtaining an anode short-circuit structure. It is a high concentration n-type layer. Reference numeral 13 denotes an RTV resin for obtaining the withstand voltage of the end face.

Reference numeral 14 denotes a cathode electrode plate in contact with the cathode electrode 5, 15 denotes a cathode external electrode, 16 denotes an anode electrode plate in contact with the anode electrode 6, 17 denotes an anode external electrode, and 20 denotes a cathode external electrode. This is a cylindrical insulating ring for insulating the anode external electrode 17. Reference numeral 18 denotes a gate electrode plate in contact with the gate electrode 2, and 19 denotes a gate lead.

The structure which is a feature of the present invention will be described with reference to FIG. The segment 49 of the ninth ring has the p emitter layer 11 so as to overlap the region where the n emitter layer 8 is projected on the anode surface, and has the same structure as that of the ninth ring except for the tenth ring. On the other hand, in the segment 410 of the tenth ring, there is no p-emitter layer in the region where the n-emitter layer 8 is projected on the anode surface, and instead the n + layer 1
2 are provided. In this element, the p-emitter layer is eliminated in the segment 410 of the tenth ring, and the thyristor operation of the tenth ring is prevented. Note that G
In order not to lose the large current carrying function as the TO, the total area (number) of the segments located at the outermost periphery is one of the total area (number) of the segments located inside the outermost periphery.
/ 2 or less.

Here, a problem which has occurred in the conventional structural element will be described.

FIG. 8A shows the structure of a conventional example of Japanese Patent Application Laid-Open No. 7-22609. A plan view of the entire device and a cross-sectional view in a state where the device is incorporated in a package are the same as those in FIG. The structure of the segment 49 of the ninth ring is shown in FIG.
1B, except that the tenth segment 410 has a p-emitter layer 11 so as to overlap a region where the n-emitter layer 8 is projected on the anode surface.
It is different from (b). Because of the p-emitter layer 11, the segment 410 also performs a thyristor operation.

FIG. 2B shows a pressure distribution in the ring when the conventional element is pressurized. The horizontal axis indicates the position in the circumferential direction by an angle. The tenth ring has a larger pressure difference than the ninth ring. The reason why such a distribution occurs will be described below. The two surfaces, front and back, which receive the pressure of the electrode plate in contact with the electrodes of the element, are not completely parallel due to processing errors. Due to this parallelism error, the thickness of the electrode plate is different at each position, the thickness is maximum at a certain position on the periphery of the electrode plate, and is minimum at another position on the periphery. become. When the element is pressurized, the stress increases at a portion where the position of the electrode plate is thick, and the stress increases at a portion where the electrode plate is thin. Therefore, when the element is pressurized, the pressure difference tends to increase in the segment in the outermost ring that is pressed through the outermost peripheral portion of the electrode plate. Also, the pressure tends to be the highest in the segment in the outermost ring. Actually, such pressure non-uniformity is caused by a combination of parallelism errors of not only the electrode plates but also the pressing surfaces of external electrodes, elements, etc., but only the parallelism errors of the electrode plates are considered. The idea is the same as in the case.

FIG. 3C shows a current turn-off waveform of a conventional segment. Regarding the tenth ring, the segment having the maximum pressure in (b) is shown. In the segment of the tenth ring, a large current flows in a conductive state due to a large pressure, and since the amount of injected carriers is large, the turn-off is delayed from the other segments of the tenth ring, and the peak current Ip is large. High current concentration.

(D) shows a voltage / current locus at the time of turning off the segment. A voltage / current region in which this segment can operate without breaking, that is, a safe operation region is also shown. Since the peak current Ip is large, when the anode voltage suddenly jumps, that is, when the spike voltage Vdsp is generated, the operation trajectory exceeds the safe operation area and is easily broken. For this reason, it cannot be used under circuit conditions where a large spike voltage Vdsp is generated. To alleviate this current concentration, the accuracy of the parallelism of the pressurized surfaces such as the electrode plate and the external electrodes may be increased, but the processing cost is increased. A device that can withstand a large spike voltage Vdsp at lower cost is desirable.

Next, returning to FIG. 1, the effect of the present invention will be described. In this element, since the thyristor operation is not performed on the segment 410 of the tenth ring, current concentration does not occur in the tenth ring even if the pressure difference within the ring is large. At the time of turn-off, current concentration occurs in the segment 49 of the ninth ring. In the ninth ring, the degree of current concentration is small because the size difference is small in the ring, so that even if a large spike voltage Vdsp occurs, the operation trajectory is safe. The device stays in the region and does not break down. Moreover, compared to the conventional example, it is not necessary to increase the precision of the parallelism of the pressurized surfaces of the electrode plates, external electrodes, and the like in order to improve the blocking resistance. As a result, the spike voltage Vdsp is several hundred volts higher than the conventional structure.
A device that can withstand the above can be achieved at low cost.

Hereinafter, another embodiment of the present invention will be described. Since the third embodiment has many points in common with the first embodiment, the following description focuses on the differences from the first embodiment.

FIG. 2 shows a second embodiment of the present invention.

FIG. 3A shows a cross-sectional view and a plan view near the outermost peripheral ring. In the segment 49 of the ninth ring, p is set so that it overlaps the region where the n emitter layer 8 is projected on the anode surface.
An emitter layer 11 is provided.
It has the same structure as the ring. On the other hand, in the segment 410 of the tenth ring, there is no p-emitter layer in the region where the n-emitter layer 8 is projected on the anode surface, and instead the n + layer 12
Is provided. The difference from the first embodiment is that the distance L between the segment 49 of the ninth ring and the segment 410 of the tenth ring is adjusted in a conductive state, and the p-emitter layer of the segment 49 is indicated by the dotted arrow in the drawing. This means that holes are injected from 11 to the n emitter of the segment 410 to perform a thyristor operation. At this time, since the p emitter and the n emitter are far apart, the carrier injection amount is small, and the current flowing through the segment 410 is small. (B) shows the current turn-off waveform of the segment. As for the tenth ring, the segment having the maximum pressure is shown. In the segment of the tenth ring, the pressure is large but the current at the time of conduction is kept small and the amount of injected carriers is small, so that the delay of turn-off from other segments is small and the peak current Ip is kept small. That is, the degree of current concentration is small.

FIG. 3C shows a voltage / current locus at the time of turning off the segment. The safe operation area of this segment is also shown. In the segment 410, the p emitter layer 11
Since the distance to the thyristor is long and the hole injection amount is small, the thyristor is less likely to reignite even when current is concentrated at the time of turn-off, that is, the safe operation area is wider than that of the conventional example of FIG. Further, the peak current Ip is small. Due to these effects, even in the operation under the same circuit conditions as in FIG. 8C, the operation trajectory is within the safe operation area with a large margin. Compared to the first embodiment, the ninth ring and the tenth ring
Since the collective current at the time of turn-off flows together with the ring, the withstand voltage is greater. An element that can withstand a spike voltage Vdsp about 1 kV higher than the conventional structure can be achieved at low cost. Since the current flowing through the segment 410 is small, there is no problem of temperature rise around the element.

FIG. 3 shows a third embodiment of the present invention. It shows a sectional view and a plan view near the outermost peripheral ring. The segment 41 of the tenth ring as in the second embodiment of FIG.
0 is operated as a thyristor. The difference from the second embodiment is that a p-emitter 11 'is provided at the periphery of the device, and a thyristor current flows from here. As compared with the second embodiment, the distribution of the concentrated current of the tenth ring at the time of turn-off was increased, and the withstand voltage was higher. In this example, the peripheral p-emitter 11 'is provided in an annular shape, but there are various other methods such as an intermittent one. Since the current flowing through the segment 410 is small, there is no problem of temperature rise around the element.

FIG. 4 is a plan view showing a device according to a fourth embodiment of the present invention. Unlike the first embodiment shown in FIG. 1, this is a so-called intermediate ring gate type element in which an annular gate is provided so as to be sandwiched between rings. In this type of element, current concentration in the innermost first ring also poses a problem. The reason is first
That is, the ring is far from the gate electrode 2, the first ring has a small number of segments, and stress concentration on the first ring is inevitable due to the structure of the external block electrode.
In order to avoid these problems, in this device, a structure which is a feature of the present invention, that is, a structure in which the p emitter layer is not provided in a region where the n emitter layer is projected on the anode surface, is applied to the segment of the first ring. The intermediate ring gate type element is
Since the gate wiring in the device is short, the structure is expected to have high withstand voltage. By applying the present invention, a device that can withstand a spike voltage Vdsp higher than the device of the conventional structure by 1 kV or more is obtained. Since the p-emitter was eliminated in the first ring having a small number of segments, the increase of the on-voltage due to the application of the present invention was small. Even when the current concentration of the outermost outermost tenth ring becomes a problem even in an intermediate ring gate type element, the present invention may be applied to the tenth ring. Alternatively, the first ring, the first
The present invention may be applied to both O-rings.

FIG. 5 shows the structure near the outermost peripheral ring of the device according to the fifth embodiment of the present invention. This is the case of a center gate type device. The segment of the tenth ring in the first embodiment of FIG.
In one ring segment 411, there is no p-emitter layer in the area where the n-emitter layer 8 is projected on the anode surface.
+ Layer 12 is provided. The length of the tenth ring segment 410 in the longitudinal direction is about 2 mm, and the length of the eleventh ring segment 411 in the longitudinal direction is about 1 mm. p
Since the area from which the emitter layer was removed was small, the increase in the on-voltage due to the application of the present invention was small. This method is particularly effective when stress concentration occurs only in a narrow portion near the outer peripheral portion in the segment due to the influence of warpage of the electrode plate and the like.

FIG. 6 is a sectional view showing the vicinity of the outermost peripheral ring of the element according to the sixth embodiment of the present invention. This is an element having a so-called punch-through structure. The n-buffer layer 21 having a higher impurity concentration than the n-base layer 10 is used to maintain the breakdown voltage and reduce the impurity concentration of the n-base layer 10 to reduce the thickness, thereby reducing the loss. Has been realized. Segment 410 of the 10th ring
Thus, the p-emitter layer is not provided in the region where the n-emitter layer 8 is projected on the anode surface, and the n @ + layer 12 is provided instead.

FIG. 7 shows a device (SW ₁₁ , S ₁₁₎ of the first embodiment.
An example of a motor drive inverter configured using W ₁₂ , SW ₂₁ , SW ₂₂ , SW ₃₁ , and SW ₃₂ ) as switching elements will be described. Two switching elements (eg, SW ₁₁ and S
W ₁₂₎ there is one phase of the inverter units are connected in series is constituted. A freewheel diode FD is connected to each switching element in anti-parallel. Furthermore, a so-called snubber circuit S is connected to each switching element in parallel to protect the switching element from a sharp rise in voltage. In this snubber circuit, a capacitor SC is connected in series to a parallel circuit of a diode SD and a resistor SR. The series connection points of the two switching elements in each phase are AC terminals T ₃ , T ₄ , T
Connected to ₅ . A three-phase induction motor is connected to each AC terminal. The anode of the switching element on the upper arm side is 3
Pieces with a common, are connected to the high potential side of the DC voltage source in series with the terminal T _1. The cathode of the switching element on the lower arm side is common to all three, and the series terminal T ₂
Is connected to the low potential side of the DC voltage source. In the device having such a configuration, DC is converted into AC by each switching operation, and the three-phase induction motor is driven. A gate circuit for controlling the switching operation is connected between the gate and the cathode of each switching element of the upper and lower arms. According to the present invention, an element having high withstand voltage can be realized, so that the capacitance of the capacitor SC of the snubber circuit can be significantly reduced. As a result, lower loss, higher frequency, downsizing and simplification of the device than before were realized. Moreover, they could be realized at low cost.

[0029]

As described above, according to the present invention, since the current concentration caused by the non-uniform pressure in the ring in the ring far from the gate can be suppressed, it is possible to realize a high blocking capability mainly in a large capacity element. That is, the allowable spike voltage can be increased by about 1 kV. Moreover, this can be realized without increasing the processing accuracy of the electrode component, that is, at low cost.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention.

FIG. 2 shows a second embodiment of the present invention.

FIG. 3 shows a third embodiment of the present invention.

FIG. 4 shows a fourth embodiment of the present invention.

FIG. 5 shows a fifth embodiment of the present invention.

FIG. 6 shows a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram of a motor drive inverter using the element of the present invention.

FIG. 8 shows a device according to the prior art.

[Explanation of symbols]

11 ... p emitter layer, 49 ... segment of inner ring (first to ninth rings), 410 ... segment of outermost ring (tenth ring).

Claims (2)

[Claims] 1. A disk-shaped semiconductor as a base, having a first main surface and a second main surface, a second main surface having a projection,
A first electrode on the first main surface, a second electrode on the second main surface protrusion, a third electrode on the second main surface, a first conductivity type adjacent to the first electrode. A first semiconductor region, a second semiconductor region of the second conductivity type adjacent to the first semiconductor region, a third semiconductor region of the second conductivity type adjacent to the second electrode, and adjacent to the third electrode A fourth semiconductor region of the first conductivity type, a second semiconductor region, a third semiconductor region, and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region, and a second electrode In the gate turn-off thyristor in which the protrusions adjacent to the semiconductor base are arranged on a plurality of concentric circles sharing the center with the semiconductor substrate, the third semiconductor region is formed on the first main surface at the concentric protrusion on the outermost peripheral portion. A gate turn-off area characterized in that the projected area does not overlap the first semiconductor area. Register. 2. A disk-shaped semiconductor as a base, having a first main surface and a second main surface, wherein the second main surface has a projection,
A first electrode on the first main surface, a second electrode on the second main surface protrusion, a third electrode on the second main surface, a first conductivity type adjacent to the first electrode. A first semiconductor region, a second semiconductor region of the second conductivity type adjacent to the first semiconductor region, a third semiconductor region of the second conductivity type adjacent to the second electrode, and adjacent to the third electrode A fourth semiconductor region of the first conductivity type, a second semiconductor region, a third semiconductor region, and a fifth semiconductor region of the first conductivity type adjacent to the fourth semiconductor region; Is a concentric annular shape sharing the center with the circle of the semiconductor substrate, and the protrusion adjacent to the second electrode is arranged on a plurality of concentric circles sharing the center with the circle of the semiconductor substrate. At the protruding portion on the concentric circle of the peripheral portion, a region where the third semiconductor region is projected on the first main surface is Gate turn-off thyristor, characterized in that one semiconductor regions do not overlap.