JPH10289993A - Solid-state image pickup device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a solid-state image pickup device, wherein photosensitivity and linearity of a picture element MOS transistor are improved by a relatively simple method, and fixed pattern noise is removed by eliminating dispersion. SOLUTION: In the solid-state image pickup device, a picture element image sensing element consisting of an MOS transistor is arranged in a matrix form on a plane, and signal electric charge corresponding to electric charge stored by photoelectric conversion function below a gate electrode of the MOS transistor is read by a signal electric charge read function one by one by a source follower operation. In the process, a drain region 5 of a MOS transistor is provided extending to a part below the gate electrode 1, and a sensor well 3 is narrowed to the side of a source region 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device and a method of manufacturing the same, and more particularly to improvement of sensitivity, linearity, and variation of a pixel solid-state imaging device and a manufacturing method therefor.

[0002]

2. Description of the Related Art MOS transistors and CCDs (Chage Co.)
2. Description of the Related Art A solid-state imaging device using an upled device) has been widely used in an imaging device. This is to utilize a charge accumulated in the MOS inversion layer, transfer the charges in an array, and output a planar image. Recently, improvements have been made to a multi-pixel with a small size, a small imaging area, and a 1 / 4-inch color product of 380,000 pixels has been commercialized.

By the way, as the size of the image pickup apparatus is reduced and the number of pixels is increased, the color needs to be changed from black and white to a color. As the light receiving area per unit pixel becomes smaller, the image pickup apparatus is more resistant to noise. It is required that the sensitivity of the pixel photoelectric conversion element be increased in order to perform imaging properly. In order to improve the sensitivity, for example, there is a method of increasing the power supply voltage. However, increasing the power supply voltage is not preferable because power consumption increases.

FIG. 8 is a schematic diagram showing a cross-sectional structure of a MOS transistor which is a pixel solid-state imaging device of a conventional amplification type imaging device. In FIG. 8, 1 is a gate electrode, 2 is a gate oxide film, 3 is a sensor well, 4 is a source, 5 is a drain,
Reference numeral 6 denotes an OFB (Over Flow Barrier), and reference numeral 7 denotes a semiconductor substrate. The gate electrode 1 is formed in a ring shape, and a charge accumulation region is formed over the entire surface under the ring-shaped gate electrode 1.

By the way, the potential distribution in the pixel MOS transistor having such a configuration is always perfectly point-symmetric with respect to the center of the ring-shaped gate electrode 1 due to the shape of the gate electrode 1 and the influence of adjacent pixels. Cannot be expected, and the distribution becomes non-uniform depending on the location in the circumferential direction, and the concentration point 10 of the electric charge is generated as shown in FIG. With such non-uniformity, in a state where minute electric charges are accumulated, electric charges are likely to accumulate in only a part of the region, and thus the characteristics of the pixel MOS transistor are deteriorated, sensitivity is reduced, and linearity is lost. Further, since the non-uniformity varies depending on the pixel, the characteristic thereof also becomes non-uniform in the imaging region, and this appears as fixed pattern noise such as roughness on the screen.

[0006]

As described above, the solid-state imaging device is required to be smaller, lighter, have lower power, and be compatible with color. For this purpose, it is desired to further improve the sensitivity so that the sensitivity does not decrease even if the area of the light receiving section is reduced. In addition, the problem that non-uniform potential distribution leads to deterioration of linearity and generation of fixed pattern noise must be solved.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and provides a solid-state image pickup device in which the light receiving sensitivity and linearity of a pixel MOS transistor are improved by a relatively simple method, and a fixed pattern noise is eliminated by eliminating variations. It is another object of the present invention to provide a method of relatively simply manufacturing such a solid-state imaging device using a conventional method.

[0008]

In order to achieve the above-mentioned object, the present invention provides a plurality of pixel image pickup devices having a photoelectric conversion function and a signal charge readout function arranged in a matrix on a plane, and this photoelectric conversion function is used for this purpose. In a solid-state imaging device for sequentially reading out a signal corresponding to the charge accumulated in the pixel image pickup device by a signal charge readout function, the pixel image pickup device includes a MOS transistor, and the MOS transistor includes a semiconductor substrate of a first conductivity type; A source region and a drain region of the second conductivity type formed apart from each other in a surface region of the semiconductor substrate, and a gate electrode provided on the substrate surface between the source region and the drain region via an insulating film. The drain region is provided so as to extend to a part below the gate electrode.

In the above-described method for manufacturing a solid-state imaging device having an annular gate electrode, the formation of the source region and the drain region is provided on the annular gate electrode when the annular gate electrode is processed. A first step of vertically ion-implanting the semiconductor substrate with the resist film left, and the semiconductor while maintaining a predetermined tilt angle with respect to a normal line of the semiconductor substrate with the resist film left A second step of performing ion implantation by rotating the substrate relative to the ion implantation direction.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a solid-state imaging device according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows a basic circuit diagram of a solid-state imaging device to which the present invention is applied. FIG.
, 21 is a vertical shift register, 22 is a horizontal shift register, 23 is a vertical signal line, 24 is a video signal output line,
Reference numeral 25 denotes a MOS transistor which is a pixel solid-state imaging device;
Reference numeral 6 denotes a light receiving unit.

The operation of the solid-state imaging device will be described with reference to FIG. When signal light is input to the solid-state imaging device, the photoelectric conversion function of the MOS transistor 25, which is a pixel solid-state imaging device of the solid-state imaging device, operates, and a charge corresponding to the light intensity is generated below the gate electrode. Stored. In FIG. 1, a photodiode symbol is shown, which corresponds to a sensor well portion having a photoelectric conversion function below the gate of the MOS transistor 25.

As described above, after the electric charges generated by the photoelectric conversion are accumulated under the gate, a Y clock and an H clock are applied to the vertical shift register 21 and the horizontal shift register 22, respectively. The switch matrix of the MOS transistor 25 is sequentially operated by the pulse, and M is applied to the electric charge accumulated by the photoelectric conversion.
The modulation amount of the source potential when the source follower operation is performed by the OS transistor 25 is sequentially read out to the video signal output line 24 as a signal. Thus, a video signal corresponding to the charge generated by the photoelectric conversion can be output from the solid-state imaging device.

In FIG. 1, the output from the source is extracted in the form of a source follower. However, the operation may be of a capacitive load type having a capacitor instead of a resistor. FIG. 2 is a cross-sectional view illustrating a configuration of a MOS transistor that is a pixel solid-state imaging device of the solid-state imaging device according to one embodiment of the present invention. FIG. 3 is a plan view showing an arrangement of MOS transistors as pixel solid-state imaging devices on the solid-state imaging device.

2 and 3, 1 is a gate electrode, 2 is a gate oxide film, 3 is a sensor well, 4 is a source region, 5 is a drain region, and 6 is an OFB (Over Flow Ba).
rrier) and 7 are semiconductor substrates.

As apparent from FIGS. 2 and 3, a MOS transistor serving as a pixel solid-state image sensor of a light-receiving portion of a solid-state image sensor has a gate electrode 1 having a ring shape,
It comprises a source region 4 provided in the surface region of the semiconductor substrate inside the ring of the gate electrode 1 and a drain region 5 provided in the surface region of the semiconductor substrate outside the ring of the gate electrode 1. Are arranged in a grid pattern to form a light receiving section.
The signal charges accumulated in the sensor well below the gate electrode 1 by the photoelectric conversion drive the source follower preamplifier of the MOS transistor, and a signal corresponding to the charges is output from the source region 4 to the vertical signal line. The OFB 6 has a function of sweeping out stored signal charges.

A pixel MO according to the embodiment of the present invention shown in FIG.
The S transistor is different from that of the conventional example shown in FIG. 8 in the shape of the drain region 5, and in the case of the conventional example shown in FIG. While it ends just below,
The drain region 5 in FIG. 2 extends below the gate electrode 1, whereby the sensor well 3 serving as the charge storage region is narrowed accordingly.

Such a pixel MOS transistor performs photoelectric conversion under its gate 2 and reads out, as a signal, a modulation of a source potential at the time of performing a capacitive load operation or a source follower operation by a charge stored in this portion. Based on such an operation principle, even if the magnitude of the charge when photoelectrically converted under the gate 2 is the same, the closer the accumulation position where the charge is accumulated to the source region 4, Further, the closer to the surface channel, the greater the influence on the source potential, that is, the output, and the higher the sensitivity.

Further, the narrower the sensor well 3 serving as the charge storage area, the smaller the area where minute charges locally accumulate. As a result, the linearity of the pixel MOS transistor characteristics with respect to the charge storage amount is improved. I do.
Further, variation between the elements of the pixel MOS transistor is reduced, and roughness on the screen caused by the variation, that is, fixed noise is also reduced.

In this embodiment, since the drain region 5 extends below the gate electrode 1 as shown in FIG. 4, the charge accumulation region is narrowed by the source region 4 side, and the concentration 10 of charges is also reduced.

Therefore, according to the embodiment of the present invention, (1) Since the sensor well, which is the charge storage region below the gate electrode, is formed narrow, the region where the charge is stored is small, and the minute charge is small. Even if it is, it becomes easy to distribute uniformly throughout. (2) Therefore, the linearity of the output signal with respect to the charge storage amount is improved due to the characteristics of the pixel MOS transistor.
Further, variation between pixels is reduced, and fixed pattern noise that appears as roughness on a screen is reduced. (3) On the other hand, since the sensor well is narrow and formed closer to the source region 4 of the pixel MOS transistor, the charge accumulation position is closer to the source region 4, thereby increasing the degree of modulation of the output with respect to the accumulated charge. And the sensitivity can be improved.

FIGS. 5 and 6 show a pixel M according to this embodiment.
A process for forming the source region 4 and the drain region 5 of the OS transistor will be described. As shown in FIG. 5, with the resist mask 8 for processing the ring-shaped gate electrode 1 of the pixel MOS transistor left as it is, the source region 4,
The drain region 5 is formed by vertical ion implantation into a silicon substrate. This step is the same as the conventional one.

Next, as shown in FIG. 6, ion implantation is further added from all directions at a constant incident angle θ with respect to the silicon substrate. As a result, ions are implanted to the lower side of the ring-shaped gate electrode 1 on the drain side, the drain region 5 expands, and the sensor well 3 narrows. On the other hand, in the source region 4 in the ring-shaped gate electrode 1, since the diameter is small, the ions do not reach the silicon substrate as a shadow of the resist mask 8 and are not implanted.

FIG. 7 is a diagram for explaining the allowable range of the incident angle in the inclined ion implantation. The incident angle θ of the implanted ions, the height h of the resist, the inner diameter of the gate electrode ring, that is, the source diameter d, the pixel The mutual relationship of the distance l between them is shown.

In this case, the incident angle θ of the implanted ions (complementary angle of the tilt angle formed by the ion beam with respect to the normal) is 45 °.
The values before and after. Considering a realistic size, the resist height h is about 1.8 μm and the source diameter d is about 0.9 μm. Although the distance between the pixels, that is, the width l of the drain portion can be considerably large in some cases, the practical value is 2.0 μm. Based on these sizes, a condition that the ion implantation is possible in the drain region 5 and the ion implantation is not possible in the source region 4 is obtained. Arctan (h / d)>θ> arctan (h / l) arctan (1.8 / 0.9)>θ> arctan
(1.8 / 2.0), about 65 °>θ> 40 °, and a range of 25 ° to 50 ° in terms of tilt angle is considered to be a practical range.

By adopting such a process, it becomes possible to extend the drain region 5 to below the gate electrode 1 relatively easily using a conventional method. As a result, the charge accumulation region is narrowed, and the distribution of charge accumulation can be made closer to the source region 4 and made uniform. As a result, the linearity and sensitivity of the pixel MOS transistor are improved, and the Variation can be reduced.

[0026]

As described above, according to the present invention, a pixel image pickup device comprising a plurality of MOS transistors having a photoelectric conversion function and a signal charge readout function is arranged in a matrix on a plane, and this MOS transistor is provided by the photoelectric conversion function. In the solid-state imaging device, the signal charge corresponding to the charge accumulated under the gate electrode of the MOS transistor is sequentially read out from the source of the MOS transistor by the signal load readout function by the capacitive load operation or the source follower operation. It is provided extending to a lower part. As a result, the sensor well, which is the charge storage region below the gate electrode, can be formed to be narrow, so that even minute charges can be easily distributed uniformly over the entire charge storage region. As a result, the linearity of the output signal with respect to the charge storage amount of the pixel MOS transistor is improved,
Variation between pixels is also reduced, and fixed pattern noise that appears as roughness on the screen is reduced. further,
Since the sensor well is formed narrow and close to the source region of the pixel MOS transistor, the charge accumulation position is made closer to the source region, the degree of modulation of the output with respect to the accumulated charge is increased, and the sensitivity is improved.

Also, a MOS having an annular gate electrode
As a method of manufacturing such a solid-state imaging device using a transistor as a pixel solid-state imaging device, in the present invention, a source substrate and a drain region are formed on a semiconductor substrate while leaving a resist film when processing an annular gate electrode. A first step of performing ion implantation perpendicular to the semiconductor substrate and a second step of performing ion implantation while maintaining a predetermined tilt angle with respect to a normal line of the semiconductor substrate and rotating the semiconductor substrate relative to the ion implantation direction. Is performed by the step of As a result, the drain region can be relatively easily extended to below the gate electrode by a process using a conventionally established method. As a result, the charge accumulation region is narrowed, and the charge accumulation is reduced. Can be made uniform by approaching the source region, and a solid-state imaging device having a pixel MOS transistor having excellent linearity and sensitivity and small variation between pixels can be manufactured.

[Brief description of the drawings]

FIG. 1 is a basic circuit diagram of a solid-state imaging device to which the present invention is applied.

FIG. 2 is a cross-sectional view illustrating a configuration of a pixel MOS transistor that is a pixel solid-state imaging device of the solid-state imaging device according to one embodiment of the present invention;

FIG. 3 is a plan view showing the arrangement of the pixel MOS transistors according to the embodiment shown in FIG. 2;

FIG. 4 is a schematic diagram showing concentration of electric charge under a gate in the pixel MOS transistor according to the embodiment shown in FIG. 2;

5 is an explanatory diagram of a step of forming a source region and a drain region of the pixel MOS transistor according to the embodiment shown in FIG. 2;

FIG. 6 is an explanatory view of a step of forming a source region and a drain region of the pixel MOS transistor according to the embodiment shown in FIG. 2 (continued).

FIG. 7 is an explanatory view of a tilt angle allowable range of the tilt ion implantation performed in the step of FIG. 6;

FIG. 8 is a cross-sectional view illustrating a configuration of a MOS transistor that is a pixel solid-state imaging device of a conventional amplification type imaging device.

FIG. 9 is a schematic diagram showing concentration of electric charge under a gate in a conventional pixel MOS transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Gate electrode, 2 ... Gate oxide film, 3 ... Sensor well, 4 ... Source region, 5 ... Drain region, 6 ... OFB,
7 semiconductor substrate, 8 resist mask, 10 charge concentration point, 21 vertical shift register, 22 horizontal shift register, 23 vertical signal line, 24 video signal output line, 2
5 MOS transistor, 26 light receiving unit.

Claims (4)

[Claims] 1. A plurality of pixel image pickup devices having a photoelectric conversion function and a signal charge readout function are arranged on a plane in a matrix in a matrix, and a signal corresponding to the charge accumulated in the pixel image pickup device by the photoelectric conversion function is converted into a signal charge. In a solid-state imaging device that sequentially reads data by a reading function, the pixel imaging device includes a MOS transistor, the MOS transistor including a semiconductor substrate of a first conductivity type;
A source region and a drain region of the second conductivity type formed apart from each other in a surface region of the semiconductor substrate; and a gate electrode provided on the substrate surface between the source region and the drain region via an insulating film. Wherein the drain region is provided to extend to a part below the gate electrode. 2. The semiconductor device according to claim 1, wherein the gate electrode has a ring shape, the source region is provided in a surface region of the semiconductor substrate below an inner circle of the ring gate electrode, and the drain region is formed in the ring gate electrode. And a drain region of the MOS transistor adjacent to the surface region of the semiconductor substrate below and outside the semiconductor substrate, wherein the drain region extends to the inside of an outer circumferential circle below the annular gate electrode. The solid-state imaging device according to claim 1. 3. The method of manufacturing a solid-state imaging device according to claim 2, wherein the formation of the source region and the drain region is performed on the annular gate electrode when the annular gate electrode is processed. A first step of vertically ion-implanting the semiconductor substrate while leaving the semiconductor substrate, and maintaining the predetermined tilt angle with respect to a normal line of the semiconductor substrate while leaving the resist film and removing the semiconductor substrate. A second step of performing ion implantation while rotating relative to the ion implantation direction. 4. The apparatus of claim 3, wherein the tilt angle is at least greater than 25 ° and less than 50 °.
5. The method for manufacturing a solid-state imaging device according to item 1.