JP3854720B2 - Imaging apparatus and imaging system using the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus that captures an image and an imaging system using the imaging apparatus.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, some imaging devices having gain cells or APS use BJTs, MOSFETs, JFETs, etc. as pixel amplifiers.
[0003]
These amplify signal charges stored in a photodiode, which is a photoelectric conversion element, and read out them as image information by each method. The means for amplifying the signal charge exists in each pixel and is called a gain cell or APS.
[0004]
Since the APS has an amplifying means (amplifier) and its control means in the pixel, the ratio (area ratio) of the photoelectric conversion unit to the pixel or the ratio of the light incident region (aperture ratio) tends to be small. is there. Accordingly, the dynamic range, sensitivity, S / N ratio, and the like of the imaging apparatus may be reduced.
[0005]
When one amplifier is provided for one pixel as shown in FIG. 22-b, the aperture ratio decreases. As a method for preventing the area ratio and the aperture ratio from being lowered by the amplifying means, a method for sharing one amplifying means by a plurality of pixels is proposed as disclosed in, for example, Japanese Patent Laid-Open No. 63-1000087 or Japanese Patent Laid-Open No. 9-46596. Has been.
[0006]
FIG. 24 is a diagram showing the pixel configuration. In FIG. 24, PD1 to PD4 are photodiodes serving as photoelectric conversion units, MTX1 to MTX4 are transfer MOS transistors for transferring signal charges stored in the photodiodes PD1 to PD4, MRES are reset MOS transistors, MSF, MSEL. Is a MOS transistor constituting an amplifying means (source follower), and MSEL is a selection switch for selecting a pixel.
[0007]
[Problems to be solved by the invention]
However, the above Japanese Patent Laid-Open No. 63-100899 or Japanese Patent Laid-Open No. 9-46596 does not disclose a specific arrangement in the case where one amplification means is shared by a plurality of pixels.
[0008]
Further, there is no specific disclosure even if the shared portion is not the above-described amplification means but performs other processing.
[0009]
Therefore, an object of the present invention is to provide an imaging device capable of obtaining good performance without reducing resolution even when a plurality of pixels share a common circuit such as one amplifying unit.
[0010]
It is another object of the present invention to provide an imaging apparatus having a noise removing unit that is preferably used in the above imaging apparatus.
[0011]
Furthermore, it aims at providing the imaging system which used said imaging device for the sensor part.
[0012]
[Means for Solving the Problems]
The present invention has been made to solve the above-described problems.
[0013]
In an imaging apparatus in which a plurality of unit cells each including a plurality of photoelectric conversion units and a common circuit for processing signals from the plurality of photoelectric conversion units are arranged, at least a central portion of the imaging apparatus includes each of the photoelectric conversion units. An adjusting means is provided for adjusting the pitch between the light receiving portions of the light receiving portions that receive the light in the conversion portion to an equal pitch at least in one direction of the vertical direction or the horizontal direction. Each of the photoelectric conversion units is adjacent to the common circuit without passing through another photoelectric conversion unit The photoelectric conversion units in the unit cell are arranged on both sides with the common circuit in between An imaging apparatus is provided.
[0015]
Furthermore, there is provided an imaging system comprising the above-described imaging device, a lens that forms an image of light on the imaging device, and a signal processing circuit that processes an output signal from the imaging device.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Prior to the description of the embodiments of the present invention, the technical background leading to the present invention will be described.
[0017]
The present inventors have disclosed an imaging apparatus that shares a common circuit such as one amplifying means (amplifier) with a plurality of pixels, as described in JP-A-63-100879 or JP-A-9-46596. The pixel layout was examined.
[0018]
FIG. 22A shows a pixel layout diagram of an example of the imaging apparatus when the number of pixels is 4 with respect to the common circuit.
[0019]
This example is an example in which the amplifying means is shared every two rows and two columns of pixels, and the amplifying means 174 is arranged between four photodiodes 173 (a11, a12, a21, a22). Here, 171 indicates a repeating unit cell for two rows, and 172 indicates a repeating unit cell for two columns.
[0020]
FIG. 23 shows a specific pixel pattern layout.
[0021]
The imaging device is a CMOS sensor.
[0022]
In FIG. 23, reference numeral 181 denotes the above-mentioned repeating unit cell (dotted line area in the figure), which is repeatedly arranged in the row and column directions with a size of 4 pixels. Light incident on the photodiodes 182a, 182b, 182c, and 182d is converted into electrons that are accumulated charges and accumulated in the photodiodes 182a to 182d. The accumulated charges are transferred to the floating diffusion 185 by the transfer gates 183a to 183d, and are carried to the input gate 186 of the MOS type amplifier which is an amplifying means. The current flowing through the MOS amplifier is modulated by the accumulated charge, and the output current is extracted from the pixel array by the vertical signal line 187.
[0023]
The XY addressing of the imaging device (two-dimensional pixel array) is performed by the vertical signal line 187, the scanning lines 188a to 188d, and the row selection line 190. In addition to these wirings, a power supply VDD wiring 191 is wired in the vertical direction, and a floating diffusion 185 and a reset line 192 for resetting the input gate 186 to a predetermined voltage are wired in the horizontal direction.
[0024]
The wirings 188 to 192 are arranged above the wirings in the cell, and accordingly, the basic dimensions are too small. Since the six opaque wirings 188 to 192 are optically insensitive areas, the amplifying means arranged in a distributed manner are placed under these wirings 188 to 192. Therefore, it is conceivable to arrange the photodiodes so as to be unevenly distributed in the square direction of the unit cell 181.
[0025]
However, as is apparent from FIG. 22A, such an arrangement does not have an equal pitch in the arrangement of the photoelectric conversion units. Therefore, the intervals between the regions (light receiving units) that detect light in each pixel are equal. However, the following problems occur.
[0026]
That is, an array having the same color and not equal pitches partially causes the spatial frequency and the resolution to be partially not equal, thereby causing a reduction in resolution and defects such as moire fringes. In addition, the occurrence of moire fringes is a very serious problem, and such an imaging apparatus cannot practically be a product. This also holds true when the number of pixels constituting the unit cell is other than four.
[0027]
As a result of further investigation in view of the above points, the present inventors have found that each of the light receiving portions can be obtained by making the pitch of the photoelectric conversion portions constant in an APS having amplification means dispersed in a plurality of pixels. The imaging device has been found to have the same interval, prevent a decrease in resolution and the occurrence of moire fringes, improve the aperture ratio, etc., and obtain good performance.
[0028]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0029]
FIG. 1 is a diagram illustrating an example in which pixels in 2 rows and 2 columns share an amplifying unit 12.
[0030]
In FIG. 1, the shared amplifying unit 12 is arranged at the center of the four pixels, and four photoelectric conversion units (a11, a12, a21, a22) are arranged so as to surround the amplifying unit 12.
[0031]
In addition, the light shielding portion 15 exists at a position symmetrical to the center of the region in each pixel occupied by the amplification means 12. Therefore, the center of gravity of the photoelectric conversion unit 11 in each pixel exists at the center of each pixel. Accordingly, the four photoelectric conversion units (a11 to a22) can be arranged at equal intervals a in the vertical direction and the horizontal direction.
[0032]
In FIG. 2, the shared amplifying means 22 is arranged at the center in the horizontal direction of the four pixels, and the four photoelectric conversion units 21 (a11, a12, a21, a22) sandwich the amplifying means 22. Has been placed.
[0033]
In addition, a light shielding portion 25 exists at a position symmetrical to the center of the region in each pixel occupied by the amplification means 12. Therefore, the center of gravity of the photoelectric conversion unit 11 in each pixel exists at the center of each pixel. Accordingly, the four photoelectric conversion units (a11 to a22) can be arranged at equal intervals a in the vertical direction and the horizontal direction.
[0034]
The above-described embodiment of FIG. 2 is established in exactly the same manner even when the horizontal direction and the vertical direction are interchanged.
[0035]
In FIG. 3, G pixels that are most effective for resolution are arranged in the upper left and lower right of the repetitive unit cell 30 composed of four pixels. In the G pixel, there is a light shielding portion 35 at a position symmetrical to the center of the region occupied by the amplification means 32 disposed at the center of the cell 30. Therefore, the center of gravity of the photoelectric conversion unit 31 in the G pixel exists at the center of the G pixel. Thereby, the photoelectric conversion parts a11 and a22 of the G pixel can be arranged at equal intervals a in the vertical and horizontal directions.
[0036]
The R pixel is arranged at the upper right of the cell 30 and the B pixel is arranged at the lower left of the cell 30. Although they do not have a light-shielding portion that is specifically considered unlike the G pixel, the number of arrangement in the unit cell 30 is 1, and therefore, the unit cells can be arranged at equal intervals with the interval 2a.
[0037]
FIG. 4 is a variation of the embodiment shown in FIG. 3, and is devised so that the area occupied by the amplifying means and the light shielding portion in the G pixel is reduced.
[0038]
The present inventors have also found a signal readout circuit used for noise removal that is effective in an imaging apparatus that shares one amplification means with a plurality of pixels as described above.
[0039]
In the embodiment described above, the amplification unit is disclosed as a portion shared by a plurality of pixels, but the shared portion is not limited to the amplification unit.
[0040]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0041]
First, FIG. 6 shows a block diagram of an imaging system using the imaging apparatus of the present invention. As shown in the figure, the image light incident through the optical system 71 forms an image on the CMOS sensor 72. The optical information is converted into an electric signal by the pixel array arranged on the CMOS sensor 72. The electric signal is subjected to signal conversion processing by a signal processing circuit 73 by a predetermined method and output. The signal processed signal is recorded or transferred by an information recording device by a recording system and communication system 74. The recorded or transferred signal is reproduced by the reproduction system 77. The CMOS sensor 72 and the signal processing circuit 73 are controlled by a timing control circuit 75, and the optical system 71, the timing control circuit 75, the recording / communication system 74, and the reproduction system 77 are controlled by a system control circuit 76.
[0042]
Example 1
First, Example 1 will be described.
[0043]
FIG. 5 shows a circuit configuration diagram for one pixel of the CMOS sensor.
[0044]
In FIG. 5, a11 to a22 are photodiodes serving as photoelectric conversion units, MTX1 to MTX are transfer MOS transistors for transferring signal charges accumulated in the photodiodes a11 to a22 to a floating diffusion (hereinafter referred to as FD), MRES Reset MOS transistors for resetting FD, MSF and MSEL are MOS transistors constituting a source follower circuit, and MSEL is a selection switch for selecting a pixel.
[0045]
FIG. 7 shows a specific pattern layout of the pixel array portion of the CMOS sensor of this embodiment.
[0046]
The CMOS sensor shown in FIG. 8 is formed on an end crystal silicon substrate with a layout rule of 0.4 μm, the pixel size is 8 μm square, and the source follower amplifier as an amplifying means is 4 pixels in 2 rows and 2 columns. Shared. Therefore, the size of the repeating unit cell 81 shown by the dotted line region in the drawing is 16 μm × 16 μm square, and a two-dimensional array is formed.
[0047]
Photodiodes 82a, 82b, 82c, and 82d, which are photoelectric conversion units, are formed obliquely at the center of each pixel, and their shapes are substantially rotationally symmetric and mirror image symmetric vertically and horizontally. The center of gravity g of the photodiode is designed to be the same for each pixel. Reference numeral 95 denotes a light shielding portion.
[0048]
Reference numeral 88-a denotes a scanning line for controlling the upper left transfer gate 83-a, 90 denotes a row selection line, and 92 denotes a reset line for controlling the MOS gate 93.
[0049]
The signal charges accumulated in the photodiodes 82a to 82d are guided to the FD 85 through the transfer gates 83a to 83d. The MOS sizes of the gates 83a to 83d are L = 0.4 μm and W = 1.0 μm (L indicates a channel length and W indicates a channel width).
[0050]
The FD 85 is connected to the input gate 86 of the source follower by an Al wiring having a width of 0.4 μm, and the signal charge transferred to the FD 85 modulates the voltage of the input gate 85. The MOS size of the input gate 86 is L = 0.8 μm and W = 1.0 μm, and the sum of the capacitances of the FD 85 and the input gate 86 is about 5 fF. Since Q = CV, 10 ^Five The voltage of the input gate 86 changes by 3.2 V due to the accumulation of electrons.
[0051]
V _DD The current flowing from the terminal 91 is modulated by the input gate 86 and flows out to the vertical signal line 87. The current flowing out to the vertical signal line 87 is signal-processed by a signal processing circuit (not shown) and finally becomes image information.
[0052]
Thereafter, the potentials of the photodiodes 82a to 82d, the FD 85, and the input gate 86 are set to a predetermined value V. _DD Therefore, by opening the MOS gate 83 connected to the reset line 82 (the transfer gates 83a to 83d are also opened at this time), the photodiodes 82a to 82d, the FD 85, and the input gate 86 are set to V _DD Shorted to the terminal.
[0053]
Thereafter, charge transfer of the photodiodes 82a to 82d starts again by closing the transfer gates 83a to 83d.
[0054]
It should be noted here that all of the wirings 88a to 88d, 90, and 92 penetrating in the horizontal direction are made of transparent conductive ITO (Indium Tin Oxide) having a thickness of 1500 mm. Since light is transmitted through the photodiodes 82a to 82d, the center of gravity g of the photodiode is coincident with the center of gravity of the light sensing region (light receiving portion).
[0055]
According to this embodiment, it is possible to provide a CMOS sensor having a relatively high area ratio and a high aperture ratio with the same pixel pitch.
[0056]
(Example 2)
A second embodiment will be described.
[0057]
FIG. 8 shows a specific pattern layout of the image pickup apparatus according to the second embodiment of the present invention.
[0058]
In FIG. 9, 102a to d are photodiodes, 103a to d are transfer gates, 105 is an FD, 106 is a source follower input gate, 107 is a vertical signal line, 108a to d are scanning lines, 110 is a row selection line, A reset line 112 controls the MOS gate 113.
[0059]
In the present embodiment, the wirings 108a to 108d, 110, and 112 that run in the horizontal direction run so as to cross the center of each pixel, so that the light incident on the photodiodes 102a to 102d is blocked. Even the metal wiring does not move the center of gravity g of the light sensing region, and therefore coincides with the center of the pixel.
[0060]
According to the present embodiment, since a normal (opaque) metal having a small electric resistance can be used, the time constant of the lateral wiring is improved, and a higher-speed imaging device can be provided.
[0061]
In the above embodiment, since the portion under the light shielding film is effectively used, a photodiode as a photoelectric conversion portion is formed up to the portion under the light shielding film as shown in FIG. 9 to function as a charge storage portion. It is also possible.
[0062]
Example 3
A third embodiment will be described.
[0063]
In the second embodiment described above, since the center of the pixel having the best light collection efficiency is crossed, there is a concern that the sensitivity of the image pickup apparatus is lowered. FIG. 10 shows a further improved embodiment.
[0064]
In this embodiment, the transfer gates 123a to 123d, the FD 125, the source follower input gate 126, and the reset MOS gate 133 all run in the horizontal direction (scanning lines 128a to 128d, row selection line 130, reset line 132). ), The photodiodes 122a to 122d and their openings can be maximized. Moreover, the opening continuously exists in the center of each pixel. The light shielding portion is formed in the horizontal and vertical wiring portions.
[0065]
Further, in this embodiment, the source follower as the amplification means and the reset MOS transistor are arranged in the horizontal direction around each pixel, so that it can be compactly arranged under the horizontal wiring. Yes.
[0066]
In addition, since an unused space still exists under the wiring of the upper right pixel, it is possible to add a new configuration such as a smart sensor.
[0067]
According to the present embodiment, since the photodiode area and the aperture ratio can be increased, an imaging device with a wide dynamic range and high sensitivity can be provided. Further, as the miniaturization progresses in the future, even if the size of the opening of the photodiode becomes about the wavelength of light, there is no possibility that light will not enter, and the performance can be exhibited for a long time.
[0068]
In the above embodiment, the amplifying means is arranged at the center of the unit cell, and the center of gravity of the region for sensing light and the center of the pixel coincide with each other. However, the present invention is not limited to these and is shown in FIG. Such an opening may have a translational symmetry.
[0069]
In other words, because the openings are translationally symmetric, the areas where light is sensed are at equal pitches.
[0070]
Example 4
A fourth embodiment will be described.
[0071]
FIG. 12 shows a specific pattern layout diagram of the image pickup apparatus according to the fourth embodiment.
[0072]
In this embodiment, the position of the color to be used is determined. The upper left and lower right are G pixels that most affect the luminance, the upper right is an R pixel, and the lower left is a B pixel.
[0073]
In this embodiment, the amplifying means and others are arranged so that the photodiodes 142a and 142d of the G pixel have the maximum area and aperture ratio.
[0074]
Further, since the center of gravity g of the light sensing region in the G pixel coincides with the center of each pixel, the equal pitch property of the G pixel is ensured.
[0075]
According to this embodiment, it is possible to provide a highly sensitive imaging device.
[0076]
Further, the human eye can realize a characteristic similar to a state in which the luminance resolution is higher than the color resolution, the color disappears in a dark place, and only the light and darkness of the subject can be seen.
[0077]
(Example 5)
A fifth embodiment will be described.
[0078]
A diagram showing a fourth embodiment of the present invention is shown in FIG.
[0079]
In FIG. 13, an on-chip lens 202 is formed in each pixel of the unit cell 201. Light from the outside world is collected by this on-chip lens and enters the opening 203. Here, reference numeral 204 denotes a light receiving portion condensed by an on-chip lens.
[0080]
Here, by adjusting the on-chip lens, the position of the light receiving unit can have a degree of freedom.
[0081]
For this reason, in the case where the amplification means is shared by a plurality of pixels, even if the photodiodes that are the photoelectric conversion units cannot be formed at an equal pitch, by adjusting the on-chip lens, the distance between the light receiving units is equal. The pitch can be set.
[0082]
When the imaging lens used in the imaging device is not telecentric, the incident angle (optical axis) of light incident on the sensor chip differs between the center and the outer periphery of the chip. For this reason, in Example 1 or Example 2, it is also possible to make the area | region which senses light over the whole sensor chip into an equal pitch by making an opening part an unequal pitch only in an outer peripheral part.
[0083]
As described above, in the first to fourth embodiments, the light sensing region (light receiving unit) is made to have an equal pitch by adjusting the light shielding unit which is an optical member. In the fifth embodiment, by adjusting a lens that is an optical member, light sensing regions (light receiving portions) are set at an equal pitch.
[0084]
(Example 6)
A sixth embodiment will be described.
[0085]
In this embodiment, an imaging apparatus according to the present invention including a signal processing circuit unit will be described. FIG. 14 shows an equivalent circuit diagram of an imaging apparatus including the signal processing circuit unit of the present embodiment.
[0086]
FIG. 15 shows a timing chart.
[0087]
Vertical scanning is started by a clock φV (n) representing a vertical blanking period. First, reset line φTX in the first row _RO Is activated during the horizontal blanking period (φHBL high), and then the second and third rows are performed in the same manner. As a result, each row of pixels has a reset potential V _DD Reset to. (Fig. 6)
[0088]
During each horizontal period, as shown in FIG. ₁ Then, the reset Tr 160 connected to the vertical signal line 157 is turned on by φRv high, and the vertical signal line 157 is reset. At the same time, each of the gates Tr162 is turned on by φTN, φTS1, and φTS2 high, and the wiring up to the signal reading Tr164 and the storage capacitor 163 are brought into conduction with the vertical signal line, and are similarly reset. As a result, charges accumulated in the storage capacitor 163 and the like are removed. Then period T ₂ The reset line φTX _RO The high causes the floating gate that is the input gate of the source follower amplifier in the pixel to be V _DD Reset to. Then period T _Three Thus, when φL is high, the grounding Tr 161 connected to the signal line 157 is turned on, and the signal line 157 is grounded. At the same time, in order to connect the storage capacitor CTN163 for storing the noise component to the signal line 57, it is set to φTN high and the gate Tr162 is turned on. At that time, the row selection line φSO is high, and the potential of the floating gate (˜V _DD ) According to the current V _DD By flowing from the terminal toward the CTN, the storage capacitor CTN holds the charge of the noise component.
[0089]
Next period T _Four Odd-column scanning line φTX _OOO The odd-numbered column transfer gate in the pixel is turned on by high, and the accumulated charge corresponding to the image light in the photodiode a11 is transferred to the floating gate. At that time, the capacitance hanging from the signal line 157 is not CTN for noise but CTS1, and similarly, the charge of the signal 1 component in the odd-numbered column corresponding to the a11 is held in the storage capacitor CTS1.
[0090]
Next period T _Five Then, only the signal line 157 is reset by φRV high. The other circuits are not affected by the reset because φSO and φTN to φTS2 are low, and the state is maintained.
[0091]
Next, period T _Five And period T ₆ The signal φTX applied to the reset line 62 between _Ro Becomes high level and the input gate in the pixel is V _DD Reset to.
[0092]
Period T ₆ Now, scan line φTX _oeo High by photodiode a ₁₂ The stored charge is transferred, and the signal charge is similarly held in the storage capacitor CTS2.
[0093]
In this way, the noise component for one row, the photodiode a ₁₁ Signal component, photodiode a ₁₂ The charge of the signal component is accumulated for each column in CTN, CTS1, and CTS2.
[0094]
Period T ₇ In this case, in order to sequentially transfer the charges accumulated in CTN to CTS2 of each column to the amplification amplifier 166, the horizontal scanning pulse φHc is sequentially set to high for each column to arrange the gates arranged for each column. The Tr 164 is turned on, and the storage capacitors CTN to CTS2 are connected to the amplification amplifier for each column. The noise component that has passed through the amplification amplifier and the photodiode a ₁₁ Signal, photodiode a ₁₂ The signal component of is output from the photodiode a by the differential amplifier 167. ₁₁ A component S1 in which a noise component is emitted from the signal component of the photodiode a, and the photodiode a ₁₂ Finally, the component S2 obtained by subtracting the noise component from the signal component is output.
[0095]
The period 7 is also a period during which photocharge accumulation of the photodiode is performed.
[0096]
Furthermore, the photodiode a _{twenty one} , A _{twenty two} Even in the case of obtaining a component obtained by subtracting the noise component from the signal component from _ooo , ΦTX _oeo ΦTX instead of _ooe , ΦTX _oee The operation can be performed in the same manner as described above except that is set to high.
[0097]
(Example 7)
Example 7 will be described.
[0098]
FIG. 16 shows an equivalent circuit diagram of the imaging apparatus including the signal processing circuit unit of this embodiment.
[0099]
In the present embodiment, four signal storage capacitors CTS1 to CTS4 63 are provided, and different signal information can be stored for each capacitor 63. More specifically, the signal charge of the pixel a11 can be stored in CTS1 and the signal charge of the pixel 22 can be stored in CTS4. Accordingly, the signal processing after the amplification amplifier 66 can be performed at half speed, and the signal processing of the amplification amplifier 66, the differential amplifier 67, and the signal processing system of the rear panel (not shown) is half that of the sixth embodiment. Get better at speed. Accordingly, the speed of the elements used in the circuit can be reduced, and lower-cost and low-performance elements and circuits can be used, so that the cost of the entire system can be expected.
[0100]
In addition, it is not necessary for the electric charge stored in the storage capacitor to be a direct output from each photodiode. By devising the clock of the transfer gate and the reset gate associated with each pixel, The signal charge of the photodiode can be added. For example, it is possible to extract signals such as G light information of the pixel a11 in the CTS1, G light information of the pixel a22 in the CTS2, and R + B light information of the pixel a12 + a21 in the CT3. In this embodiment, a smart sensor that uses each pixel more intelligently can be sufficiently exerted.
[0101]
In the sixth embodiment and the seventh embodiment described above, it is possible to remove noise due to variations in characteristics of the amplifying means for each unit cell.
[0102]
(Example 8)
Example 8 will be described.
[0103]
The timing when the present embodiment is driven in a non-interlace manner will be described with reference to FIG.
[0104]
In the horizontal blanking period (HBLK), transfer of signals photoelectrically converted by the pixels and reset operation to the initial state of photoelectric conversion are performed.
[0105]
Period T ₁ Then, the vertical signal line is reset by the pulse φV to remove the residual charges on the signal line, and the residual charges on the temporary storage memories CTN1, CTN2, CTS1, and CTS2 are removed by the pulses φTN1, φTN2, φTS1, and φTS2. Do.
[0106]
Period T ₂ Then, the first pixel row (a ₁₁ , A ₁₂ , ... a _1n ) First, as a step before transferring the odd-numbered photoelectric conversion signal, the gate portion of the common amplifier is set to the pulse φTX. _RO Reset to remove residual charge. Reset noise remains in the gate after removal.
[0107]
Period T _Three Then T ₂ This is a period in which the reset noise and the offset voltage of the common amplifier are transferred to the memory CTU1. The output portion of the common amplifier is connected to the vertical signal line by the pulse φSO, and the load MOS Tr is turned on by the pulse φL in order to put the common amplifier in the operating state, and the vertical signal line and the memory are connected by the pulse φTN1. It is accumulated as noise (N) in the memory.
[0108]
Period T _Four Then, odd number (a ₁₁ , A ₁₃ , ... a _1n ) Photoelectric conversion signal is transferred to the memory CTS1. Pulses φL, φTS1, and φSO bring the common amplifier to the memory into conduction.
[0109]
Pulse φTX _oo Thus, the photoelectric conversion signal is transferred from the light receiving portion to the gate portion of the common amplifier. At this point the gate has a T ₂ The photoelectric conversion signal is added to the reset noise in the period. This gate voltage is superimposed on the offset voltage of the common amplifier and is stored as a signal (S + N) on the memory.
[0110]
Period T _Five ~ T ₈ Then, this period is an even number (a ₁₂ , A _14, , ... a _1n-1 ) Photoelectric conversion signal of memory T _S2 Drive to transfer to. The basic operation is the aforementioned T ₁ ~ T _Four It is the same as the period. The difference is φTX _oo → φTX _oe , ΦT _N1 → φT _N2 , ΦT _S1 → φT _S2 Pulse control.
[0111]
Period T ₉ Then, by removing residual charges between the vertical signal line, the common amplifier, and the transfer MOS, the basic operation of transferring reset noise and photoelectric conversion signals is completed.
[0112]
Noise N1, N2, and signals S1 + N1, S2 + N2 are accumulated on each memory by the above driving. These noises and signals are T _Ten During the period, the horizontal output line is transferred with pulses φH1 and φH2 from the horizontal shift register. The output amplifier A1 subtracts (S1 + N1) -N1 and outputs a signal S1, and the output amplifier A2 performs subtraction of (S2 + N2) -N2 and outputs a signal S2.
[0113]
The pixel row (a ₁₁ ... a _1n Only the photoelectric conversion signal of) is obtained. The accumulation of pixel rows is T _Four , T ₈ Photoelectric conversion is started when the photoelectric conversion signal is transferred to the gate portion during the period.
[0114]
In the next horizontal blanking period, the operation of the second pixel row is performed in the same manner as the first row. When the operation of the second pixel row is completed, the common amplifier in units of four pixels becomes non-conductive until one vertical period after the next operation is performed.
[0115]
In FIG. 18, when two rows are driven simultaneously, the memory (CT _N1 , CT _S1 , CT _S2 ) And another output differential amplifier (A1, A2) can be easily added. In other words, the non-interlaced driving is performed for one row to the pixel row every 1H, but this may be performed for two pixel rows within the 1H period.
[0116]
FIG. 6 shows a schematic diagram of the vertical timing.
[0117]
In one vertical period, the operation in the horizontal period is sequentially performed for the pixels in the vertical direction. The vertical shift register has a drive pulse φTX every 1H. _oo , ΦTX _oe , ΦTX _RO , ΦSo pulse is output for each row.
[0118]
As described above, in the eighth embodiment, not only noise due to variations in characteristics of the amplifying means as in the sixth and seventh embodiments described above, but also reset noise can be removed.
[0119]
Example 9
Example 9 will be described.
[0120]
The present invention is not only used for a general CMOS sensor as shown in FIG. 24, but also in addition to an image sensor disclosed in ISSCC98 / SESS: ON11 / IMAGESEMSORS / PAPER FA11.8pp182 shown in FIG. Can also be applied.
[0121]
As a configuration of the amplifier shared by the four pixels at that time, for example, a circuit as shown in FIG. 20 can be considered.
[0122]
(Example 10)
Example 10 will be described.
[0123]
In this embodiment, a common circuit in which an additional function is provided in a common amplifier of pixels will be described.
[0124]
FIG. 21 shows a common circuit embodiment.
[0125]
There are a memory circuit, a differential amplifier, and a comparator after the common amplifier. If the noise described in the above embodiment is temporarily stored in the memory, the signal (SN) is transferred to the (+) side of the amplifier, and the difference between the two is obtained, only the signal (S) is obtained. This signal is output to the vertical signal line. Or depending on the purpose, it can be binarized by a comparator at a later stage.
[0126]
If the comparator is an AD converter, an AD output can be obtained. The AD output may be either serial output or parallel output, and the circuit configuration may be changed depending on the purpose.
[0127]
【The invention's effect】
As described above, according to the present invention, there is provided a high-yield imaging device that has a high aperture ratio, high sensitivity, and built-in multi-functions without causing performance degradation such as resolution reduction and generation of moire fringes. Can be realized.
[Brief description of the drawings]
FIG. 1 is a diagram showing a layout of a pixel portion according to the present invention.
FIG. 2 is a diagram showing a pixel portion layout of the present invention.
FIG. 3 is a diagram showing a layout of a pixel portion according to the present invention.
FIG. 4 is a diagram showing a pixel portion layout of the present invention.
FIG. 5 is a circuit configuration diagram of a unit cell of a CMOS sensor.
FIG. 6 is a block diagram of an imaging system using the imaging apparatus of the present invention.
FIG. 7 is a pattern layout diagram of an embodiment of the present invention.
FIG. 8 is a pattern layout diagram of an embodiment of the present invention.
FIG. 9 is a diagram illustrating an embodiment of the present invention.
FIG. 10 is a pattern layout diagram of one embodiment of the present invention.
FIG. 11 is a diagram illustrating an embodiment of the present invention.
FIG. 12 is a pattern layout diagram of one embodiment of the present invention.
FIG. 13 is a diagram illustrating an embodiment of the present invention.
FIG. 14 is a signal processing circuit diagram according to an embodiment of the present invention.
FIG. 15 is a timing chart of an embodiment of the present invention.
FIG. 16 is a signal processing circuit diagram according to an embodiment of the present invention.
FIG. 17 is a signal processing circuit diagram of one embodiment of the present invention.
FIG. 18 is a timing chart of an embodiment of the present invention.
FIG. 19 is a timing chart of an embodiment of the present invention.
FIG. 20 is a diagram illustrating an embodiment of the present invention.
FIG. 21 is a diagram illustrating an embodiment of the present invention.
FIG. 22 is a layout diagram of a pixel portion of the imaging apparatus.
FIG. 23 is a pattern layout diagram of the imaging apparatus of FIG. 22;
FIG. 24 is a circuit configuration diagram of a unit cell of a CMOS sensor.
FIG. 25 is a circuit configuration diagram of a pixel portion of a conventional CMOS sensor.
[Explanation of symbols]
11 Photoelectric converter
12 Common pixel amplifier
15 Shading part
21 Photoelectric converter
22 Common pixel amplifier
25 Shading part
31 Photoelectric converter
32 Common pixel amplifier
35 Shading part
202 On-chip lens

Claims (24)

In an imaging apparatus in which a plurality of unit cells are arranged by arranging a plurality of photoelectric conversion units and a common circuit for processing signals from the plurality of photoelectric conversion units,
Adjusting means for adjusting the pitch between the light receiving portions of the light receiving portions that receive light in each of the photoelectric conversion portions at least in the central portion of the image pickup device to at least equal pitch in one direction of the vertical direction or the horizontal direction. Is provided,
The photoelectric conversion units in the unit cell are arranged on both sides of the common circuit so that each of the plurality of photoelectric conversion units in the unit cell is adjacent to the common circuit without passing through another photoelectric conversion unit. An imaging device characterized by being arranged .   2. The optical member according to claim 1, wherein the adjusting unit cancels an unequal pitch in at least one direction of a horizontal direction or a vertical direction of a light receiving unit at least in a central portion of the imaging apparatus, which is generated by the common circuit. An imaging apparatus characterized by that.   The imaging apparatus according to claim 2, wherein the optical member is a light shielding film.   4. The imaging apparatus according to claim 3, wherein the common circuit is disposed in a central portion of the unit cell.   5. The imaging apparatus according to claim 4, wherein the light shielding film is disposed between adjacent unit cells.   6. The imaging apparatus according to claim 5, wherein the light shielding film is disposed at a position that is at least line-symmetric with respect to a horizontal or vertical center line of the unit cell.   The imaging apparatus according to claim 2, wherein the optical member is an on-chip lens.   8. The imaging apparatus according to claim 1, wherein the center of gravity of the light receiving unit and the center of gravity of each photoelectric conversion unit in each photoelectric conversion unit are the same.   9. The imaging apparatus according to claim 1, wherein the common circuit is an amplifier.   The imaging apparatus according to claim 9, wherein the amplifier includes an amplifying unit that amplifies signals from a plurality of photoelectric conversion units in the unit cell and a reset unit that resets the unit cell.   The control line for applying a drive pulse from the shift register to the common circuit so that the center of gravity of the light receiving unit and the center of photoelectric conversion unit in each photoelectric conversion unit in the unit cell coincide with each other. An imaging device characterized by being provided.   11. The unit cell according to claim 9, further comprising a control line for passing a drive pulse from a shift register to a common circuit, the control line being a transparent conductor that transmits light. There is an imaging apparatus.   11. The control unit according to claim 9, wherein the unit cell has a control line that penetrates in a horizontal direction and applies a driving pulse from a shift register to a common circuit, and the control line extends through a central portion of the photoelectric conversion unit. An imaging apparatus characterized by traversing.   11. The unit cell according to claim 9, further comprising a control line for applying a driving pulse from a shift register to a common circuit, which penetrates in the unit cell in a horizontal direction, and the common circuit constituting the unit cell includes the control An image pickup apparatus arranged below a line.   In Claim 9 or Claim 10, it has a control line for applying a drive pulse from a shift register to a common circuit, which penetrates in the unit cell in the horizontal direction, and the control line is divided into two groups, An imaging apparatus characterized by penetrating the peripheral portion of each pixel in the same number.   16. The imaging apparatus according to claim 15, wherein the unit cell includes at least an amplifying unit and a reset unit, and the amplifying unit and the reset unit are disposed below the control lines of different groups.   2. The imaging according to claim 1, wherein the adjusting means adjusts the pitch between the light receiving portions for each same color in at least the central portion of the imaging apparatus to be equal to at least one pitch in the vertical direction or the horizontal direction. apparatus.   The light receiving unit of the photoelectric conversion unit to which the color filter mainly determining luminance is attached is larger than the light receiving unit of the photoelectric conversion unit to which other color filters are attached. Imaging device.   The imaging apparatus according to claim 18, wherein the color that mainly determines luminance is green (G).   18. The imaging apparatus according to claim 17, wherein the adjusting unit is a light shielding film, and the light shielding film is centrally symmetric with respect to a center of the unit cell.   21. The imaging apparatus according to claim 17, wherein the common circuit is an amplifier.   24. The imaging apparatus according to claim 21, wherein the amplifier includes an amplifying unit that amplifies signals from a plurality of photoelectric conversion units and a reset unit that resets an input unit of the amplifying unit.   21. The common circuit according to claim 1, wherein the common circuit includes digital signal conversion means for converting signals from a plurality of photoelectric conversion units into digital signals. An imaging device.   The image pickup apparatus according to any one of claims 1 to 15, a lens that forms an image of light on the image pickup apparatus, and a signal processing circuit that processes an output signal from the image pickup apparatus. A characteristic imaging system.

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