JPH10284954A - Bias voltage control circuit for avalanche photodiode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily decide the max. value and the min. value of the bias voltage of APD(avalanche photodiode) by connecting NPN transistors to the both ends of the output resistance of a voltage control current source to which an APD cathod is connected by bias control circuit of the APD, thereby appling a prescribed voltage to the APD cathod. SOLUTION: The voltage control current source 51 controls current flowing in an output resistance 54 and the voltage obtained by subtracting voltage lowering in the output resistance 54 from a high-order power voltage 55 is impressed on the APD cathod. The upper limit of the voltage to be applied to the APD cathod is decided by the voltage obtained by subtracting a voltage lowering portion of APD bias current by the resistance 54. The NPN transistors 58 are connected to the both ends of the resistance 54 and its base is connected to a clip terminal 57 for outputting a prescribed voltage. At the time of the saturation of a transistor 52, the lower limit of the voltage to be applied to the APD cathod is decided by an emitter resistance 53 and the clip voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bias voltage control circuit for an avalanche photodiode in an optical receiver using an avalanche photodiode as a light receiving element.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional optical receiving apparatus shown in, for example, a conventional example of Japanese Patent Application Laid-Open No. 2-212710. In FIG. 5, reference numeral 1 denotes an avalanche photodiode (hereinafter referred to as APD);
Is a preamplifier, 3 is an AGC amplifier, 4 is a peak detection circuit,
5 is an APD control circuit, 51 is a voltage control current source, 52 is an NPN transistor, 53 and 54 are resistors, and 55 is a high voltage generation circuit.

Next, the operation of the conventional optical receiver shown in FIG. 5 will be described. In FIG. 5, an APD 1 receives an optical signal from an optical fiber and outputs a current signal proportional to the received optical power to a preamplifier 2. The preamplifier 2 converts the current signal into a voltage signal and outputs the voltage signal to the AGC amplifier 3. The AGC amplifier 3 amplifies the voltage signal with a gain corresponding to the gain control voltage output from the peak detection circuit 4 and outputs a data signal having a predetermined constant amplitude. The peak detection circuit 4 is AGC
The amplitude value of the output signal of the amplifier 3 is detected, and a gain control voltage such that the output signal of the AGC amplifier 3 has a constant amplitude is output to the AGC amplifier 3 and the APD control circuit 5. APD control circuit 5 is A
Outputs the supply voltage to PD1 and controls the multiplication factor of APD1.

In the following description, an optical receiving apparatus will be described in which after the optical signal power input to the APD 1 is reduced and the AGC amplifier 3 reaches the maximum gain, the gain of the APD 1 is controlled to increase. . In this case, the optical signal power input to the APD 1 decreases, and when the gain of the AGC amplifier 3 becomes equal to or less than the optical signal power at which the gain becomes maximum, the bias voltage of the APD 1 increases. As a result, the multiplication factor of APD1 increases and AG
The output signal amplitude of the C amplifier 3 can be controlled to be constant.

Next, the operation of the APD control circuit 5 shown in FIG. 5 will be described. The APD control circuit 5 includes a resistor 54 having one end connected to the high voltage generation circuit 55 and a voltage control current source 51 connected to the other end of the resistor 54. The voltage control current source 51 includes an NPN transistor 52 and a resistor 53, and the current value of the voltage control current source 51 is controlled by a voltage applied to the base of the NPN transistor 52. The resistance 5
A bias voltage of the APD 1 is supplied from a connection point between the APD 4 and the voltage control current source 51. Therefore, the bias voltage of APD1 is
It is controlled by a control voltage applied to the base of the NPN transistor 52.

On the other hand, the multiplication factor M of the APD 1 is the bias voltage V
It is known that the following relationship is established, determined by R and the breakdown voltage VB. M = 1 / (1− (VR / VB) N) (1) where N is a coefficient determined by APD1. However, in the APD 1, when the bias voltage becomes equal to or higher than the breakdown voltage, a breakdown occurs between the junctions and the device is destroyed, so that the maximum value of the bias voltage is limited. Further, when the bias voltage falls below a certain limit, the inter-terminal capacitance sharply increases and high-frequency characteristics deteriorate, so that the minimum value of the bias voltage is also limited. Therefore, APD selected according to the application
It is necessary to design the APD control circuit 5 so that the bias voltage is output within the range of the maximum value and the minimum value determined according to the characteristic of 1.

In this case, the maximum value of the bias voltage is given when the NPN transistor 52 is cut off, and is a value obtained by subtracting the voltage drop of the resistor 54 due to the current flowing through the APD 1 from the voltage of the high voltage generating circuit 55. The voltage of the high voltage generator 55 is VH, the current flowing through APD1 is IAPD1,
Assuming that the resistance value of the resistor 54 is R1, the maximum value VAPD-MAX of the bias voltage of the APD1 is given by the following equation. VAPD-MAX = VH−IAPD1 × R1 (2) Therefore, the voltage VH of the high voltage generation circuit 55 is given,
When the current IAPD1 flowing through APD1 is given, the maximum value VAPD-MAX of the bias voltage is determined by the resistance R1 of the resistor 54.

The bias voltage given by equation (2)
When the optical signal power increases from the optical signal power at which the maximum value is reached, the output signal amplitude of the AGC amplifier 3 is controlled to be constant by lowering the bias voltage and decreasing the multiplication factor. In this case, the minimum value of the bias voltage of the APD 1 is given when the transistor 52 is saturated, and the voltage of the resistor 54 is the sum of the current IAPD2 flowing through the APD1 from the voltage of the high voltage generating circuit 55 and the current flowing through the NPN transistor 52. This is the value obtained by subtracting the drop. Assuming that the current flowing through the NPN transistor 52 is ITR, the minimum value VA of the bias voltage of the APD 1
PD-MIN is given by the following equation. VAPD-MIN = VH-(IAPD2 + ITR) x R1 (3)

Generally, considering the current driving capability to APD1, IA
Since the circuit is designed so that PD2 ≪ ITR, the saturation voltage of the NPN transistor 52 is set to VSAT, and the resistance value of the resistor 53 is set to
Assuming R2, equation (2) can be transformed into the following equation. VAPD-MIN = (VH−VSAT) × R2 / (R1 + R2) + VSAT (4) Therefore, the voltage VH of the high voltage generation circuit 55 is given, and NPN
When the saturation voltage VSAT of the transistor 52 is given,
The minimum value of the bias voltage VAPD-MIN is the resistance value R1 of the resistor 54.
And the resistance value R2 of the resistor 53. However, since the resistance value R1 of the resistor 54 is fixed to determine the maximum value VAPD-MAX of the bias voltage as shown by the equation (2), the resistance value R2 of the resistor 53 is determined according to the value. There must be.

Here, in order to perform continuous gain control on the optical signal power, the minimum value of the bias voltage according to equation (4) is used.
The VAPD-MIN needs to be designed so that the AGC amplifier 3 is provided with an optical signal power at or above the maximum gain. AG
Assuming that the base voltage of the NPN transistor 52 at the optical signal power at which the C amplifier 3 has the maximum gain is VBASE and the base-emitter voltage of the NPN transistor 52 is VBE, the bias voltage at the optical signal power at which the AGC amplifier 3 has the maximum gain VAP
D needs to be equal to or greater than the minimum value of the bias voltage VAPD-MIN according to equation (4), and is given by the following equation. VAPD = (VBASE-VBE) x R1 / R2 ≥ VAPD-MIN (5)

[0011]

The conventional APD shown in FIG.
In the control circuit 5, the currents IAPD1, IAPD2,
The maximum and minimum values of the bias voltage of the APD 1 are determined so as to satisfy the equations (2), (4) and (5) with respect to the saturation voltage VSAT of the NPN transistor 52 and the base voltage VBASE of the NPN transistor 52. And the calculation conditions are complicated. In the worst case, the resistance R1 and the resistance
There is a problem that the resistance value R2 does not exist.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide an APD control circuit which can determine the maximum value and the minimum value of the bias voltage of the APD 1 by a simple design method. I do.

[0013]

A bias control circuit for an avalanche photodiode according to a first aspect of the present invention controls a bias voltage applied to a cathode of the avalanche photodiode by a voltage from a voltage control terminal. , An avalanche photodiode having a cathode connected to an output of a high voltage generation circuit via a resistor, a voltage control current source for controlling a current flowing through the resistor by a voltage from the voltage control terminal, and the resistor An NPN transistor having a collector connected to a higher power supply side terminal of the resistor, an emitter connected to a lower power supply side terminal of the resistor, and a base connected to a clip terminal for outputting a predetermined voltage; and The voltage changes the NPN transistor to the avalanche photodiode. Is intended to determine the lower limit of the voltage applied to the cathode of the over de.

A bias control circuit for an avalanche photodiode according to a second invention is a bias control circuit for an avalanche photodiode for controlling a bias voltage applied to a cathode of an avalanche photodiode by a voltage from a voltage control terminal. A voltage control current source connected to an output of the resistor via a resistor, and controlling a current flowing through the resistor by a voltage from the voltage control terminal; and a collector connected to the high voltage generation circuit,
A first NPN transistor having a base connected to a terminal of the resistor on the voltage control current source side, and a second NPN transistor having a collector connected to the high voltage generation circuit and a base connected to a clip terminal for applying a predetermined voltage. NPN transistor, an avalanche photodiode having a cathode connected to the emitters of the first and second NPN transistors, one end connected to the emitters of the first and second NPN transistors, and the other end grounded A constant current source, wherein a lower limit of a voltage applied to the cathode of the avalanche photodiode by the second NPN transistor is determined by a voltage from the clip terminal.

A bias control circuit for an avalanche photodiode according to a third invention is a bias control circuit for an avalanche photodiode for controlling a bias voltage applied to a cathode of an avalanche photodiode by a voltage from a voltage control terminal. An avalanche photodiode having a cathode connected to the output of the resistor via a resistor, a voltage control current source for controlling a current flowing through the resistor by a voltage from the voltage control terminal, a collector grounded, and A PNP transistor having an emitter connected to the voltage control current source side terminal and a base connected to a clip terminal for applying a predetermined voltage, and the NPN transistor being connected to a cathode of the avalanche photodiode by a voltage from the clip terminal. The upper limit of the applied voltage It is intended Mel.

A bias control circuit for an avalanche photodiode according to a fourth invention is a bias control circuit for an avalanche photodiode for controlling a bias voltage applied to a cathode of an avalanche photodiode by a voltage from a voltage control terminal. A voltage control current source connected to an output of the resistor via a resistor and controlling a current flowing through the resistor by a voltage from the voltage control terminal; and a constant current source having one end connected to the high voltage generation circuit. A first PNP transistor whose collector is grounded and whose base is connected to a terminal of the resistor on the side of the voltage-controlled current source; and a second PNP transistor whose collector is grounded and whose base is connected to a clip terminal for applying a predetermined voltage. A cathode connected to the PNP transistor and the emitters of the first and second PNP transistors; An avalanche photodiode, and a constant current source having one end connected to the emitters of the first and second PNP transistors and the other end connected to the high voltage generating circuit, The second PNP transistor determines the upper limit of the voltage applied to the cathode of the avalanche photodiode.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a diagram showing a configuration example when the APD control circuit according to the present embodiment is used in an optical receiver. In the figure, reference numeral 5 denotes an APD control circuit according to the present embodiment;
Is a control terminal of the voltage controlled current source, 51 is a voltage controlled current source,
52 is an NPN transistor, 53 and 54 are resistors, 55 is a high voltage generation circuit, 56 is a voltage applied to the cathode of the APD,
That is, it is a bias voltage output terminal. 57 is a clip voltage input terminal, and 58 is an NPN transistor. The other parts are the same as those shown in FIG. Shown in FIG.
The APD control circuit 5 has a configuration in which an NPN transistor 58 is connected to both ends of a resistor 54 in a conventional APD control circuit including a voltage control current source 51 and a resistor 54. Here, the collector of the NPN transistor 58 is connected to the high voltage generating circuit 55, the emitter is connected to the connection point between the resistor 54 and the voltage control current source 51, and the bias voltage output terminal 56, and the base has the minimum value of the bias voltage of the APD. , That is, a clip voltage.

Next, the operation will be described. The operation of the optical receiver shown in FIG. 1 is the same as that of the conventional example. The operation of the circuit including the voltage control current source 51 and the resistor 54 of the APD control circuit 5 is the same as that of the conventional APD control circuit, and the maximum value VAPD-MAX of the bias voltage is given by Expression (2). Since a voltage corresponding to the minimum value of the bias voltage is applied to the clip voltage input terminal 57, in this case, the NPN transistor 5
8 is in a non-conductive state.

When the optical signal power increases from the optical signal power at which the voltage at the bias voltage output terminal 56 becomes the maximum value of the bias voltage given by the equation (2), the voltage control current source 51
The voltage of the bias voltage output terminal 56 decreases due to the increase in the current of the bias voltage. At this time, when the voltage of the bias voltage output terminal 56 becomes lower than the voltage applied to the clip voltage input terminal 57, the NPN transistor 58 becomes conductive. The voltage VAPD-MIN of the bias voltage output terminal 56 in this state is given by the following equation, where the voltage of the clip voltage input terminal 57 is VLCLIP and the voltage between the base and the emitter of the NPN transistor 58 is VBE. VAPD-MIN = VLCLIP-VBE (6) Even if the optical signal power further increases and the current of the voltage control current source 51 increases, the current of the voltage control current source 51 flows through the transistor 58, so that the bias voltage output The voltage at terminal 56 is clipped to the voltage given by equation (6). Therefore, according to this circuit configuration, the minimum value of the bias voltage of the APD can be determined only by the voltage applied to the clip voltage input terminal 57 when the base-emitter voltage of the NPN transistor 58 to be applied is determined. In the above example, the voltage control current source 51 is an NPN transistor 52
The operation has been described as being composed of the voltage control current source having another configuration such as a differential type.

Embodiment 2 FIG. 2 is according to the present embodiment.
FIG. 3 is a configuration diagram of an APD control circuit. The optical receiver according to the present embodiment can be configured by replacing the APD control circuit according to the first embodiment in FIG. 1 with the APD control circuit in FIG. 2, reference numeral 50 denotes a control terminal of a voltage control current source, 51 denotes a voltage control current source, 52 denotes an NPN transistor, 53 and 54 denote resistors, 55 denotes a high voltage generation circuit, 56 denotes a bias voltage output terminal, and 57 denotes a clip voltage. Input terminal, 59 is constant current source, 6
0 and 61 are NPN transistors. The APD control circuit shown in FIG. 2 is a conventional APD control circuit comprising a voltage control current source 51 and a resistor 54.
In the APD control circuit, a constant current source 59, an NPN transistor 60,
61 is connected to the clip circuit. Here, the collectors of the NPN transistors 60 and 61 are both connected to the high voltage generation circuit 55, and the emitters are both connected to the constant current source 59 and the bias voltage output terminal 56. The base of the NPN transistor 60 is connected to a connection point between the voltage control current source 51 and the resistor 54, and the base of the NPN transistor 61 is supplied with a voltage corresponding to the minimum value of the bias voltage of the APD, that is, a clip voltage.

Next, the operation of the APD control circuit shown in FIG. 2 will be described. The operation of the circuit including the voltage control current source 51 and the resistor 54 is the same as that of the conventional APD control circuit, and the maximum value of the base voltage of the NPN transistor 60 is
2 given when cut off. At this time, since the base voltage of the NPN transistor 60 is higher than the voltage corresponding to the minimum value of the bias voltage of the APD applied to the base of the NPN transistor 61, the NPN transistor 60 is turned on. Therefore, the maximum value VAPD-MAX of the bias voltage output terminal 56 is obtained by setting the voltage of the high voltage generation circuit 55 to VH and the base-emitter voltage of the NPN transistor 60 to VH.
Assuming that BE1 is the resistance value of the resistor 54, R1 is given by the following equation. VAPD-MAX = VH-VBE1 (7)

When the optical signal power increases from the optical signal power at which the voltage at the bias voltage output terminal 56 becomes the maximum value of the bias voltage given by the equation (7), the voltage control current source 51
, The base voltage of NPN transistor 60 drops. At this time, when the base voltage of NPN transistor 60 becomes lower than the voltage applied to clip voltage input terminal 57, NPN transistor 61 is turned on. The voltage VAPD-MIN of the bias voltage output terminal 56 in this state
The following equation is obtained when the voltage of the clip voltage input terminal 57 is VLCLIP and the voltage between the base and the emitter of the NPN transistor 61 is VBE2. VAPD-MIN = VLCLIP-VBE2 (8) Even if the power of the optical signal further increases and the current of the voltage control current source 51 increases, the current of the constant current source 59 does not exceed the NPN transistor 6
1, the voltage at the bias voltage output terminal 56 is clipped to the voltage given by equation (8). Therefore, according to this circuit configuration, the minimum value of the bias voltage of the APD can be determined only by the voltage applied to the clip voltage input terminal 57 if the base-emitter voltage of the NPN transistor 61 to be applied is determined. In the above example, the operation has been described assuming that the voltage control current source 51 includes the NPN transistor 52 and the resistor 53. However, the same operation can be performed with a voltage control current source having another configuration such as a differential type.

Embodiment 3 FIG. FIG. 3 is according to the present embodiment.
FIG. 3 is a configuration diagram of an APD control circuit. The optical receiver according to the present embodiment can be configured by replacing the APD control circuit according to the first embodiment in FIG. 1 with the APD control circuit in FIG. 3, reference numeral 50 denotes a control terminal of a voltage control current source, 51 denotes a voltage control current source, 52 denotes an NPN transistor, 53 and 54 denote resistors, 55 denotes a high voltage generation circuit, 56 denotes a bias voltage output terminal, and 57 denotes a clip voltage. The input terminal 62 is a PNP transistor. The APD control circuit shown in FIG. 3 has a configuration in which a PNP transistor 62 is connected to a bias voltage output terminal 56 in a conventional APD control circuit including a voltage control current source 51 and a resistor 54. Here, the emitter of the PNP transistor 62 is connected to the bias voltage output terminal 56, the collector is grounded, and the base is supplied with a voltage corresponding to the maximum value of the bias voltage of the APD, that is, a clip voltage.

Next, the operation of the APD control circuit shown in FIG. 3 will be described. The operation of the circuit composed of the voltage control current source 51 and the resistor 54 is the same as that of the conventional APD control circuit, and the minimum value of the bias voltage is given by Expression (4). Since a voltage corresponding to the maximum value of the bias voltage is applied to the clip voltage input terminal 57, the PNP transistor 62 is in a non-conductive state in this case.

When the optical signal power decreases from the optical signal power at which the voltage of the bias voltage output terminal 56 becomes the minimum value of the bias voltage given by the equation (4), the voltage control current source 51
, The voltage of the bias voltage output terminal 56 increases. At this time, when the voltage of the bias voltage output terminal 56 becomes higher than the voltage applied to the clip voltage input terminal 57, the PNP transistor 62 becomes conductive. The voltage VAPD-MAX of the bias voltage output terminal 56 in this state is
If the voltage of the clip voltage input terminal 57 is VLCLIP and the base-emitter voltage of the PNP transistor 62 is VBE, the following equation is obtained. VAPD-MIN = VLCLIP + VBE (9) Even if the power of the optical signal further decreases and the current of the voltage control current source 51 decreases, the high voltage generation circuit 55 supplies the voltage via the resistor 54.
Since a current flows through the PNP transistor 62, the voltage of the bias voltage output terminal 56 is clipped to the voltage given by Expression (9). Therefore, according to this circuit configuration, the maximum value of the bias voltage of the APD is determined by the applied PNP transistor 6.
If the base-emitter voltage is determined, it can be determined only by the voltage applied to the clip voltage input terminal 57. In the above example, the voltage control current source 51
Although the operation has been described as being configured by the N transistor 52 and the resistor 53, the same operation is performed by a voltage control current source having another configuration such as a differential type.

Embodiment 4 FIG. 4 is according to the present embodiment.
FIG. 3 is a configuration diagram of an APD control circuit. The optical receiver according to the present embodiment can be configured by replacing the APD control circuit according to the first embodiment in FIG. 1 with the APD control circuit in FIG. 4, reference numeral 50 denotes a control terminal of a voltage control current source, 51 denotes a voltage control current source, 52 denotes an NPN transistor, 53 and 54 denote resistors, 55 denotes a high voltage generation circuit, 56 denotes a bias voltage output terminal, and 57 denotes a clip voltage. Input terminal, 63 is constant current source, 6
4 and 65 are PNP transistors. The APD control circuit shown in FIG. 2 is a conventional APD control circuit comprising a voltage control current source 51 and a resistor 54.
In the APD control circuit, a constant current source 63, a PNP transistor 64,
65 is connected to the clip circuit. Here, one end of the constant current source 63 is connected to the high voltage generating circuit 55, and the other end is connected to the emitters of the PNP transistors 64 and 65 and the bias voltage output terminal 56.
The collectors of the PNP transistors 64 and 65 are both grounded, and the base of the PNP transistor 64 is a voltage-controlled current source 5
The base of the PNP transistor 65 is supplied with a voltage corresponding to the maximum value of the bias voltage of the APD, that is, a clip voltage.

Next, the operation of the APD control circuit shown in FIG. 4 will be described. The operation of the circuit composed of the voltage control current source 51 and the resistor 54 is the same as that of the conventional APD control circuit, and the minimum value of the base voltage of the PNP transistor 64 is NPN transistor 5
Given when 2 is saturated. At this time, since the base voltage of the PNP transistor 64 is lower than the voltage corresponding to the maximum value of the bias voltage of the APD applied to the base of the PNP transistor 65, the PNP transistor 64 is turned on. Therefore, the bias voltage output terminal 56
Is the minimum value VAPD-MIN of the base-emitter voltage of the PNP transistor 64 as VBE1, the saturation voltage of the NPN transistor 52 as VSAT, the resistance of the resistor 54 as R1, and the resistance of the resistor 53 as VBE1.
If R2, the following equation is obtained. VAPD-MIN = (VH-VSAT) x R2 / (R1 + R2) + VSAT + VBE1 (10)

The voltage at the bias voltage output terminal 56 is given by the equation (1)
When the optical signal power is reduced from the optical signal power having the minimum value of the bias voltage given in (0), the base voltage of the PNP transistor 64 increases due to the decrease in the current of the voltage control current source 51. At this time, when the base voltage of the PNP transistor 64 becomes higher than the voltage applied to the clip voltage input terminal 57, the PNP transistor 65 becomes conductive. The voltage VAPD-MAX of the bias voltage output terminal 56 in this state
The following equation is obtained when the voltage of the clip voltage input terminal 57 is VLCLIP and the base-emitter voltage of the PNP transistor 65 is VBE2. VAPD-MAX = VLCLIP + VBE2 (11) Even if the power of the optical signal further decreases and the current of the voltage control current source 51 decreases, the current of the constant current source 63 remains the PNP transistor 6
5, the voltage at the bias voltage output terminal 56 is clipped to the voltage given by equation (11). Therefore, according to this circuit configuration, the maximum value of the bias voltage of the APD can be determined only by the voltage applied to the clip voltage input terminal 57 if the base-emitter voltage of the PNP transistor 65 to be applied is determined. In the above example, the voltage control current source 51 is an NPN transistor 52
The operation has been described as being composed of the voltage control current source having another configuration such as a differential type.

[0029]

As described above, according to the APD bias voltage control circuits according to the first and second inventions, the minimum value of the APD bias voltage can be determined by the voltage applied to the clip voltage input terminal. The circuit design is easier than the bias voltage control circuit described above.

According to the APD bias voltage control circuit according to the third and fourth aspects of the present invention, the maximum value of the APD bias voltage can be determined by the voltage applied to the clip voltage input terminal. Circuit design becomes easier.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a bias voltage control circuit of an APD according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an APD bias voltage control circuit according to Embodiment 2 of the present invention;

FIG. 3 is a configuration diagram of an APD bias voltage control circuit according to Embodiment 3 of the present invention;

FIG. 4 is a configuration diagram of an APD bias voltage control circuit according to Embodiment 4 of the present invention;

FIG. 5 is a configuration diagram of a conventional optical receiving device.

[Explanation of symbols]

 Reference Signs List 51 voltage control current source 54 resistor 55 high voltage generating circuit 58 NPN transistor 59 constant current source 60 first NPN transistor 61 second NPN transistor 62 PNP transistor 63 constant current source 64 first PNP transistor 65 second PNP transistor

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H04B 10/06

Claims (4)

[Claims] An avalanche photodiode bias control circuit for controlling a bias voltage applied to a cathode of an avalanche photodiode by a voltage from a voltage control terminal, wherein a cathode is connected to an output of a high voltage generation circuit via a resistor. An avalanche photodiode, a voltage control current source that controls the current flowing through the resistor by a voltage from the voltage control terminal, a collector connected to a higher power supply terminal of the resistor, and a lower power supply terminal of the resistor. An NPN transistor having an emitter connected thereto and a base connected to a clip terminal for outputting a predetermined voltage, wherein the NPN transistor determines a lower limit of a voltage applied to a cathode of the avalanche photodiode by a voltage from the clip terminal Avalanche photo-dio Bias control circuit of de. 2. An avalanche photodiode bias control circuit for controlling a bias voltage applied to a cathode of an avalanche photodiode by a voltage from a voltage control terminal, wherein the bias control circuit is connected to an output of a high voltage generation circuit via a resistor, A voltage-controlled current source that controls a current flowing through the resistor by a voltage from a control terminal; a collector connected to the high-voltage generation circuit; and a base connected to a terminal of the resistor on the voltage-controlled current source side. 1
A second NPN transistor having a collector connected to the high voltage generation circuit and a base connected to a clip terminal for applying a predetermined voltage.
An avalanche photodiode having a cathode connected to the emitters of the first and second NPN transistors;
A constant current source having one end connected to the emitters of the first and second NPN transistors and the other end grounded,
A bias control circuit for an avalanche photodiode, wherein the second NPN transistor determines a lower limit of a voltage applied to a cathode of the avalanche photodiode by a voltage from the clip terminal. 3. A bias control circuit for an avalanche photodiode for controlling a bias voltage applied to a cathode of an avalanche photodiode by a voltage from a voltage control terminal, wherein the cathode is connected to an output of the high voltage generation circuit via a resistor. An avalanche photodiode, a voltage control current source for controlling a current flowing through the resistor by a voltage from the voltage control terminal, a collector grounded, an emitter connected to the voltage control current source side terminal of the resistor, a predetermined PNP with base connected to clip terminal that applies
A bias control circuit for an avalanche photodiode, wherein the NPN transistor determines an upper limit of a voltage applied to a cathode of the avalanche photodiode by a voltage from the clip terminal. 4. An avalanche photodiode bias control circuit for controlling a bias voltage applied to a cathode of an avalanche photodiode by a voltage from a voltage control terminal, wherein an output of a high voltage generation circuit is connected via a resistor, A voltage control current source for controlling a current flowing through the resistor by a voltage from a control terminal; a constant current source having one end connected to the high voltage generation circuit; a collector grounded; and the voltage control current source for the resistor. A first PNP transistor having a base connected to a terminal on the side thereof; a second PNP transistor having a collector grounded and having a base connected to a clip terminal for applying a predetermined voltage; and the first and second PNP transistors. An avalanche photodiode whose cathode is connected to the emitter of
A constant current source having one end connected to the emitters of the first and second PNP transistors, and the other end connected to the high voltage generation circuit, wherein the second PNP transistor is connected to a voltage from the clip terminal. Determines the upper limit of the voltage applied to the cathode of the avalanche photodiode.