JPH10283341A - Fast fourier transformation arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit in which fast Fourier transformation can be adaptively performed by the same circuit even when the number K(K<=N) of OFDM(multicarrier orthogonal frequency division multiple modulation system) carrier waves for the number N of input data. SOLUTION: This circuit is constituted so that fast Fourier transformation(FFT) can be attained with the number N of fast Fourier transformation to be processed. In this case, plural basic circuits respectively constituted of a butterfly computing part 1, rotary factor multiplying part 3, and data rearranging circuit 2 are arranged, and the butterfly computing part in which a base can be changed is used for one or plural basic circuit, and those bases are changed or several arithmetic stages are skipped. Thus, even when the number N of the input fast Fourier transformation is changed, the fast Fourier transformation can be operated in the same circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fast Fourier transform used for signal processing, data analysis, linear systems, and the like. The present invention relates to a fast Fourier transform operation circuit capable of performing a Fourier transform (hereinafter abbreviated as FFT).

[0002]

2. Description of the Related Art With the development of digital technology in recent years, preparations have been made for terrestrial television broadcasting to shift from current analog broadcasting to digital broadcasting. In this terrestrial digital television broadcasting, adoption of a multicarrier orthogonal frequency division multiplexing modulation method (hereinafter abbreviated as OFDM) is expected as a modulation method. In this OFDM, a fast Fourier transform is used for modulation and demodulation of a carrier wave. The number N of fast Fourier transform points of the fast Fourier transform used in this modulation scheme depends on the number K of OFDM carriers.

The number of carrier waves K is 1705 in the standard,
6,817, and these standards may be further increased. In order to correspond to the number of the plurality of carriers, it is necessary to prepare dedicated fast Fourier transform operation circuits. Conventional fast Fourier transform operation circuits that can handle a plurality of data points include N / R, N / R ² , (R is a radix) with respect to the point N.
... Only the points divided by the power of R can be calculated.

In addition, there are fast Fourier transform circuits corresponding to a large number of points by providing butterfly operation circuits of different radixes. In this case, however, it is necessary to change the structure of all the rearrangement circuits. Circuit control becomes difficult. Therefore, there is no circuit that can respond to various scores with the same circuit regardless of R and that can easily control changes in the data point sequence.

[0005]

As described above, in the conventional circuit for performing the fast Fourier transform, when the score N is determined, the circuit configuration is uniquely determined. Therefore, there is a problem that even if the number of points of the input data is changed and reduced, the operation cannot be performed by the same circuit.

Further, even in a fast Fourier transform operation circuit capable of changing the score, the score can be changed only by a power of the radix R. That is, there is a problem that the change of the score depends on the radix R.

The present invention has been made in view of the above-mentioned conventional drawbacks, and has as its object to provide a circuit which can set the number of conversion points without being affected by the radix R even if the number of input data points decreases, and perform conversion with the same circuit. It is the purpose.

[0008]

FIG. 1 is a diagram for explaining the principle of the present invention. FIG. 1A shows the concept of data input to a basic circuit, and FIG. 1B shows the basic concept of the present invention. 3 shows a configuration example of a circuit. FIG. 2 shows a configuration example of a butterfly operation circuit in the present invention, and FIG. 3 shows a configuration example of a data rearrangement circuit. The above problem is solved by a fast Fourier transform circuit configured as follows.

(1) Fast Fourier Transform (FF) to be processed
T) A circuit for performing a fast Fourier transform on the number of points N. The R-input basic operation circuit 100 including the butterfly operation unit 1, the twiddle factor multiplication unit 3, and the data rearrangement circuit 2 is defined as one stage, and the number thereof is M. (= Log _R N) (R is a radix)
It is configured to be able to perform fast Fourier transform by arranging in series,
The butterfly operation unit 1 performs a cross operation of the radix R between the R inputs, and the twiddle factor multiplication unit 3 multiplies R-1 outputs of the outputs of the butterfly operation unit 2 by a twiddle factor. The data rearrangement circuit 2 generates a data set required for the second and subsequent operations on the input data N, and can change the radix of the butterfly operation unit 1 by an external control signal. Yes, one or a plurality of basic operation circuits 100 capable of changing the twiddle factor multiplying unit 3 and the data rearrangement circuit 2 according to the radix are provided, and the radix of one or more of the basic operation circuits 100 is changed. Thus, even if the number N of the fast Fourier transform points becomes N / 2, N / 4,... Irrespective of the radix R, the same circuit performs the fast Fourier transform.

(2) The fast Fourier transform operation circuit shown in (1), comprising a signal line for outputting the progress of the butterfly operation, and a selection circuit 5 for selecting a signal of the signal line and another calculation result. Equipped with a butterfly operation unit 1 capable of
The radix can be changed by an external signal.

(3) The fast Fourier transform circuit shown in (1), which is a data rearranging circuit in the basic arithmetic circuit 100, wherein a plurality of variable delay elements 6
A switching circuit 9 that can change the switching state according to the radix; a plurality of delay elements 6, 7, and 8 with variable delay amounts at the output stage; and a radix based on an external control signal. Has a data rearranging circuit capable of responding to changes.

(4) In the fast Fourier transform operation circuit shown in (1), in a circuit in which M stages of basic operation circuits 100 are connected in series, the radix of L stages (L ≦ M) can be changed from the front. This is a basic arithmetic circuit.

(5) In the fast Fourier transform operation circuit shown in (1), all the basic operation circuits 100 are operation circuits whose radix can be changed, and the radix is smaller than R in all the basic operation circuits 100 and the same. In the data rearrangement circuit 2 according to claim 3, the delay amounts of the delay elements 6 and 8 that can change the delay amount are made equal, and the independent input data are Fourier-transformed based on an external control signal. What can be output.

(6) In a multi-carrier orthogonal frequency division multiplexing (OFDM) broadcast receiver, an information separation circuit 22 for extracting an information transmission signal based on a signal from a broadcast wave is provided. Claim 1
In which the radix of the basic arithmetic circuit can be changed and the number of points subjected to Fourier transform can be adaptively changed according to the number of carriers.

In the above configuration, a circuit for performing a fast Fourier transform on the number of fast Fourier transform (FFT) points N to be processed, comprising a butterfly operation unit 1, a twiddle factor multiplication unit 3, and a data rearrangement circuit 2. It is configured by arranging a plurality of arithmetic circuits 100. Among them, the butterfly operation unit 1 of one or a plurality of basic operation circuits 100 has a circuit configuration in which the radix can be changed. By appropriately inputting the input data to this arithmetic circuit, N-point fast Fourier transform results can be obtained.

At this time, by changing the radix of one or a plurality of butterfly operation units 1, N / 2, N / 4,..., Two points of fast Fourier transform can be flexibly performed regardless of the radix R. It becomes possible. Furthermore, by using this arithmetic circuit, the number of arithmetic circuits previously required for each number of fast Fourier transform points can be reduced to a single arithmetic circuit, so that hardware can be reduced. Further, it can correspond to various transmission parameters of digital terrestrial broadcasting and can switch the receiving system instantly.

According to the present invention, a fast Fourier transform corresponding to a plurality of data point sequence numbers is possible without a large increase in hardware. According to the configuration of the present invention, two independent data can be Fourier-transformed at high speed.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 to 3 are views for explaining the principle of the present invention, and FIGS. 4 to 12 are views showing an embodiment of the present invention. FIG. 13 is a diagram for explaining the conventional fast Fourier transform, and FIGS. 14 to 16 show another embodiment of the present invention.

In the present invention, the fast Fourier transform (FF)
T) As shown in FIG. 4, the fast Fourier transform operation circuit having N points is configured by arranging M (= log _R N) basic operation circuits 100. Each basic operation circuit 100 includes a butterfly operation unit 1, a twiddle factor operation unit 3, and a data rearrangement circuit 2. The butterfly operation unit 1 performs a crossing operation shown in FIG. 13, the twiddle factor operation unit 3 multiplies the corresponding twiddle factor by data, and the data rearrangement circuit 2 generates data corresponding to the input of the next stage. Rearrange the data in order to

When the number N of input data decreases in such a fast Fourier transform operation circuit, the radix R in the butterfly operation circuit is changed to cope with the change in the number of input data. An example of an operation in this case is a radix R
Is 4, and the number of fast Fourier transform points is N = 64.

Since 64 = 4 ³ , three basic circuits 100 each comprising a butterfly operation unit 1, a twiddle factor multiplication unit 3, and a data rearrangement unit 2 are arranged in series. FIG. 4 shows the overall configuration of this arithmetic circuit.

The case of executing the fast Fourier transform with 64 data point strings will be described with reference to FIG. Input data A ₀ ...
A ₆₃ is given as the first-stage input as shown in the figure. The first-stage butterfly operation unit 10 performs a radix-4 butterfly operation and outputs data B ₀ ... B ₆₃ . It is necessary to change the data set so that these data are suitable for the second-stage input. This is executed by the data rearranging circuit 11 with the delay amount of 4. Through this data rearranging circuit 11, the data is changed to a data set suitable for the next stage input.

The sorted data B ₀ ... B ₆₃ is input to the butterfly operation unit 12 of the second stage, butterfly computation with a base 4 is executed, the data C ₀ ... C ₆₃ is output.
As in the previous stage, these data are stored in the data rearranging circuit 1.
3, the data set is changed and input to the third-stage butterfly operation unit 14. A radix-4 butterfly operation is performed in the third-stage butterfly operation circuit, and data D ₀ ... D ₆₃ are output. The data D ₀ ... D ₆₃ are the results of the fast Fourier transform.

Next, using this circuit, the number of data point strings 32
The case where the fast Fourier transform of the above is executed will be described with reference to FIG. Input data A ₀ ... A ₃₁ are given as first-stage inputs as shown in the figure, the radix of the first-stage butterfly operation unit 15 is changed, and the radix-2 butterfly operation is performed by this operation unit.
Output data B ₀ ... B ₃₁ of the first-stage butterfly operation unit 15
Are changed in the data rearrangement circuit 16 and input to the next stage. In the second and subsequent stages, a radix-4 butterfly operation is executed in the same manner as in the conversion of 64 points, and the obtained results D _{0 to} D ₃₁ are the results of the fast Fourier transform.

Similarly, when the fast Fourier transform with 16 data points is executed, the input data is 1 as shown in FIG.
The second stage butterfly operation unit 17 and the data rearrangement circuit 18
To skip. C ₀ ... C ₁₆ obtained by performing a radix-4 butterfly operation in an arithmetic circuit thereafter are the results of the fast Fourier transform.

Operations such as changing the radix and skipping the basic arithmetic circuit have the same effect when the number N of data points is further increased, and the circuit shown in FIG.
It can support fast Fourier transform of points.

Next, the change of the radix will be described in detail with reference to FIGS. In this case, the calculation switching method is as follows. As a property of the fast Fourier transform, the fast Fourier transform having a large number of data point sequences internally includes a fast Fourier transform having a small number of data point sequences. Due to this property, the radix-2 butterfly operation uses the radix-2
It can be seen that the butterfly operation is included. Therefore, in an arithmetic circuit capable of switching the radix, the result of the radix-2 butterfly operation is output during the radix-4 butterfly operation.

This is realized by extracting the output of the first stage of the complex adder / subtractor 4 connected in two stages in FIG. This output is connected to the input of the second stage complex adder / subtractor 4 and the input of the selection circuit 5. Since the result calculated by the second-stage complex adder / subtracter 4 is the result of the radix-4 butterfly operation, the selection circuit 5 selects the result of the radix-4 butterfly operation and the result of the radix-2 butterfly operation. By doing so, the radix is changed.

FIG. 9 shows the operation of the butterfly operation unit 1 and the twiddle factor multiplication unit 3 when the radix is 2, and data flows through a path shown by a solid line. At this time, since the twiddle factor is multiplied only by the output B and the output D, the complex multiplier 19 for multiplying the output C is multiplied by 1. The operation of the butterfly operation unit 1 when the radix is 4 is as shown in FIG. 10, and data flows through the solid line portions as in FIG.

Next, skipping of the basic arithmetic circuit will be described. This processing does not perform any operation of the basic operation circuit 100 in a certain stage. Also, since the basic arithmetic circuit 100 to be skipped is always the preceding stage, the basic arithmetic circuit 10
Without adding a special skip circuit to 0, it is sufficient to directly input the next stage of the skipped stage. Therefore, input to a plurality of stages can be performed at the input section of the fast Fourier transform operation circuit, and skip processing can be easily performed by selecting this input line.

Since no additional circuit is provided inside the basic circuit, it is possible to reduce the circuit configuration. In the present invention, the arithmetic circuit to be skipped is always the preceding stage. By doing so, it is possible to perform calculations without making any changes in the calculations after the arithmetic circuit that has performed the skip processing. This can be easily understood from the fact that the order of the last two stages of calculations is the same in FIGS. This property is the same even when the number of data point sequences increases.

The method of changing the data rearrangement circuit 2 will be described in detail with reference to FIGS. The data rearrangement circuit 2 needs to be changed according to the radix R of the butterfly operation unit 1. FIG. 3 shows a configuration used when the radix is 4. In the data sorting circuit 2, first,
A data point sequence is serially input from input A, input B, input C, and input D, respectively.

Each data inputted from the input B, the input C, and the input D is delayed as required by each basic circuit of the fast Fourier transform. At this time, the delay amount of the delay element 7 connected to the input C is twice the delay amount of the delay element 6 connected to the input B, and the delay amount of the delay element 8 connected to the input D is the delay amount of the delay element 6. 3 times the amount.

The delayed data is input to a switching circuit 9 which appropriately allocates four inputs. The switching circuit exchanges data as shown in FIG. After the data exchange, the data of the output A, the output B, and the output C are delayed, and the data output timing is adjusted and output.
In this way, the data is rearranged so as to be a data set required for each basic circuit. FIG. 11 is a block diagram of a circuit corresponding to the radix-2 butterfly operation unit 1.

The operation of the data rearranging circuit 2 corresponding to the radix-2 butterfly operation unit 1 is as follows. The data point sequence is serially input from input A, input B, input C, and input D, respectively, and delays the data input from input B and input D by a required number by the fast Fourier transform. At this time, the delay amounts of the delay elements 6 and 8 connected to the input B and the input D become equal.

Thereafter, the input A and the input B, the input C and the input D
Data exchange is performed between the switching circuits 20 and 21 in FIG.
As shown in FIG. After the data exchange, the output A and the output C are delayed by the number of times performed at the input, the output timing is adjusted, and the output is performed.

In the present invention, the radixes of all the basic arithmetic circuits can be changed, so that two fast Fourier transforms can be executed simultaneously. FIG. 14 is a block diagram of the circuit in this case, and FIG. 15 is a data flow diagram. In this calculation, all the basic calculation circuits 100 calculate the radix as 2. Also, the data rearranging circuit 2 in this case shows the same operation as that of the radix 2 shown above,
The amount of delay in the delay elements 6 and 8 is a number obtained by taking the square root in the above case.

FIG. 16 shows a configuration in which the fast Fourier transform circuit of the present invention is used in a multi-carrier orthogonal frequency division multiplexing (OFDM) receiver. In this case, the carrier wave number K of the broadcast wave can be extracted by a signal from the broadcast wave. This information is separated by the information separation circuit 22 and sent to the control unit 24 of the fast Fourier transform circuit. Based on this information, a control signal is sent from the control unit 24 to the basic circuit 23 of the FFT, and the number of processing points of the fast Fourier transform circuit is changed. In this way, it is possible to instantaneously change the number of fast Fourier transform points N (N ≧ K) corresponding to the number K of OFDM carriers.

In the above embodiment, the circuit configuration method in the case where the radix is 4 has been described as an example. However, the same effect can be obtained even if the radix R is increased, and the hardware can be reduced and the speed can be increased. New effects can be expected.

[0040]

As described above, according to the fast Fourier transform operation circuit of the present invention, even if the number N of data points to be processed is changed to N / 2, N / 4,... Irrespective of the radix R. The same circuit is capable of performing fast Fourier transform. The greatest effect of the present invention is that the use of this arithmetic circuit makes it possible to deal with the fast Fourier transform of various points with a single circuit. As a result, when fast Fourier transform processing is required with various input numbers N, it can be realized with a single hardware,
This can be effective in reducing the amount of material.

According to the first aspect of the present invention, it is possible to cope with the fast Fourier transform of various points with only one circuit.
According to the second aspect of the present invention, the number of the butterfly operation circuits that have been required so far can be reduced to one, which is effective in reducing the number of components. According to the third aspect of the present invention, as in the second aspect, the number of data rearranging circuits can be reduced to one, which is effective in reducing the number of components. According to the fourth aspect of the present invention, the control system is simplified since it has no effect on the rear arithmetic circuit. According to the fifth aspect of the present invention, two arithmetic circuits have been required to execute simultaneously. However, since this operation can be performed by one, there is an effect of reducing the number of components and simplifying the control system. According to the sixth aspect of the present invention, since it is possible to quickly follow the change in the score and to perform the operation with the same circuit, there are effects of reducing the quantity, simplifying the control system, and increasing the speed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a butterfly operation unit in the explanation of the principle of the present invention.

FIG. 3 is a block diagram of a data rearranging circuit in the explanation of the principle of the present invention.

FIG. 4 is a block diagram of a 64-point fast Fourier transform circuit according to an embodiment of the present invention.

FIG. 5 is a data flow diagram of a 64-point fast Fourier transform according to the embodiment of the present invention.

FIG. 6 is a data flow diagram of a 32-point fast Fourier transform according to the embodiment of the present invention.

FIG. 7 is a data flow diagram of a 16-point fast Fourier transform according to the embodiment of the present invention.

FIG. 8 shows a fast Fourier transform operation circuit corresponding to 16 to 16384 points according to the embodiment of the present invention.

FIG. 9 shows an operation when the radix is 2 in the embodiment of the present invention.

FIG. 10 shows an operation when the radix is 4 in the embodiment of the present invention.

FIG. 11 is an operation block diagram of the data rearranging circuit according to the embodiment of the present invention when the radix is 2.

FIG. 12 is an explanatory diagram of an operation of a data rearranging circuit in a 32-point fast Fourier transform according to an embodiment of the present invention.

FIG. 13 is a diagram illustrating a conventional fast Fourier transform.

FIG. 14 shows an arithmetic circuit when all basic arithmetic circuits according to another embodiment of the present invention can be changed.

FIG. 15 is a data flow diagram when two fast Fourier transforms are simultaneously executed according to another embodiment of the present invention.

FIG. 16 is an application of the present invention in an OFDM receiver according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Fast Fourier transform basic circuit 1,10,12,14,15,17 Butterfly operation part 2,11,13,16,18 Data rearrangement circuit 3 Rotation factor multiplier 4 Complex adder / subtracter 5 Selection circuit 6,7,8 Delay element 9, 20, 21 Switch circuit 19 Complex multiplier 22 Control signal separation unit 23 FFT basic circuit group 24 Control unit of fast Fourier transform circuit

Claims (6)

[Claims] 1. A circuit for performing a fast Fourier transform on the number N of fast Fourier transform points to be processed, comprising: an R-input basic operation circuit 100 comprising a butterfly operation unit 1, a twiddle factor multiplication unit 3, and a data rearrangement circuit 2. As one stage, M (= log _R N) (R is a radix) are arranged in series so that fast Fourier transform can be performed. In the butterfly operation unit 1, a radix R crossing operation is performed between the R inputs. The twiddle factor multiplying unit 3 multiplies R-1 outputs among the outputs of the butterfly operation unit 2 by a twiddle factor. The data rearrangement circuit 2 calculates the input data N by 2 Generating a data set required for the operations of the second and subsequent stages; further, the radix of the butterfly operation unit 1 can be changed by an external control signal; One or a plurality of basic operation circuits 100 capable of changing the data rearrangement circuit 2 in accordance with the radix are provided. By changing the radix of one or a plurality of the basic operation circuits 100, the number of the fast Fourier transform points N is N / 2, N / regardless of the radix R
4. A fast Fourier transform operation circuit, wherein the same circuit performs fast Fourier transform even if the following conditions are satisfied. 2. The fast Fourier transform operation circuit according to claim 1, further comprising: a signal line for outputting a progress of the butterfly operation, wherein a signal of the signal line and another calculation result can be selected by a selection circuit. A high-speed Fourier transform operation circuit comprising a butterfly operation unit 1, wherein a radix can be changed by an external signal. 3. The fast Fourier transform operation circuit according to claim 1, wherein the data rearrangement circuit in the basic operation circuit 100 includes a plurality of delay elements 6, 7, and 8 having variable delay amounts at an input stage. A switch circuit 9 capable of changing a switching state according to a radix; a plurality of delay elements 6, 7, and 8 having variable delay amounts at an output stage; and a radix corresponding to the change based on a control signal from the outside. A fast Fourier transform operation circuit, characterized by having a data rearrangement circuit capable of performing (1). 4. The fast Fourier transform operation circuit according to claim 1, wherein the circuit in which the M stages of basic operation circuits 100 are connected in series is configured such that the radix can be changed from L stages (L ≦ M) from the front. A fast Fourier transform operation circuit, which is an operation circuit. 5. The fast Fourier transform operation circuit according to claim 1, wherein all the basic operation circuits 100 are operation circuits whose radix can be changed, and the radix is smaller than R in all the basic operation circuits 100 and the same. Value, and the data rearranging circuit 2
Fast Fourier transform operation characterized in that it is possible to make the delay amounts of the delay elements 6 and 8 capable of changing the delay amounts equal and to perform Fourier transform and output of independent input data based on an external control signal. circuit. 6. A broadcast receiver of the multi-carrier orthogonal frequency division multiplexing modulation method, comprising: an information separation circuit 22 for extracting an information transmission signal based on a signal from a broadcast wave;
A fast Fourier transform for a multi-carrier orthogonal frequency division multiplexing modulation method, wherein the radix of the basic arithmetic circuit is changeable, and the number of Fourier transforms can be adaptively changed according to the number of carriers. Arithmetic circuit.