JP2011227559A - Control information automatic generation method for data sorting circuit, data sorting circuit and control information automatic generation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the design and implementation time of control information for a data sorting circuit.SOLUTION: A data sorting circuit 100 comprises a first delay mechanism 140, a shuffle mechanism 150 for sorting output data of the first delay mechanism 140, and a second delay mechanism 160 for delaying output data of the shuffle mechanism 150. In the data sorting circuit, a shuffle port search procedure for determining an output port number after sorting for each element in data array before sorting, a control information generation procedure for the first delay mechanism to adjust input data based on the amount of delay, and adjust an output time cycle, a shuffle mechanism control information generation procedure for sorting the output data of the first delay mechanism 140, and a control information generation procedure for the second delay mechanism to adjust the output data of the shuffle mechanism 150 based on the amount of delay, and adjust the output time cycle, are performed as a control information generation procedure for the data sorting circuit 100 by a control information automatic generation part 180.

Description

  The present invention relates to a control information automatic generation method, a data rearrangement circuit, and a control information automatic generation program for a data rearrangement circuit that rearranges data by a delay mechanism and a shuffle mechanism.

  In certain signal processing algorithms, it is known that an efficient circuit can be designed by using an arithmetic unit and a data rearrangement circuit constituted by a delay mechanism and a shuffle mechanism. As an example, FFT (Fast / Fourier / Transform) is to design a circuit with high throughput and low area cost by incorporating the above data rearrangement circuit between the butterfly arithmetic unit and the twiddle factor multiplier. Can do.

  In such a circuit incorporating a data rearrangement circuit for a specific algorithm, the delay amount in the delay mechanism and the shuffle method in the shuffle mechanism are fixed, and it can be used other than the algorithm for the designed circuit. was difficult. In view of this, in the data rearrangement circuit, a data rearrangement circuit has been proposed in which the delay amount and the shuffle method can be changed by a program created by the user so as to be compatible with various algorithms. Is shown in FIG.

  The data rearrangement circuit 200 shown in FIG. 22 has the same configuration as the data rearrangement circuit (see Patent Document 5). The data rearrangement circuit 200 includes a counter 201, a control information table 202, a first stage variable delay circuit 203 to 206, a shuffle circuit 207, a second stage variable delay circuit 208 to 211, a control information deleter 212 to 215, And control information combiners 216 to 219. The data rearrangement circuit 200 receives input data (ID # 0 to ID # 3), a mode signal MODE, and a counter reset signal RST, and outputs output data (OD # 0 to OD # 3).

  Here, the mode signal MODE is a signal for designating the sort pattern type (calculation mode) such as 64-point FFT rearrangement and 32-point FFT rearrangement. The counter reset signal RST is a signal for designating the start time of the rearrangement pattern. The counter 201 is reset by a counter reset signal RST, and then counts up every cycle that is a unit of delay amount. In the control information table 202, control information corresponding to the combination of the count value indicated by the counter 201 and the calculation mode indicated by the mode signal MODE is stored. The control information includes the delay amounts of the first-stage variable delay circuits 203 to 206, the control information of the shuffle circuit 207, and the delay amounts of the second-stage variable delay circuits 208 to 211.

  The control information output from the control information table 202 is combined with input data (ID # 0 to ID # 3) in the control information combiners 216 to 219 and input to the first-stage variable delay circuits 203 to 206. Also, the control information is removed from the combined data output from the second-stage variable delay circuits 208 to 211 in the control information deleters 212 to 215. Data obtained by removing control information from the combined data becomes output data (OD # 0 to OD # 3) of the data rearrangement circuit 200.

  There is a related discrete Fourier transform device (see Patent Document 1). An object of the discrete Fourier transform apparatus described in Patent Document 1 is to provide a discrete Fourier transform apparatus and a discrete Fourier inverse transform apparatus that reduce the amount of transform computation and simplify the computation circuit.

  There is also a related fast Fourier transform arithmetic circuit (see Patent Document 2). The fast Fourier transform arithmetic circuit described in Patent Document 2 relates to a fast Fourier transform circuit, and is adaptive with the same circuit even if the number of OFDM carriers K (≦ N) is changed with respect to the number of input data points N. An object of the present invention is to provide a circuit capable of performing fast Fourier transform.

In addition, there is a parallel system that performs array processing with a short waiting time using a related fast Fourier transform (see Patent Document 3). The parallel system described in Patent Document 3 aims to minimize the waiting time in the fast Fourier transform and simplify the connection and design.
There is also a related method and apparatus for performing variable-size high-speed orthogonal transform (see Patent Document 4).

JP 2008-052504 A Japanese Patent Laid-Open No. 10-283341 Japanese Patent Laid-Open No. 11-161637 Special table 2008-506191 gazette Japanese Patent Application No. 2009-218919

The data rearrangement circuit shown in FIG. 22 has a problem that it is difficult to create control information constituting the control information table 202, and that creation takes a long time.
In order to clarify the above problem, first, the operation of the data rearrangement circuit 200 will be described with reference to FIGS. FIG. 23 is a diagram showing a state of data rearrangement in the data rearrangement circuit 200 shown in FIG. FIG. 24 is a diagram showing the contents of the control information table 202 at this time. As the control information registered in the control information table shown in FIG. 24, values for port ID # 0, ID # 1, ID # 2, and ID # 3 are described for each of the first-stage delay, shuffle, and second-stage delay. Has been.

  In the time chart shown in FIG. 23, the count value of the counter 201 is reset in the first cycle (cycle 0) because the count reset signal is valid. Since the mode signal is 001 during the first four cycles (cycles 0 to 3), the control information in the first row of the control information table shown in FIG. 24 is read out in the first cycle. The read control information is combined with the input data in the control information combiners 216 to 219 and input to the first-stage variable delay circuits 203 to 206. In FIG. 23, the data combined with the control information is expressed in the form of “data name (first stage delay amount, shuffle control signal, second stage delay amount)”. This data will be referred to as combined data.

For example, when the count value is 0000 (cycle 0), the delay amount at the first stage with respect to the data A input to the input port # 0 is 2, so that the input data A in the first cycle has control information of 2-cycle delay. Combined and output from the variable delay circuit 203 at the first stage in cycle 2.
Similarly, in the count value 0001 (cycle 1), the data C input to the input port # 0 has a delay amount of 4 in the first stage with respect to the input port # 0 of the count value 0001 in FIG. Control information indicating a delay of 4 cycles is combined and output from the variable delay circuit 203 at the first stage in cycle 5. Note that the control information in the combined data is delayed or shuffled together with the data in the combined data.

In cycle 3 (count value 0003), the combined data E input to the input # 0 of the shuffle circuit 207 includes control information whose shuffle control information indicates 1. Therefore, the combined data B at the input # 1 of the shuffle circuit 207 is output to the output # 0 of the shuffle circuit 207 in cycle 3. Similarly, the combined data E at the input # 0 of the shuffle circuit 207 is output to the output # 1 of the shuffle circuit 207.
The combined data B input to the input # 0 of the second stage variable delay circuit 208 in cycle 3 includes 1 as the second stage delay amount. For this reason, the combined data B is output from the variable delay circuit 208 at the second stage in cycle 4, which is the next cycle. Similarly, since the second-stage delay amount of the combined data E input to the input # 1 of the second-stage variable delay circuit 209 in cycle 3 is 0, the combined data E has two stages in cycle 3, which is the same cycle. Output from the variable delay circuit 209 of the eye.

  Here, when the user creates control information for controlling the operation, the user must grasp and program all the operations. That is, the user must grasp the input data to each variable delay circuit for each cycle, the control method, and the state of the counter up, and it takes a lot of time for design, implementation, and debugging.

  The main object of the present invention is to reduce the time required for designing, implementing, and debugging control information for controlling rearrangement in a data rearrangement circuit.

  The present invention has been made to solve the above problems, and the control information automatic generation method of the present invention provides a data rearrangement circuit for rearranging and outputting the output order of input data and the arrangement between ports. A control information automatic generation method that generates control information that controls the output order and rearrangement of input data. Each element is assigned a unique value, the row is the time cycle, and the column is the port number. A data array and a rearranged data array indicating a rearrangement state of the data after rearrangement of the data array before rearrangement by the data rearrangement circuit are input, and the data array before rearrangement and the rearrangement are input. The control information is automatically generated based on the post-replacement data array.

  In the control information automatic generation method of the present invention, the control information for the data rearrangement circuit is automatically generated based on the “data array before rearrangement” and “data array after rearrangement”. As a result, the time required for designing, implementing, and debugging the control information for controlling the data rearrangement circuit can be shortened.

It is a figure which shows the structure of the data rearrangement circuit concerning embodiment of this invention. It is a figure which shows the structural example of a control information coupling | bonding mechanism. It is a figure which shows the structural example of a 1st delay mechanism. It is a figure which shows the structural example of a shuffle mechanism. It is a figure which shows the structural example of a control information separation mechanism. It is a flowchart which shows the procedure of control information automatic generation. It is a figure which shows the pseudo code of a shuffle port search procedure. It is a figure which shows the pseudo code of the function search_port. It is a figure which shows the pseudo code of the control-information production | generation procedure for 1st delay mechanisms. It is a figure which shows the pseudo code of function initialize_fd_port. It is a figure which shows the pseudo code of function do_fd_search. It is a figure which shows the pseudo code of the function modify_delay_array. It is a figure which shows the pseudo code of the control information generation procedure for shuffle mechanisms. It is a figure which shows the pseudo code of the control-information production | generation procedure for 2nd delay mechanisms. It is a figure which shows the pseudo code of function get_sdu_val. FIG. 5 is a diagram illustrating “data array before rearrangement” and “data array after rearrangement” in the first embodiment. It is a figure which shows the specific example of a shuffle port search procedure. It is a figure which shows the specific example of the control information generation procedure for 1st delay mechanisms. It is a figure which shows the specific example of the control information generation procedure for shuffle mechanisms. It is a figure which shows the specific example of the control information production | generation procedure for 2nd delay mechanisms. It is a figure which shows the example in the case of implementing this invention by software. It is a figure which shows the example of a data rearrangement circuit. It is a time chart which shows the mode of the data rearrangement in the rearrangement circuit of FIG. It is a figure which shows the content of the control information table in the data rearrangement circuit shown in FIG.

[First Embodiment]
Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a data rearrangement circuit 100 according to the embodiment of the present invention. The data rearrangement circuit 100 shown in FIG. 1 includes a counter 110, a control information table 120, a control information combination mechanism 130, a first delay mechanism 140, a shuffle mechanism 150, a second delay mechanism 160, and a control information separation mechanism 170. .

  Input data (ID # 0 to ID # M-1), mode signal MODE and counter reset signal RST are input to the data rearrangement circuit 100, and output data (OD # 0 to OD # M-1) is output. . Here, the mode signal MODE and the counter reset signal RST are signals that operate in the same manner as the mode signal MODE and the counter reset signal RST shown in FIG. The control information stored in the control information table 120 is automatically generated based on the “data array before rearrangement” and “data array after rearrangement” created and input by the user in the control information automatic generation unit 180. To be created.

  Here, the “data array before rearrangement” and the “data array after rearrangement” are each represented by a matrix of size N × M (a matrix of N rows and M columns). The column number M corresponds to the input ID # 0 to ID # M-1 (port number) of the data rearrangement circuit 100, and indicates data input to the data rearrangement circuit 100 at the same time. On the other hand, the row number N represents the input time cycle of data input to the data rearrangement circuit 100, and 0, 1, 2,..., N−1 are the first cycle input and the second cycle, respectively. Input, third cycle input,..., N-1 cycle input. Also, unique data is allocated to each element in the array of “data array before rearrangement”. As an example, the “data array before rearrangement” shown in FIG. 1 shows a state in which natural numbers of 0 to (N−1) × (M−1) are stored in elements. In addition, unique data is allocated to each element in the “data array after rearrangement”, and each element has a one-to-one correspondence with the element of “data array before rearrangement”.

FIG. 2 is a diagram illustrating a configuration example of the control information combining mechanism 130. As shown in FIG. 2, the control information combining mechanism 130 is a unit configured by arranging control information combiners 131 in parallel in M stages, and includes input data ID # 0 to ID # M-1 and an input control signal (control information). IC # 0 to IC # M-1 are combined and output.
FIG. 3 is a diagram illustrating a configuration example of the first delay mechanism. As shown in FIG. 3, the first delay mechanism 140 is a unit in which variable delay circuits 141 are arranged in parallel in M stages, and input data # 0 to # M−1 are respectively connected to control signals (controls). Information) and output to outputs # 0 to # M-1. Here, the configuration and operation of the variable delay circuit 141 are the same as those of the variable delay circuit 206 shown in FIG. The second delay mechanism 160 has the same configuration as the first delay mechanism 140 shown in FIG.

FIG. 4 is a diagram illustrating a configuration of the shuffle mechanism 150. The shuffle mechanism 150 shown in FIG. 4 is configured by arranging a control information extractor 151 and a selector 152 in M stages in parallel. The shuffle mechanism 150 replaces the arrangement of the input data # 0 to # M-1 and outputs it to the output data # 0 to # M-1. Here, the configuration and operation of the shuffle mechanism 150 are the same as those of the shuffle circuit 207 shown in FIG.
FIG. 5 is a diagram showing the configuration of the control information separation mechanism. The control information separation mechanism 170 has a configuration in which the control information deleters 171 are arranged in M stages. The control information deleter 171 deletes the control signal (control information) combined with the input data and outputs it.

  Next, a method for automatically generating control information stored in the control information table 120 will be described. As shown in FIG. 6, the control information automatic generation method according to the present invention includes a shuffle port search procedure (step S101), a first delay mechanism control information generation procedure (step S102), and a shuffle mechanism control information generation procedure (step S103). ) And the second delay mechanism control information generation procedure (step S104).

First, the shuffle port search procedure (step S101) will be described with reference to FIGS. In this shuffle port search procedure, the “data array before rearrangement” and the “data array after rearrangement” are scanned, and each element in the “data array before rearrangement” passes through the data rearrangement circuit 100 to determine which port. Is recorded in the “shuffle port array” of N rows and M columns.
FIG. 7 shows the pseudo code shuffle_port_search for the shuffle port search. In this pseudo code, the “data array before rearrangement” is data_bef, and the “data array after rearrangement” is data_aft. The output “shuffle port array” is indicated by shuffle_port. FIG. 8 shows the contents of the search_port function on the 10th line in FIG. Here, the search_port function is a function that takes one index src and array data_aft as arguments, checks which column of the array specified by the argument is the same, and returns the column number.

  In the code shown in FIG. 7, first, as shown in the sixth line, the process from the seventh line to the 14th line is repeated in the Nth line of the input data. Further, as shown in the seventh row, the processing from the eighth row to the thirteenth row is applied to the row M column of the input data. Next, on the ninth line, the index designated as the element in the row col column of the “data array before reordering data_bef” is acquired. In the 10th row, the search_port function is called to obtain in which column of the “sorted data array data_ft” the index acquired in the 9th row is located. This result is set in the row col column of the “shuffle port array shuffle_port”.

  Next, the search_port function shown in FIG. 8 will be described. In the search_port function, first, as shown in the third row, the processing from the fourth row to the tenth row is performed in the Nth row of the “sorted data array data_ft” given by the argument. Further, as shown in the fourth row, the processing from the fifth row to the ninth row is applied to each of the M columns of the row in the “data array after rearrangement”. Next, in the fifth line, the index src given by the argument is compared with the index in the row col column of the “rearranged data array data_aft”. Here, if these indexes match, the column number col is stored in the temporary variable result. If they do not match, no processing is performed. Finally, a temporary variable “result” is returned, and the process ends.

  By the above-described shuffle port search procedure (step S101), as shown in the lower diagram of FIG. 7, the “data array before data rearrangement data_bef” and “data array after rearrangement data_aft” are scanned, and “data before rearrangement” It analyzes which port each element of the “array” is output after passing through the data rearrangement circuit 100 and records it in the “shuffle port array shuffle_port” of N rows and M columns.

  Next, the first delay mechanism control information generation procedure (step S102) will be described with reference to FIGS. In the first delay mechanism control information generation procedure (step S102), as shown in the lower diagram of FIG. 9, “pre-sort data array data_bef” and “shuffle port array shuffle_port” are input, and “ The first delayed data array fd_data_bef ”,“ first delayed shuffle port array fd_shuffle_port ”, and“ first delay mechanism control information fd_array ”are output. Here, the “first delay mechanism control information fd_array” represents delay information for each element in the “pre-sort data array data_bef” in an array format.

The pseudo code shown in FIG. 9 is pseudo code make_fdu_array indicating the first delay mechanism control information generation procedure (step S102). In the first delay mechanism control information generation procedure (step S102), first, in the fifth line, the initial post-delay data array fd_data_bef and the first post-delay shuffle port array fd_shuffle_port are initialized by the initialize_fd_port function. To do. Here, FIG. 10 shows the processing contents of the Initialize_fd_port function.
As illustrated in FIG. 10, the Initialize_fd_port function includes the “pre-sort data array data_bef” and “shuffle data array” in the 0th column of the “first post-delay data array fd_data_bef” and the “first post-delay shuffle port array fd_shuffle_port”, respectively. Initialization is performed by substituting the 0th column of the port array shuffle_port.

  Next, as shown in the 13th line of FIG. 9, the do_fd_search function is called for the Nth row and the first to M−1th columns of the “pre-sort data array data_bef” and “shuffle port array shuffle_port”. Search for a data rearrangement method by the first delay mechanism. Here, the do_fd_search function is a function that searches for a position where the element of the shuffle port array that is currently searched for does not match data indicating another shuffle port in the same row after the first delay. The processing content of this do_fd_search function is shown in FIG.

  As shown in FIG. 11, the do_fd_search function has, as inputs, one element of “data array before rearrangement”, one element of “shuffle port array”, a column number at the time of calling the function, and a generation It has a “first delayed data array fd_data_bef” and a “first delayed shuffle port array fd_shuffle_port”. In this function, as shown in the processing from the 4th line to the 11th line, one element of the input shuffle port array is used as a source, and the “first post-delay shuffle port array” in the middle of the generation is column-by-line. Search for matches in the direction. Next, as shown in the 12th to 17th lines, when the column numbers at the time of calling do not match, the “first post-delay data array” and the “first post-delay shuffle port array” are generated. 1 element of the “data array before rearrangement” and 1 element of “shuffle port array” are respectively assigned to the column number and the corresponding row at the time of calling. Finally, return the line and exit the function.

Next, in FIG. 9, on the 16th line after the end of the do_fd_search function, the difference of the current line number is obtained from the line number returned from the do_fd_search function, and is registered in the “first delay mechanism control information fd_array”.
Finally, on the 19th line, the delay set in the “first delay mechanism control information fd_array” is adjusted by the modify_delay_array function shown in FIG. This is a function that, when a delay having a negative value is set in the input argument array fd_array, adds the value to the entire fd_array to correct all elements to a positive or zero value. Specifically, the minimum value in the array is searched from the 4th line to the 12th line in FIG. Next, in the 14th to 19th lines, a process of adding the value obtained by inverting the sign of the found minimum value to all the elements in the array is performed.

  As described above, in the first delay mechanism control information generation procedure (step S102), based on the “shuffle port array shuffle_port” and the “pre-sort data array data_bef”, a plurality of ports are assigned to the same port in the same time cycle. “First delay mechanism control information fd_array” is generated to adjust the time cycle in which each element is output according to the delay amount so that the element is not output redundantly.

  Next, the shuffle mechanism control information generation procedure (step S103) will be described with reference to FIG. FIG. 13 is a pseudo code make_shuffle_array for generating control information for the shuffle mechanism. In this shuffle mechanism control information generation procedure, as shown in the lower diagram of FIG. 13, it has “first delayed data array fd_data_bef” and “first delayed shuffle port array fd_shuffle_port” as inputs. The rear data array sh_data_bef ”and the“ shuffle mechanism control information sh_array ”are output.

  In this shuffle mechanism control information generation procedure, as shown in the 4th to 14th lines in FIG. 13, the following processing is performed for each element in N rows and M columns. First, the element “desport” of the “first delayed shuffle port array fd_shuffle_port” corresponding to each element of the “first delayed data array fd_data_bef” is read out. In FIG. 13, this corresponds to the seventh and eighth lines. Next, the read data is assigned to the column indicated by destination in the row row of the “data array after shuffle”. Further, the destination is substituted into the row col column of the “shuffle mechanism control information sh_array”.

  As described above, in the shuffle mechanism control information generation procedure (step S103), rearrangement is performed so that the port numbers recorded in the “first delayed shuffle port array fd_shuffle_port” match the output ports. , Each element in the “first delayed data array fd_data_bef” is also rearranged, and “shuffle mechanism control information sh_array” is determined according to the information on the rearrangement method for each element in the “first delayed data array fd_data_bef”. Is generated.

  In this procedure, the control information array is generated as described above. However, this may be changed to a procedure according to the target architecture. For example, in the shuffling mechanism of the data rearrangement circuit disclosed in the previously-disclosed invention (Patent Document 5), it may be configured to select which output port to output for each input port. From which input port data may be selected for each output port. In the latter case, in the generation of the “shuffle mechanism control information sh_array” in this procedure, the current column number col may be substituted for the row row and the destination column.

Next, the second delay mechanism control information generation procedure (step S104) will be described with reference to FIGS. FIG. 14 is a diagram illustrating pseudo code make_sdu_array of the second delay mechanism control information generation procedure. In this second delay mechanism control information generation procedure, as shown in the lower diagram of FIG. 14, it has “shuffled data array sh_data_bef” and “reordered data array data_aft” as inputs. The mechanism control information sdu_array "is output.
In this procedure, as shown in the 4th to 14th rows in FIG. 14, the following processing is performed for each element of the N row and M column array. First, the data of sh_data_bef in the row row col column is read to data. Next, the get_sdu_val function is executed with data, data_aft, and row as inputs, the second delay mechanism control information for data is obtained, and it is registered in the row row col column of sdu_array.

  Details of the get_sdu_val function are shown in FIG. The get_sdu_val function searches the input data array data_aft element by element using the input data as a key, and calculates the difference between the line number row at the time of matching and the input now_row. Obtain control information. Further, as shown in the twelfth line of FIG. 14, the generated second delay mechanism information is adjusted by the modify_delay_array function already shown in FIG.

  As described above, in the second delay mechanism control information generation procedure (step S104), the time cycle is adjusted according to the delay amount so that the “post-shuffle data array sh_data_bef” and the “rearranged data array data_aft” match. Rearrangement is performed, and information on the rearrangement method is generated as “second delay mechanism control information sdu_array”.

  Through the procedure described above, the first delay mechanism control information, the shuffle control information, and the second delay mechanism control information necessary for the data rearrangement circuit 100 shown in FIG. 1 are obtained. Each element of these data arrays uniquely corresponds to each element of the pre-sort data array, the first delayed data array, and the shuffled data array, and each information is stored using each index as a key. If arranged in the memory, a control memory can be configured. Here, regarding the method of configuring the control memory, individual tables may be prepared for each piece of information, or all of them may be arranged together in one table.

[Other Embodiments]
Next, as another embodiment of the present invention, there is an automatic generation of control information by this method for a configuration in which the first delay mechanism, the shuffle mechanism, and the second delay mechanism in FIG. As an example, a configuration without the second delay mechanism is conceivable. In this case, the automatic generation of control information by this method is configured not to perform the second delay mechanism control information generation procedure (step S104).

As another example, a configuration without the first delay mechanism is conceivable. In the automatic generation of control information by this method in this case, the data array before rearrangement and the shuffle port array obtained by the shuffle port search are input to the shuffle mechanism control information generation procedure (step S103), respectively. The first post-delay data array fd_data_bef ”and the“ first post-delay shuffle port array fd_shuffle_port ”are input and processing is performed.
As yet another example, a configuration having only a delay mechanism is conceivable. In this case, the configuration may be such that the shuffle port search procedure, the first delay mechanism control information generation procedure, and the shuffle mechanism control information generation procedure are skipped and only the second delay mechanism control information generation procedure is performed. Moreover, the structure of only a shuffle mechanism can be considered. In this case, the configuration may be such that only the shuffle port search procedure and the shuffle mechanism control information generation procedure are performed.

  Finally, the control information automatic generation method of the present invention may be applied to various embodiments disclosed in the previously-disclosed prior application invention (Patent Document 5). For example, in the above-mentioned previously-disclosed prior application, as a method for referring to the control information table, the maximum counter value is set for each mode, and the counter value is divided by the maximum counter value for each mode. It is also possible to refer to the control information table using the remainder, or to refer to the control information table using a part of the bit string of the counter extracted so as to be within the maximum value of the counter for each mode. ing. The control information automatic generation method of the present invention can be applied to any of these methods.

  Next, a method for automatically generating control information in the data rearrangement circuit of the present invention will be described using a specific embodiment. Here, an example will be described based on the first embodiment. Furthermore, for simplification of explanation, N = 4 and M = 4, and “data array before rearrangement” and “data array after rearrangement” are assigned indexes A to P as shown in FIG. Array.

  First, a specific procedure of the shuffle port search will be described with reference to FIG. FIG. 17 shows a state where a “shuffle port array” is generated from the “data array before rearrangement” and the “data array after rearrangement”. Note that the row number and the column number are appended to the “sorted data array”. As an example, in the element A in the 0th row and the 0th column of the “data array before rearrangement” indicated by shading, the column number including the element A of the “data array after rearrangement” is 0. Therefore, 0 is written in the 0th row and the 0th column of the shuffle port array. On the other hand, the element M in the third row and the 0th column of the “data array before rearrangement” is located in the third column in the “data array after rearrangement”. Therefore, 3 is described in the third row and the zeroth column of the shuffle port array.

Next, a specific example of the procedure for generating the first delay mechanism control information will be described with reference to FIG. FIG. 18 shows how the input “data array before rearrangement” and “shuffle port array” change in the procedure for generating control information for the first delay mechanism, the data array after the first delay, and the shuffle after the first delay. 2 shows the output state of the port arrangement and the control information for the first delay mechanism.
First, in the state shown in the upper left figure (A) of FIG. 18 showing the state at the start of this procedure, each element in the first column of the shuffle port array surrounded by a thick black line is shaded. When the same number is set as compared with the number of the element in the 0 column, the process of shifting the rows is performed.

Specifically, the element at the 0th row and the 1st column in the shuffle port array in FIG. 9A is 0, but when this value is compared with the element at the 0th row and the 0th column in the same array, they match. Therefore, since the element is different from the element in the first row and the zeroth column, the value in the first row and the first column is set to the first row and the first column as shown in the shuffle port array in FIG. . Further, in this process, since the value of the 0th row and the first column is moved to the first row and the first column, the delay necessary for the movement is calculated as 1. Therefore, 1 is set in the element of the 0th row and the 1st column of the first delay mechanism control information.
Further, the element in the 0th row and the first column of the “data array before rearrangement” is moved to the first row and the first column in accordance with the above movement. This process is repeated for all elements in the first column. When this process ends, the array is in the state shown in FIG.

  Next, the process moves to the second column. When the shuffle port array in the lower left (B) of FIG. 18 is viewed in the 0th row and the second column, 0 is set. When this value is compared with the 0th row and the 0th column of the same array, the same number is set. Therefore, when the first row and the 0th column in the same array are viewed, different elements are set. However, since the same element is set when looking at the first row and the first column, it can be seen that the first row cannot be set. Therefore, when the comparison of the second row is performed, it can be seen that values different from those of the second row and the second column are set in the second row, the zeroth column, and the second row, the first column. Therefore, the element in the second row and second column of the same array is set in the second row and second column. Furthermore, since the delay required for this movement is calculated as 2, it is set to 2 in the 0th row and the 2nd column of the first delay mechanism control information. Also, in accordance with this, the element at row 0 and column 2 of the “data array before rearrangement” is moved to row 2 and column 2 (see FIG. (C)). Similarly, when the processing in the third column is performed, the first post-delay shuffle port array shown in FIG. 4D and the first delay mechanism control information shown in FIG.

  In this way, in the state surrounded by the dotted lines, each element indicated by the thick black line is compared with the element indicated by the shaded portion, and the same element is moved to the same line in the same line. Delay information can be generated by repeating the process.

  Finally, looking at the generated first delay mechanism control information (FIG. (E)), there is a place where a negative value is set. On the other hand, a process for eliminating the negative value is performed by searching for the minimum value in the array and adding a value obtained by inverting the sign of the value to all elements. Specifically, looking at the arrangement of the first delay mechanism control information shown in FIG. (E), the minimum value is -3. Therefore, if 3 whose sign is inverted is added to all the elements, the first delay mechanism control information in which the negative value is eliminated can be generated as shown in FIG.

  As described above, in the first delay mechanism control information generation procedure, a plurality of elements are not output to the same port in the same time cycle based on the “shuffle port array” and the “pre-sort data array”. As described above, the control information for the first delay mechanism that adjusts by delaying the time cycle in which each element is output is generated, and the “first data mechanism” after the “data array before rearrangement” is delayed by the first delay mechanism. A data array after one delay "and a" first delay shuffle port array "indicating the state of the shuffle port array are generated and output.

Next, a specific example of the procedure for generating the shuffle mechanism control information will be described with reference to FIG. FIG. 19 shows changes in “data array after first delay” and “port array for shuffle after first delay”, “data array after shuffle” and “control for shuffle mechanism” in the control information generation procedure for shuffle mechanism. The state of the output of “information” is shown.
First, in the state of FIG. 19A showing the state at the start of this procedure, the 0th row of the “first post-delay shuffle port array” indicated by shading is searched for and after shuffling. The rearrangement process is performed so that the array becomes 0, 1, 2, 3. As an example, since 3 is set in the 0th row and the 1st column of the same array, the element in the 0th row and the 1st column of the same array and the first delayed data array is set in the 0th row and the 3rd column accordingly. Moving. Further, 3 is set in the 0th row and the first column of the control information for the shuffle mechanism. By repeating this process, the “data array after shuffle” and “control information for shuffle mechanism” can be finally obtained.

  In this way, in the generation procedure of the shuffle mechanism control information, based on the “first post-delay data array” and the “first post-delay shuffle port array”, the “shuffle post-delay shuffle port array” is included. Reordering is performed so that the recorded port numbers match the output ports, and each element in the “first delayed data array” corresponding to each element of the “first delayed shuffle port array” is also used. Rearrangement is performed to create a “after-shuffle data array”, and further, rearrangement information for each element in the “first delayed data array” is generated as control information for the shuffle mechanism.

Next, a specific example of the procedure for generating the second delay mechanism control information will be described with reference to FIG. FIG. 20 shows how the data arrangement after shuffling changes and how the second delay mechanism control information is generated according to the second delay mechanism control information generation procedure.
First, in the state of the upper left figure (A) of FIG. 19 showing the state at the time of starting this method, the elements indicated by shading of “data array after shuffle” and “data array after rearrangement” are compared, They are rearranged so that they are in the same order, and the delay required for the rearrangement is described in the second delay mechanism control information shown in FIG.

  As an example, in the state of FIG. 20A at the upper left of FIG. 20, the arrangement of both arrays is from the 0th line to the 3rd line and matches A, B, C, and D. For this reason, there is no need for rearrangement. Therefore, 0 is described in all elements in the 0th column of the control information for the second delay mechanism in FIG. Next, in the state of the figure (B) shown by the arrow from the figure (A), the first columns of both arrays are compared. Here, for example, when looking at the 0th row and the first column, the element of the “data array after shuffle” is H, whereas the element of the “data array after rearrangement” is E. It is necessary to rearrange the “distribution data string”. Further, it is understood that the element H of the “data array after shuffle” is in the third row and the first column in the “data array after rearrangement”. Therefore, the delay required to re-arrange the element H in the 0th row and the first column of the “data array after shuffle” in the third row and the first column is calculated as 3, and this information is used as the second delay mechanism control information. In the 0th row, 1st column element.

  When the process is repeated in this manner, the array shown in the second delay mechanism control information in FIG. Here, since there are negative values in this array, it is necessary to adjust them all to positive values or zero. Therefore, the sign of the minimum value −3 in the array is inverted and added to all elements of the array. The array generated thereby is the array shown as the second delay mechanism control information adjusted so as to eliminate the negative value shown in FIG. (G), and this is the output of the second delay mechanism control information generation. Become.

  As described above, in the second delay mechanism control information generation procedure, the “data array after shuffle” and the “data array after rearrangement” are compared, and the “data array after shuffle” matches the “data array after rearrangement”. Thus, rearrangement is performed by adjusting the delay amount, and information on the rearrangement method is generated as second delay mechanism control information.

  Although the embodiments and examples of the present invention have been described above, the counter 110, the control information table 120, the control information combining mechanism 130, the first delay mechanism 140, the shuffle mechanism 140, the first in the data rearrangement circuit 100 described above have been described. The processing units of the 2-delay mechanism 160, the control information separation mechanism 170, and the control information automatic generation unit 180 may be realized by dedicated hardware, and some or all of the functions of each processing unit May be recorded on a computer-readable recording medium, and the program recorded on the recording medium may be read into a computer system and executed to implement the function. Here, the “computer system” includes an OS and hardware such as peripheral devices. The computer-readable recording medium is a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like.

  For example, as shown in FIG. 21, a control information automatic generation program 191 created by a user is stored in a memory (magnetic disk or the like) in a PC (personal computer) 193 or an external recording medium 192, and this control information automatic generation When the computer in the PC 192 reads and executes the program 191, as a result, the control information 194 for the data rearrangement circuit can be obtained.

  Here, the correspondence between the present invention and the above-described embodiment will be supplementarily described. The data rearrangement circuit in the present invention corresponds to the data rearrangement circuit 100, the delay mechanism in the present invention corresponds to the first delay mechanism 140 and the second delay mechanism 160, and the shuffle mechanism in the present invention corresponds to the shuffle mechanism 150. Correspond. The control information automatic generation unit 180 corresponds to the control information automatic generation unit in the present invention. Further, “data array before rearrangement” in the present invention corresponds to “data array before rearrangement data_bef”, and “data array after rearrangement” in the present invention corresponds to “data array after rearrangement data_aft”. Also, the first delay mechanism control information in the present invention corresponds to “first delay mechanism control information fd_array”, and the first delayed data array in the present invention corresponds to “first delayed data array fd_data_bef”. The first post-delay shuffle port array in the present invention corresponds to the “first post-delay shuffle port array fd_shuffle_port”, and the second delay mechanism control information in the present invention is “second delay mechanism control information”. sdu_array "corresponds. Further, the shuffle mechanism control information in the present invention corresponds to the shuffle mechanism control information sh_array, and the post-shuffle data array in the present invention corresponds to the “after-shuffle data array sh_data_bef”, and the shuffle port array in the present invention. Corresponds to the “shuffle port array shuffle_port”.

In the control information automatic generation method according to the above-described embodiment, control for controlling the output order of input data and how to rearrange the data rearrangement circuit 100 that rearranges and outputs the output order of input data and the order between ports. A control information automatic generation method for generating information, in which a unique value is assigned to each element, a row is an output time cycle, a column is a port number, a “pre-sort data array data_bef”, and “pre-sort data The “array data_bef” is inputted with “reordered data array data_aft” indicating the rearrangement state of the data after being rearranged by the data rearrangement circuit 100, and “pre-reordered data array data_bef” and “after rearrangement”. Based on the data array “data_aft”, the control information is automatically generated.
In such an automatic control information generation method, control information for the data rearrangement circuit 100 is automatically generated based on the “data array before data rearrangement data_bef” and “data array after rearrangement data_aft”. Thereby, the time required for the design, implementation, and debugging of control information for controlling the data rearrangement circuit 100 can be shortened.

In the control information automatic generation method of the above embodiment, the data rearrangement circuit 100 includes the first delay mechanism 140 and the second delay mechanism 160 that can control the delay amount, and the shuffle mechanism 150 that can control the shuffle method. Control information is generated for each of the first delay mechanism 140, the second delay mechanism 160, and the shuffle mechanism 150.
In such a control information automatic generation method, the data rearrangement circuit 100 configured by a combination of the first delay mechanism 140 and the second delay mechanism 160 capable of controlling the delay amount and the shuffle mechanism 150 capable of controlling the shuffle method. On the other hand, the delay amount control information in the first delay mechanism 140 and the second delay mechanism 160 and the rearrangement method control information in the shuffle mechanism 150 are generated.
Thereby, control information for the delay mechanisms 140 and 160 and control information for the shuffle mechanism 150 can be generated. For this reason, the time required for the design, implementation, and debugging of the control information for controlling the data rearrangement circuit 100 can be shortened.

In the control information automatic generation method of the above embodiment, the data rearrangement circuit 100 uses the first delay mechanism 140 that delays input data and the output data of the first delay mechanism 140 as input data, and shuffles the input data. And a second delay mechanism 160 that delays the input data using the output data of the shuffle mechanism 150 as input data. Shuffle port search procedure for determining the output port number after rearrangement of each element in the pre-replacement data array data_bef, and control information for the first delay mechanism for adjusting the input data according to the delay amount and adjusting the output time cycle Control information generator for shuffle mechanism that rearranges the generation procedure and the output data of the first delay mechanism 140 When, by adjusting the delay amount output data of the shuffling mechanism 150, a second delay mechanism for control information generation step of adjusting the time cycle to be output, is performed.
In such a control information automatic generation method, input data (data array before rearrangement) is rearranged by sequentially passing through the first delay mechanism 140, the shuffle mechanism 150, and the second delay mechanism 160. In order to generate the control information necessary for this, the output port number after the rearrangement of each element in the “pre-rearrangement data array data_bef” is determined by the shuffle port search procedure. Next, the first delay mechanism control information generation procedure adjusts the time cycle in which each element is output according to the delay amount so that a plurality of elements are not output to the same port in the same time cycle. At the same time, control information for the first delay mechanism is generated. Subsequently, each element in the “data array after the first delay mechanism” whose time cycle is adjusted by the first delay mechanism control information generation procedure by the shuffle mechanism control information generation procedure is the port to be finally output. Rearrangement is made so as to match the position, and at the same time, control information for the shuffle mechanism is generated. Subsequently, each element in the “data array after shuffle” shuffled by the control information generation procedure for shuffle mechanism matches the elements in the “data array after rearrangement” by the second delay mechanism control information generation procedure. The time cycle is adjusted according to the delay amount, and at the same time, the second delay mechanism control information is generated.
Thereby, the control information for each of the first delay mechanism 140, the shuffle mechanism 150, and the second delay mechanism 160 can be automatically and sequentially generated.

Further, in the control information automatic generation method of the above embodiment, the shuffle port search procedure is based on the “data array before data rearrangement data_bef” and “data array after data rearrangement data_aft”. It is determined which port is output, and a “shuffle port array shuffle_port” indicating the determination result is created.
In such a control information automatic generation method, the “pre-sort data array data_bef” and the “pre-sort data array data_ft” are scanned by a shuffle port search procedure, and each element of the “pre-sort data array data_ft” After passing through the rearrangement circuit 100, which port is output is analyzed, and it is recorded in the “shuffle port array shuffle_port” of N rows and M columns.
Thereby, it is possible to analyze which port each element in the “data array before data rearrangement data_bef” is output after passing through the data rearrangement circuit 100 and generate a shuffle port array shuffle_port ”.

Further, in the control information automatic generation method of the above embodiment, the first delay mechanism control information generation procedure is the same in the same time cycle based on the “shuffle port array shuffle_port” and the “pre-sort data array data_bef”. Generate “first delay mechanism control information fd_array” that adjusts the time cycle in which each element is output according to the delay amount so that a plurality of elements are not output to the port in duplicate. “first post-delay data array fd_data_bef” after delaying “data_bef” by the first delay mechanism 140 and “first post-delay shuffle port array fd_shuffle_port” showing the state after rearrangement in the “shuffle port array shuffle_port” Is generated.
In such a control information automatic generation method, in the first delay mechanism control information generation procedure, a plurality of ports are allocated to the same port in the same time cycle based on the “shuffle port array shuffle_port” and the “pre-sort data array data_bef”. The time cycle in which each element is output is adjusted according to the delay amount so that the elements of (the elements in the pre-sorted data array) are not output, and at the same time, “first delay mechanism control information fd_array” Is generated.
Thereby, the “first delay mechanism control information fd_array” for the second delay mechanism 140 can be generated. Then, by controlling the first delay mechanism 140 using this “first delay mechanism control information fd_array”, it is possible to control so that a plurality of elements are not output to the same port in the same time cycle.

Further, in the control information automatic generation method of the above embodiment, the shuffle mechanism control information generation procedure is based on the “first delayed data array fd_data_bef” and the “first delayed shuffle port array fd_shuffle_port”. The port numbers recorded in the post-delay shuffle port array fd_shuffle_port are rearranged so as to match the output ports, and the “first delay shuffle port array fd_shuffle_port” corresponding to each element of the “first post-delay shuffle port array fd_shuffle_port” The elements in the 1-delayed data array fd_data_bef are also rearranged to create a “shuffled data array sh_data_bef”, and information on the rearrangement method for each element in the “first delayed data array fd_data_bef”. `` Sh To generate as Waffles mechanism for control information sh_array ".
In such an automatic control information generation method, the port numbers recorded in the “first post-delay shuffle port array fd_shuffle_port” are rearranged so as to match the output ports, and the “first Rearrangement is also performed for each element in the post-delay data array fd_data_bef. Then, the rearrangement method information for each element in the “first delayed data array fd_data_bef” is generated as “shuffle mechanism control information sh_array”.
Thereby, the “shuffle mechanism control information sh_array” for the shuffle mechanism 150 can be generated. Then, the shuffle mechanism 150 is controlled by the “shuffle mechanism control information sh_array”, and rearrangement is performed so that each element in the “first delayed data array fd_data_bef” matches the port position to be output. be able to.

In the control information automatic generation method of the above embodiment, the second delay mechanism control information generation procedure compares “post-shuffle data array sh_data_bef” and “post-reorder data array data_aft”, and determines “post-shuffle data array”. Each element in the “sh_data_bef” is rearranged by adjusting the delay amount so as to coincide with each element in the “sorted data array data_aft”, and information on the rearrangement method is displayed as “second delay mechanism control information”. sdu_array ".
In such a control information automatic generation method, the second delay mechanism control information generation procedure is such that each element in the “post-shuffle data array sh_data_bef” matches each element in the “post-sort data array data_aft”. Further, rearrangement is performed by adjusting the time cycle according to the delay amount, and information on the rearrangement method is generated as “second delay mechanism control information sdu_array”.
Thereby, the “shuffle mechanism control information sh_array” for the second delay mechanism 160 can be generated. Then, by controlling the second delay mechanism 160 with this “shuffle mechanism control information sh_array”, the elements in the “shuffled data array sh_data_bef” are rearranged so as to match the time cycle to be output. be able to.

  Although the embodiment of the present invention has been described above, the data rearrangement circuit 100 and the control information automatic generation unit 180 according to the present invention are not limited to the illustrated examples described above, and do not depart from the gist of the present invention. Of course, various changes can be made within the range.

100 ... Data rearrangement circuit, 110 ... Counter,
120 ... control information table, 130 ... control information combining mechanism,
131 ... Control information combiner, 140 ... First delay mechanism, 141 ... Variable delay circuit, 150 ... Shuffle mechanism, 151 ... Control information extractor, 152 ... Selector, 160 ... Second delay mechanism, 170 ... Control information separation mechanism,
171 ... Control information deleter, 180 ... Control information automatic generation unit,
ID # 0 to ID # M-1 ... input data,
IC # 0 to IC # M-1... Input control signal (control information),
OD # 0 to OD # M-1 ... output data,
data_aft ... rearranged data array,
data_bef ... data array before rearrangement,
fd_array ... control information for the first delay mechanism,
fd_data_bef ... first delayed data array,
fd_shuffle_port ... Port array for shuffle after the first delay,
sdu_array ... control information for the second delay mechanism,
sh_array ... Control information for shuffle mechanism,
sh_data_bef: data array after shuffling,
shuffle_port ... Port array for shuffle

Claims (9)

A control information automatic generation method for generating control information for controlling an output order and rearrangement of the input data for a data rearrangement circuit that rearranges and outputs an output order of input data and an arrangement between ports,
A unique value is assigned to each element, the pre-sort data array with rows as output time cycles and columns as port numbers,
The pre-sorting data array, a post-sorting data array indicating a sorting state of the data after sorting by the data sorting circuit;
As input,
A control information automatic generation method, wherein the control information is automatically generated based on the pre-sort data array and the post-sort data array. The data rearrangement circuit includes:
It consists of a combination of a delay mechanism that can control the amount of delay and a shuffle mechanism that can control the shuffle method,
The control information automatic generation method according to claim 1, wherein control information is generated for each of the delay mechanism and the shuffle mechanism. The data rearrangement circuit includes:
A first delay mechanism for delaying input data;
A shuffle mechanism that uses the output data of the first delay mechanism as input data and shuffles the input data;
A second delay mechanism that uses the output data of the shuffle mechanism as input data and delays the input data;
With
By the control information automatic generation unit,
As a procedure for generating the control information,
A shuffle port search procedure for determining an output port number after rearrangement of each element in the pre-sort data array;
A first delay mechanism control information generation procedure for adjusting input data according to a delay amount and adjusting a time cycle of output;
A shuffle mechanism control information generation procedure for rearranging output data of the first delay mechanism;
Adjusting the output data of the shuffle mechanism according to the delay amount, and adjusting the time cycle to output, the second delay mechanism control information generation procedure;
The method for automatically generating control information according to claim 2, wherein: The shuffle port search procedure includes:
Based on the data array before sorting and the data array after sorting,
4. The control information automatic generation method according to claim 3, further comprising: determining to which port each element of the pre-sort data array is output, and creating a shuffle port array indicating the determination result. The first delay mechanism control information generation procedure includes:
Based on the shuffle port array and the pre-sort data array, the time cycle in which each element is output is adjusted by the delay amount so that a plurality of elements are not output to the same port in the same time cycle. Generating control information for the first delay mechanism;
And a first post-delay data array after the pre-sort data array is delayed by a first delay mechanism;
A first post-delay shuffle port array showing a state after rearrangement in the shuffle port array;
The control information automatic generation method according to claim 4, wherein the control information is generated. The shuffle mechanism control information generation procedure is as follows:
Based on the first delayed data array and the first delayed shuffle port array,
The port numbers recorded in the first post-delay shuffle port array are rearranged so as to match the output ports, and after the first delay corresponding to each element of the first post-delay shuffle port array Reorder each element in the data array to create a data array after shuffling,
Furthermore, the information of the rearrangement method with respect to each element in the data array after said 1st delay is produced | generated as control information for shuffle mechanisms, The control information automatic generation method of Claim 5 characterized by the above-mentioned. The second delay mechanism control information generation procedure includes:
Comparing the shuffled data array and the rearranged data array;
Rearrangement is performed by adjusting the delay amount so that each element in the post-shuffle data array matches each element in the rearranged data array, and information on the rearrangement method is provided as second delay mechanism control information. The method according to claim 6, wherein the control information is automatically generated.   A data rearrangement circuit, wherein data rearrangement is controlled by the control information generated in the control information automatic generation method according to any one of claims 1 to 7.   A computer-readable control information automatic generation program for executing the control information automatic generation method according to any one of claims 1 to 7.

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