JP7086321B2 - Frequency analyzer, frequency analysis method, control circuit and storage medium - Google Patents

Description

The present disclosure relates to a frequency analysis device for performing frequency analysis, a frequency analysis method, a control circuit, and a storage medium.

Conventionally, as a method of identifying a frequency band used for communication or the like from a wide band frequency spectrum, for example, a technique of setting an appropriate threshold value and searching for a frequency having a power level exceeding the threshold value from the spectrum has been used (). For example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2019-208282

When searching for a target frequency using the threshold value determination as described in Patent Document 1, it is necessary to appropriately set the threshold value in order to perform the search with high accuracy. However, it is difficult to set an appropriate threshold value in an environment where the received power level fluctuates, such as a moving object. Also, in mobiles, the frequency used for communication may change, so it is necessary to perform a search in real time. Here, instead of searching for the target frequency by threshold value determination, a method is conceivable in which the entire acquired frequency spectrum is simply sorted based on the received power level, and the frequency band having a high received power level is used as the search result. .. In the case of this method, there is no problem that it is difficult to set the threshold value appropriately as described above. However, in general, the sorting process has a high calculation cost, and when the target spectrum has a wide band and it is necessary to sort and analyze the spectrum in real time, an increase in the circuit scale becomes a problem.

The present disclosure has been made in view of the above, and an object of the present invention is to obtain a frequency analysis device that realizes miniaturization of a circuit that simultaneously performs frequency analysis and sorting processing.

In order to solve the above-mentioned problems and achieve the object, the present disclosure performs a fast Fourier transform using a butterfly arithmetic circuit and delay buffers provided before and after the butterfly arithmetic circuit, and also executes a fast Fourier transform. It is a frequency analyzer that performs sorting processing of the obtained data, and performs sorting processing using the delay buffer at the timing when the delay buffer is not used in the fast Fourier transform.

The frequency analysis device according to the present disclosure has an effect that a circuit that simultaneously performs frequency analysis and sorting processing can be miniaturized.

The figure which shows the hardware composition of the circuit which the frequency analysis apparatus which concerns on Embodiment 1 presupposes. The figure which shows the structure of the butterfly arithmetic circuit The figure which shows the structure of a switch circuit The figure which shows the signal processing timing in the MDC type FFT realized by the frequency analysis apparatus shown in FIG. The figure which shows the structural example of the frequency analysis apparatus which concerns on Embodiment 1. The figure which shows the specific example of the sort process by the frequency analysis apparatus which concerns on Embodiment 1. A flowchart showing a sort process performed by the frequency analysis device according to the first embodiment. The figure which shows the specific example of the sorting operation performed by the frequency analysis apparatus which concerns on Embodiment 1. The figure which shows the configuration example of the processing circuit when the frequency analysis apparatus is realized by a processor and a memory. A flowchart showing a sort process performed by the frequency analysis device according to the second embodiment. The figure which shows the result of the sort process by the frequency analysis apparatus which concerns on Embodiment 2.

Hereinafter, the frequency analysis device, the frequency analysis method, the control circuit, and the storage medium according to the embodiment of the present disclosure will be described in detail with reference to the drawings.

Embodiment 1.
FIG. 1 is a diagram showing a hardware configuration of a circuit premised on the frequency analysis device according to the first embodiment. Specifically, FIG. 1 shows the hardware configuration of a frequency analysis device that performs an MDC (Multi-path Delay Commutator) type FFT when the number of FFT (Fast Fourier Transform) points is N = 8. ..

The frequency analysis apparatus 100 shown in FIG. 1 includes delay buffers 1 ₁ to ₁₅ , butterfly arithmetic circuits 2 ₁ and 2 ₂ , switch circuits 3 ₁ and 32 ₂ , multipliers 4 ₁ and 4 ₂ , and a control unit 10. And prepare. The frequency analysis device 100 is composed of three stages, that is, FFT stage (stage) # 1, FFT stage # 2, and FFT stage # 3.

Here, "z ^{-N / x} " (x = 2, 4, 8) described in each of the delay buffers 1 ₁ to ₁₅ represents the amount of delay given to the input signal by the number of samples. Since N = 8 in this embodiment, for example, the delay buffer 11 described as “z ^{−N / 2} _” gives the input signal a delay of 4 sample times.

The butterfly arithmetic circuits 2 ₁ and 2 ₂ have the same configuration and perform the same processing. Further, the switch circuits 3 ₁ and 3 ₂ have the same configuration and perform the same processing. In the following description, when it is not necessary to distinguish between the butterfly arithmetic circuit 2 ₁ and the butterfly arithmetic circuit 2 ₂ , these are referred to as the butterfly arithmetic circuit 2. Similarly, when it is not necessary to distinguish between the switch circuit 3 ₁ and the switch circuit 3 ₂ , these are referred to as the switch circuit 3.

FIG. 2 is a diagram showing the configuration of butterfly arithmetic circuits _{2 1} and 22. As shown in FIG. 2, the butterfly arithmetic circuit 2 outputs the sum of two inputs from the upper path and outputs the difference between the two inputs from the lower path.

_FIG . ₃ is a diagram showing the configuration of the switch circuits 31 and 32. The "sel" shown in FIG. 3 corresponds to the "sel1" and "sel2" shown in FIG. As shown in FIG. 3, the switch circuit 3 includes two selectors having two inputs and one output. Data signals s1 and s2 and control signals sel signals are input to each selector. When the sel signal is 0, each selector outputs the signal input from the side described as 0, and when the sel signal is 1, outputs the signal input from the side described as 1. Therefore, when the sel signal is 0, the switch circuit 3 transmits the input of s1 to P1 and the input of s2 to p2, and when the sel signal is 1, the input of s1 is transmitted to p2 and s2. The input is transmitted to p1.

Returning to the description of FIG. 1, in the frequency analysis device 100, the first FFT stage, FFT stage # ₁ , is composed of a delay buffer 1 ₁ , a butterfly arithmetic circuit 2 ₁ , and a multiplier 41. The second FFT stage, FFT stage # 2, is composed of delay buffers 1 ₂ , 1 ₃ and a butterfly arithmetic circuit 2 ₂ , a switch circuit 3 ₁ and a multiplier 4 ₂ . The third FFT stage, FFT stage # 3, is composed of delay buffers 1 ₄ , ₁₅ and a switch circuit 32 ₂ .

The signal x (n), which is an input to the frequency analysis device 100, is branched into two systems and input to the delay buffer 1 ₁ and the butterfly arithmetic circuit 2 ₁ of the FFT stage # 1. The delay buffer 1 ₁ gives the input signal x (n) a delay of 4 sample times, and inputs the signal b (n) to the butterfly arithmetic circuit 2 ₁ . That is, the signal x (n) and the signal b (n) are input to the butterfly calculation circuit 2 ₁ . One of the two outputs of the butterfly arithmetic circuit 2 ₁ is input to the switch circuit 3 ₁ of the FFT stage # 2, and the other is input to the multiplier 4 ₁ . The multiplier 4 ₁ multiplies the input signal from the butterfly arithmetic circuit 2 ₁ by W ^k , which is a Twiddle factor input from the control unit 10, and outputs the input signal to the delay buffer 1 ₂ of the FFT stage # 2. The Twiddle factor is also called a rotation factor and is expressed by the following equation (1). In the following description, it is described as a rotation factor W ^k . This rotation factor W ^k is a complex coefficient used in the FFT operation.

The delay buffer 1 ₂ delays the input signal from the multiplier 4 ₁ by two sample times, and then inputs the input signal to the switch circuit 3 ₁ . The switch circuit 3 ₁ outputs the input signal from the butterfly calculation circuit 2 ₁ to one of the delay buffer 1 ₃ and the butterfly calculation circuit 2 ₂ according to the state of the sel 1 signal input from the control unit 10, and is sent from the delay buffer 1 ₂ . The input signal is output to the other of the delay buffer 1 ₃ and the butterfly arithmetic circuit 2 ₂ .

The signal c (n) output by the switch circuit 3 ₁ is input to the butterfly calculation circuit 2 ₂ , and the signal d (n) output by the delay buffer 1 ₃ is input to the butterfly calculation circuit 2 2. One of the two outputs of the butterfly arithmetic circuit 2 ₂ is input to the switch circuit 3 ₂ of the FFT stage # 3, and the other is input to the multiplier 4 ₂ .

The multiplier 4 ₂ multiplies the input signal from the butterfly arithmetic circuit 2 ₂ by the rotation factor W ^k input from the control unit 10 and outputs the input signal to the delay buffer 1 ₄ of the FFT stage # 3.

The delay buffer 1 ₄ delays the input signal from the multiplier 4 ₂ by one sample time, and then inputs the input signal to the switch circuit 3 ₂ . The switch circuit 3 ₂ outputs the input signal from the butterfly calculation circuit 2 ₂ to one of the outside of the delay buffer 1 ₅ and the frequency analysis device 100 according to the state of the sel 2 signal input from the control unit 10, and from the delay buffer 1 ₄ Is output to the other outside the delay buffer ₁₅ and the frequency analyzer 100.

Although FIG. 1 shows a hardware configuration when the number of FFT points is N = 8, frequency analysis is performed by connecting m stages in cascade to perform FFT processing with N = 2 ^m of FFT points. The device is feasible.

FIG. 4 is a diagram showing signal processing timing in the MDC type FFT realized by the frequency analysis device 100 shown in FIG. x (n) represents the time series data that is the target of the FFT. In FIG. 4, b (n), c (n) and d (n) correspond to b (n), c (n) and d (n) shown in FIG. 1, respectively. sel1 and sel2 correspond to sel1 and sel2 shown in FIG. 1, respectively. Further, BF 2 (1) shows two outputs of the butterfly calculation circuit 2 ₁ shown in FIG. 1, and BF 2 (2) shows two outputs of the butterfly calculation circuit 2 ₂ shown in FIG.

Since FIG. 1 is a circuit that performs an 8-point FFT, the input signal x (n) is divided into 8 samples, and the result of performing the FFT is output. In the timing chart shown in FIG. 4, the blank part indicates the timing when the delay buffer is not used. The frequency analysis apparatus according to the embodiment described later performs sorting processing at a timing when the delay buffer included in the circuit configuration for performing the MDC type FFT, which corresponds to the delay buffers 1 ₁ to ₁₅ shown in FIG. 1, is not used in the FFT. By using it, the memory usage is reduced.

FIG. 5 is a diagram showing a configuration example of the frequency analysis device according to the first embodiment. The frequency analysis device 101 according to the present embodiment has a configuration in which the comparators _{5 1} to 55 are added to the frequency analysis device 100 shown in FIG. 1 described above.

In FIG. 5, the arrow shown by the broken line represents the flow of the sorting process. The sorting process has the same number of stages (sorting stages) as the number of stages of the MDC type FFT to be mounted, and is realized by flowing the data to be sorted in the opposite direction of the signal path of the FFT. The data to be sorted by the frequency analysis device 101 is the frequency analysis result obtained by the frequency analysis device 101 performing the MDC type FFT. That is, the frequency analysis device 101 performs a fast Fourier transform on the input signal and sorts the frequency domain signal obtained by the fast Fourier transform.

The comparator 5 ₁ compares the first data, which is one of the data stored in the delay buffer 1 ₁ , with the second data, which is the data immediately before being input to the delay buffer 1 ₁ , and the comparison result. Based on the above, a sort process including a control of reading the first data from the delay buffer 1 ₁ and a control of writing the second data to the delay buffer 1 ₁ is performed. The same applies to the comparators _{5 2} to 55. The comparators _{5 2} to 55 constitute a comparison unit.

FIG. 6 shows a specific example of the sorting process at each stage executed by the comparators _{5 1} to 55. FIG. 6 is a diagram showing a specific example of the sort process by the frequency analysis device 101 according to the first embodiment. In the case of the example shown in FIG. 6, the frequency analysis device 101 sorts the data according to the procedure shown in (2) to (10) under the condition shown in (1).

In FIG. 6, four blocks (squares) represent delay buffers in sorting stage # 3 (L _N = 4) shown in FIG. 5, and one block represents one buffer. That is, the delay buffer is composed of four buffers. _The shaded blocks indicate the buffers selected by the comparator 51 as comparison targets. In this example, the delay buffer consists of four buffers. The buffer selection method is realized, for example, by addressing the memory. FIG. 6 shows an example of a sorting process in which '1', '2', '3', '7', '0', '4', '5', and '6' are sorted in ascending order.

In the sorting process in sorting stage # 3, first, the first 4 samples out of the 8 samples to be sorted are stored in 4 buffers, and the data stored in the first buffer and the 4 samples not stored in the buffer are stored. Compare with the data at the beginning of. In the example shown in FIG. 6, "1", "2", "3", and "7" are stored in the buffer, and "1" and "0" are compared.

As a result of comparison, the smaller data is output as a sort result. In the example shown in FIG. 6, since the data '0' on the side not stored in the buffer is smaller, this is output. Next, the data stored in the first buffer and the beginning of the remaining three samples not stored in the buffer are compared. Of the two data to be compared, the data stored in the buffer is the first data, and the data not stored in the buffer is the second data. In the example shown in FIG. 6, '1' and '4' are compared. In this case, since the data '1' stored in the buffer is smaller, this is output, the data '4' that is not output is stored in the first buffer, and the values in the buffer are replaced. Next, the comparison pointer indicating the buffer in which the data to be compared is stored is incremented, and the data stored in the second buffer is changed to the comparison target. Then, the data stored in the second buffer and the head of the remaining two samples not stored in the buffer are compared. In the example shown in FIG. 6, '2' and '5' are compared. In this case, since the data '2' stored in the buffer is smaller, this is output, the data '5' that is not output is stored in the second buffer, and the values in the buffer are replaced. Next, the comparison pointer is incremented and the data stored in the third buffer is changed to the comparison target. Hereinafter, the data is rearranged in the same manner.

An example of sorting the data in ascending order is shown, but it is also possible to sort the data in descending order. When sorting in descending order, the data stored in the buffer and the data not stored in the buffer may be compared, and then the data having the larger value may be output as the sorting result.

FIG. 7 is a flowchart showing a sort process performed by the frequency analysis device 101 according to the first embodiment. In the initial state at the start of the operation shown in FIG. 7, k = 0 and n = L _N. In FIG. 7, buff [k] represents the kth value in the delay buffer 1, and tail [n] represents the nth value of the samples to be input to the delay buffer 1.

First, the frequency analysis device 101 stores the head L _N sample in a buffer (step S11), and compares buff [k] and tail [0] (step S12).

When buff [k] ≧ tail [0] (step S12: No), the frequency analysis device 101 bypasses the buffer and outputs tail [0] (step S13). On the other hand, in the case of buff [k] <tail [0] (step S12: Yes), the frequency analyzer 101 takes out buff [k] from the buffer and stores the tail [0] in the buffer (step S14). The frequency analyzer 101 then increments k (step S15).

After executing step S13 or S15, the frequency analysis device 101 sets tail [i] = tail [i + 1] (step S16). That is, the frequency analysis device 101 sets the tail [i + 1] as a comparison target with the buff [k]. Next, the frequency analysis device 101 decrements n (step S17) and confirms whether n> 0 (step S18). When n> 0 (step S18: Yes), the frequency analysis device 101 returns to step S12 and continues the operation.

On the other hand, when n ≦ 0 (step S18: No), the frequency analysis device 101 takes out the data in each buffer constituting the delay buffer 1 in order from the beginning (step S19), and ends the sort process.

FIG. 8 is a diagram showing a specific example of the sorting operation performed by the frequency analysis device 101 according to the first embodiment. FIG. 8 specifically shows an operation of sorting so that the values of 8 samples are in ascending order in a circuit having 3 stages. In each stage shown in FIG. 8, the shaded value is the target of sorting. The blocks (squares) represent one buffer that constitutes the delay buffer for each stage. In stages # 2 and # 3, the shaded blocks indicate the buffer in which the values to be compared are stored.

In stage # 1, sorting is performed by the method described above for the first two samples before they are stored in the buffer. This process is sequentially executed for 8 samples. As a result, the first two samples and the last two samples are sorted in ascending order. In stage # 2, sorting is performed on the four samples from the beginning after the sorting is completed in stage # 1. This process is sequentially executed for 8 samples. As a result, the first 4 samples and the last 4 samples are sorted in ascending order. Further, in stage # 3, sorting is performed on 8 samples after the sorting of 4 samples from the beginning is completed in stages # 1 and # 2, and as a result, the 8 samples are sorted in ascending order.

Next, the hardware configuration of the frequency analysis device 101 according to the present embodiment will be described. The frequency analyzer 101 is a processing circuit which is dedicated hardware, specifically, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), and an FPGA (Field Programmable). It is realized by Gate Array) or a processing circuit that combines these.

Further, the processing circuit that realizes the frequency analysis device 101 may be a control circuit composed of a processor that executes a program stored in the memory and the memory. FIG. 9 is a diagram showing a configuration example of a processing circuit when the frequency analysis device 101 is realized by a processor and a memory. The processor 201 is a CPU (also referred to as a CPU (Central Processing Unit, central processing unit, processing unit, arithmetic unit, microprocessor, microprocessor, processor, DSP (Digital Signal Processor)). The memory 202 is, for example, a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), an EEPROM (registered trademark) (Electrically Erasable Programmable Read Only Memory), or the like. A program for operating as each part of the frequency analysis device 101 is stored in the memory 202, and the frequency analysis device 101 is realized by reading and executing this program by the processor 201. In the frequency analysis device 101, some components may be realized by dedicated hardware, and the remaining components may be realized by the processor 201 and the memory 202 shown in FIG. When some or all of the components of the frequency analyzer 101 are realized by the processor 201 and the memory 202, the program stored in the memory 202 is, for example, a CD (Compact Disc) -ROM, a DVD (Digital Versatile Disc)-. It may be provided to a user or the like in a state of being written in a storage medium such as a ROM, or may be provided via a network.

As described above, the frequency analysis device 101 according to the present embodiment includes an arithmetic circuit that performs MDC type FFT, and delays the delay buffers arranged before and after the butterfly arithmetic circuit constituting the arithmetic circuit by fast Fourier transform. Used for sorting processing when the buffer is not needed. According to the frequency analysis device 101, the buffer can be shared between the FFT circuit and the sort circuit, and the frequency analysis process and the sort process can be realized at the same time with a small amount of resources. That is, it is possible to reduce the size of the circuit that performs the frequency analysis process and the sort process.

Embodiment 2.
Next, the frequency analysis device according to the second embodiment will be described. The frequency analysis device according to the second embodiment has the same configuration as the frequency analysis device 101 according to the first embodiment, and the content of the sort process is partially different. In the present embodiment, a part different from the first embodiment will be described. Further, for convenience of explanation, the frequency analysis device according to the second embodiment will be referred to as a frequency analysis device 102.

FIG. 10 is a flowchart showing a sort process performed by the frequency analysis device 102 according to the second embodiment. Steps S11 to S19 of the flowchart shown in FIG. 10 are the same as steps S11 to S19 of the flowchart shown in FIG. 7. That is, the flowchart shown in FIG. 10 is obtained by adding steps S21 to S33 to the flowchart shown in FIG. 7. Specifically, the flowchart shown in FIG. 10 executes step S21 when the determination in step S18 of the flowchart shown in FIG. 7 is "No", and when the determination in step S21 is "Yes". Steps S22 to S33 are executed. The description of steps S11 to S19 will be omitted.

When the frequency analysis device 102 determines in step S18 that n ≦ 0 (step S18: No), the frequency analysis device 102 confirms whether k is other than 0 (step S21). When k is 0 (k = 0) (step S21: No), the frequency analysis device 102 executes step S19 and ends the sort process.

On the other hand, when k is other than 0 (k ≠ 0) (step S21: Yes), the frequency analysis device 102 sets k to the variable t, that is, t = k (step S22), and t and L _N. Are compared (step S23). When t <L _N (step S23: Yes), the frequency analyzer 102 compares buff [0] with buff [t] (step S24).

When buff [0]> buff [t] (step S24: Yes), the frequency analysis device 102 takes out buff [t] from the buffer and outputs it (step S25), increments t (step S26), and steps. Return to S23.

Further, when t ≧ L _N (step S23: No) and when buff [0] ≦ buff [t] (step S24: No), the frequency analysis device 102 sets the variable m to 0 (step). S27), m and k are compared (step S28). When m <k (step S28: Yes), the frequency analysis device 102 takes out the buffer [m] from the buffer and outputs it (step S29), increments m (step S30), and returns to step S28.

On the other hand, when m ≧ k (step S28: No), the frequency analysis device 102 compares t and L _N (step S31). When t <L _N (step S31: Yes), the frequency analysis device 102 takes out the buffer [t] from the buffer and outputs it (step S32), increments t (step S33), and returns to step S31. On the other hand, when t ≧ L _N (step S31: No), the frequency analysis device 102 ends the sort process.

FIG. 11 is a diagram showing the result of sorting processing by the frequency analysis device 102 according to the second embodiment. FIG. 11 shows the result when the frequency analysis device 102 performs the sorting process under the conditions of the number of samples 4096 and the number of stages 11.

As described above, the frequency analysis device 102 according to the second embodiment sorts according to the same procedure as the frequency analysis device 101 according to the first embodiment, and when the value is finally taken out from the delay buffer, the delay buffer is used. Output while sorting the stored values. Specifically, the frequency analysis device 102 outputs the values from the comparison position k in the delay buffer until a value equal to or higher than the value at the beginning of the delay buffer is found, and then outputs the values from the beginning of the delay buffer to the comparison position k in order. , The values that remain without being output at the end are output in order. As a result, deterioration from the ideal sort process when retrieving the value in the delay buffer can be suppressed. That is, when the values stored in the delay buffer are not arranged in ascending order from the first buffer, it is possible to prevent the values from being output in the same order.

The configuration shown in the above embodiments is an example, and can be combined with another known technique, can be combined with each other, and does not deviate from the gist. It is also possible to omit or change a part of the configuration.

1 ₁ to ₁₅ delay buffer, 2, 2 ₁ , 2 ₂ butterfly arithmetic circuit, 3, 3 ₁ , 3 ₂ switch circuit, 4 ₁ , 4 ₂ multiplier, 5 ₁ to 5 ₅ comparator, 10 control unit, 100 , 101 Frequency analyzer, 201 processor, 202 memory.

Claims (7)

A frequency analysis device that performs a fast Fourier transform using a butterfly arithmetic circuit and delay buffers provided before and after the butterfly arithmetic circuit, and also performs sorting processing of data obtained by executing the fast Fourier transform.
When the delay buffer is not used in the fast Fourier transform, the delay buffer is used to perform the sorting process.
A frequency analyzer characterized by this. The data stored in the delay buffer is compared with the data before being stored in the delay buffer, and based on the comparison result, a data read process from the delay buffer and a data write process to the delay buffer are included. A comparison unit for controlling the sorting process is provided.
The delay buffer is composed of one or more buffers.
The comparison unit
In the sorting process
Among the data stored in the buffer of the delay buffer, the first data corresponding to the comparison position indicating the position of the buffer in which the data to be compared is stored and the data before being stored in the delay buffer. Compared with the second data which is the head data, if the second data is smaller, the second data is output without being stored in the delay buffer, and if the second data is larger, the second data is output. The data processing of taking out one data, storing the second data in the buffer from which the first data is taken out, and changing the comparison position is repeated as many times as the number of times based on the configuration of the delay buffer.
The frequency analysis apparatus according to claim 1. After repeating the data processing a number of times based on the configuration of the delay buffer,
Each data stored in the delay buffer is output in order from the first buffer constituting the delay buffer.
The frequency analysis apparatus according to claim 2. After repeating the data processing a number of times based on the configuration of the delay buffer,
Each data stored in the delay buffer is output from the delay buffer in the order based on the value of each data.
The frequency analysis apparatus according to claim 2. It is a frequency analysis method executed by a frequency analysis device.
The first step of performing a fast Fourier transform using the butterfly arithmetic circuit and the delay buffers provided before and after the butterfly arithmetic circuit, and
The second step of performing the sorting process of the data obtained by executing the Fast Fourier Transform using the delay buffer at the timing when the delay buffer is not used in the Fast Fourier Transform.
A frequency analysis method comprising. A control circuit that controls a frequency analysis device that performs frequency analysis.
The first step of performing a fast Fourier transform using the butterfly arithmetic circuit and the delay buffers provided before and after the butterfly arithmetic circuit, and
A second step of performing the sorting process of the data obtained by executing the Fast Fourier Transform using the delay buffer at the timing when the delay buffer is not used in the Fast Fourier Transform.
A control circuit, characterized in that the frequency analyzer is executed. A storage medium that stores a program that controls a frequency analysis device that performs frequency analysis.
The program
The first step of performing a fast Fourier transform using the butterfly arithmetic circuit and the delay buffers provided before and after the butterfly arithmetic circuit, and
A second step of performing the sorting process of the data obtained by executing the Fast Fourier Transform using the delay buffer at the timing when the delay buffer is not used in the Fast Fourier Transform.
A storage medium, characterized in that the frequency analyzer is used to execute the above.

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