JPH10283285A - High-speed data transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time for transfer by performing data transfer in dedicated manner through a reader and a writer in place of a central processing unit(CPU). SOLUTION: A reader 23 has a read circuit 25 and a read memory area 24. When the instruction of data transfer is received from a CPU 21, this read circuit performs processing of data transfer in place of the CPU 21 and when the data transfer is completed, the completion is reported to the CPU 21 so that it is enough for the CPU only to output the instruction of data transfer. Besides, a writer 26 has a write circuit 28 and a write memory area 27. When the instruction of data transfer is received from the CPU 21, this write circuit 28 performs the processing of data transfer in place of the CPU 21 and when the data transfer is completed, the completion is reported to the CPU 21 so that it is enough for the CPU 21 only to output the instruction of data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high-speed data transfer on a network.

[0002]

2. Description of the Related Art Conventionally, a computer, a printer, a scanner or the like is connected to a network as shown in FIG. 1 to transfer data from the computer to a device such as a printer.
When data is taken in from a device to a computer, if the central processing unit (CPU) of the computer also performs management and processing other than data transfer, the processing capability of the computer is reduced, and the data transfer speed and other processing are reduced. . Even if a printer server or the like is used, the CPU must perform a process for monitoring the end of the process, which slows down other processes.

[0003]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has as its object to perform high-speed data transfer in a network without involving a CPU in data transfer.

[0004]

SUMMARY OF THE INVENTION The present invention relates to a high-speed data transfer device for transferring data between a computer and a device or a computer on a network at a high speed, comprising: a read device having a read circuit and a read memory area; A writing device having a circuit and a write memory area, wherein the reading device receives the input / output address of the device of the data transfer source, the read circuit checks the usage status of the network and the usage status of the transfer destination device, When data transfer is possible, the data is transferred from the transfer destination device to the read memory area, and when the transfer is completed, the completion of the transfer is notified to the central processing unit, and the writing device receives the input / output address of the device to which the data is transferred. , The write circuit checks the network usage status and the usage status of the transfer destination device When possible data transfer, and transfers the data to the transfer destination device from the write memory area, the transfer and notifies the completion of the transfer when the complete central processing unit, in high-speed data transfer device.

[0005]

Embodiments of the present invention will be described below with reference to the drawings.

<A> Overview of high-speed data transfer device As shown in FIG.
To transfer data from the computer 2 connected to the computer 2 to another device (including a computer) such as the printer 3 or to transfer data from another device such as the scanner 4 to the computer 2 as shown in FIG. , Reading device 23
And a writing device 26 for performing high-speed data transfer between the computer 2 and other devices. The high-speed data transfer device may be provided inside or outside the computer 2.

<B> Reading Device The reading device 23 takes in data from another device on the network 1 to the computer 2, and has a reading circuit 25 and a reading memory area 24.

When receiving a data transfer instruction from the CPU 21, the read circuit 25 performs a data transfer process in place of the CPU 21.
1, the CPU 21 only needs to issue a data transfer instruction, and is released from the data transfer processing.

That is, when receiving the read instruction from the CPU 21, the read circuit 25 reads the memory contents of the specific address in which the input / output address of the transfer source device for transferring data is written, and reads the network 1 and the transfer source device. The transfer status is checked, and if transfer is possible, the data is read from the transfer source device and transferred to the memory area 24.

When the transfer from the transfer source device is completed, the reading circuit 25 notifies the CPU 21 of the completion.

The transfer data stored in the read memory area 24 is transferred by the CPU 21 to the memory 22 of the computer.

<C> Writing Device The writing device 26 transfers data in the memory of the computer 2 to other devices on the network 1 and has a writing circuit 28 and a writing memory area 27.

When receiving a data transfer instruction from the CPU 21, the writing circuit 28 performs a data transfer process in place of the CPU 21.
1, the CPU 21 only needs to issue a data transfer instruction, and is released from the data transfer process.

That is, when the write circuit 28 receives a write instruction from the CPU 21, the write circuit 28 reads the memory contents of the specific address in which the input / output address of the transfer destination device to which the data is transferred is written, and reads the network 1 and the transfer source device. The use status of the device is checked, and if transfer is possible, the data is transferred from the write memory area 27 to the transfer destination device. When the data transfer is completed, the CPU 21 is notified of the completion.

Before issuing a transfer instruction to the write circuit 28, the CPU 21 pre-stores the data in the memory 22 of the computer.
Is transferred to the write memory area 27 in advance.

The data transfer procedure will be described below.

<A> Transfer of Data to Computer An example of transferring data from the computer 2 to a destination device will be described with reference to the flowchart of FIG.

When the read device 23 receives the input / output address of the transfer source device from the CPU 21 (S1), the read circuit 25 monitors the use status of the network 1 and the use status of the transfer source device (S2). If data transfer is possible (S3), the data is read from the transfer source device and the memory area 24 is read.
The data is transferred to (S4). Alternatively, when the use is not possible (S3), the reading circuit 25 monitors the use status again (S2).

The reading circuit 25 determines whether the transfer of all data has been completed (S5), and when completed, interrupts the CPU 21 of the computer to notify the transfer completion (S6). If the transfer of all data is not completed, the process returns to step S2 again, and the above steps are repeated until the transfer of all data is completed.

The CPU 21 transfers the read data to the memory 22 according to the interrupt processing.

By adopting this method, the CPU 21
Is released from the processing for data transfer only.

<B> Transfer of Data from Computer An example of transferring data from the computer 2 to the transfer destination device will be described with reference to the flowchart of FIG.

When the writing device 26 receives the input / output address of the transfer destination from the computer 2 (S11), the writing circuit 28 monitors the usage status of the network 1 and the usage status of the transfer destination device (S12), If transfer is possible (S13), the data is transferred from the write memory area 27 to the transfer destination device (S14). Alternatively, if the data transfer is not possible (S13), the writing circuit 28 monitors the usage status again (S12).

The write circuit 28 determines whether the transfer of all data has been completed (S15), and when completed, notifies the CPU 21 of the computer of the transfer completion by interruption (S16). If the transfer of all data is not completed,
Returning to step S12, the above steps are repeated until the transfer of all data is completed.

By adopting this method, the CPU 21
Is released from the processing for data transfer only.

[0026]

According to the present invention, the following effects can be obtained. <B> Instead of the central processing unit, the reading device and the writing device perform data transfer exclusively,
The transfer time can be shortened. <B> Since the reading device and the writing device operate independently of the CPU, the CPU does not need to monitor the transfer processing and the transfer completion, and the central processing unit can release the data transfer work. The processing device can be effectively used for other processing.

[Brief description of the drawings]

FIG. 1 is a block diagram of a high-speed data transfer device.

FIG. 2 is an explanatory diagram of a network.

FIG. 3 is a flowchart of processing of a reading device.

FIG. 4 is a flowchart of processing of a writing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Network 2 ... Computer 3 ... Printer 4 ... Scanner 21 ... Central processing unit (CPU) 22 ... Computer memory 23 ... Read device 24 ... Read memory area 25 ... Read circuit 26 Write device 27 Write memory area 28 Write circuit

Claims (1)

[Claims] 1. A high-speed data transfer device for transferring data between a computer and a device on a network at high speed, comprising: a read device having a read circuit and a read memory area; and a write device having a write circuit and a write memory area. When the reading device receives the input / output address of the data transfer source device, the reading circuit checks the network usage status and the transfer destination device usage status. The data is transferred from the device to the read memory area, and when the transfer is completed, the completion of the transfer is notified to the central processing unit. Check the status and use status of the transfer destination device, and if data transfer is possible, write memory Transfers the data to the transfer destination device from the band, and notifies the completion of the transfer when the transfer is completed in the central processing unit, a high-speed data transfer device.