JPH10282938A - Display control circuit and picture display device and electronic equipment provided therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display control circuit and a picture display device and an electronic equipment provided therewith, wherein a transfer method of display data is improved and an operation speed and an access speed are accelerated with a low power consumption. SOLUTION: A display control circuit wherein a display data (LDn) is transferred from a system on MPU 10 side and display and control the display data for a display part. This circuit has a RAM 18 in which the display data is written during a 1st period in which the data is required to be accessed to according to a command from MPU 10 and is read during the directly following one frame. This circuit has a driving means 40, 50 comprising display data RAM (100) for reading/writing the read display data. This circuit has a control means 20 to control reading/writing of RAM 18. A control means 20 has a selection means 25 for selecting by changing over either to a 1st mode for always writing the display data in RAM 18 from VRAM in accordance with a request for an access from MPU 10 or to a 2nd mode for transferring the display data to a display data RAM (100) from RAM 18. Thus, a high speed operation becomes possible without restriction to MPU 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control circuit for transferring display data by a microprocessing unit (MPU) and controlling display data on a display unit such as a liquid crystal display unit, and an image display device using the same. Related to electronic equipment.

[0002]

2. Description of the Related Art Conventionally, in this type of liquid crystal display device, display data is transmitted from an MPU side to an LCD module (LCD panel), a scanning electrode driving circuit (Y driver), and a signal electrode driving circuit ( The method of transferring data to an X driver or the like can be roughly classified into a method using a matrix type liquid crystal display element module controller (hereinafter referred to as a module controller) and a method using an X driver with a built-in RAM (read only memory).

In the former method, like a display device using a CRT, a module controller connected to a system bus reads display data from a video RAM (VRAM) storing display data, and sends the read data to an LCD module at a high frequency. The display refresh operation is performed by transferring the clock.

The latter method uses a built-in RAM in an X driver.
(Frame memory), the MPU directly accesses the built-in RAM via the data bus, control bus, or address bus regardless of display timing, transfers one frame of display data to the built-in RAM, and displays the display data in the RAM. , A required control signal is generated in the X driver, display data is sequentially read from the built-in RAM, and a display refresh operation is performed.

[0005] As a modification of the former method, MPU
It is conceivable to have a frame buffer on the MPU side between the driver and the driver. In this case, L
When transferring data to the CD driver, the data is transferred based on the operation clock of the LCD driver.

However, in the display refresh operation, the former method is applied to the VRAM, the latter method is applied to the built-in RAM, and the former method is applied to the frame buffer. , The access from the LCD and the access from the MPU conflict.

This point will be described in detail with reference to FIG.
As shown in (1), when the RAM has one port, the connection of the port on the MPU side and the connection of the port on the LCD side are switched in a time sharing manner using a switch. Here, when the LCD access and the MPU access conflict with each other as in the period T in FIG. 21A, a so-called adjustment that preferentially processes any access is required.

More specifically, for example, in the case of a modification of the former method, as shown in FIG.
Access is performed by using an operating frequency (for example, t1 = 500 ns) set on the MPU side and writing data to the RAM for one line during the period t1. When data is read from the RAM to the LCD and data transfer is performed, the operating frequency (for example, t2 = 66.6 μ) set on the LCD is used.
One line is read using the clock based on s).
After the end of the first MPU access, the LCD access is performed at intervals of the period t3, the data transfer to the LCD is performed in the period t2, and the data transfer process is completed. carry out. This period t
No. 3 is caused by the difference in the operating frequencies.
Further, the case where the MPU has access means a case where scrolling on the display screen or new information is updated.

In the case of such time-division driving, M
After the PU access ends, it takes a considerable amount of time t2 + t3 until the next MPU access is performed. Especially,
When it comes to one field period, the period becomes enormous,
There is a problem that updating is delayed and display processing cannot be speeded up.

In such processing, the MPU processing capacity is restricted, and when the performance of the MPU (higher frequency) is improved, the difference from the LCD operation clock (the above-mentioned time t2 + t3) increases, and the MPU's performance is increased. Processing capacity is reduced. In addition, even if the performance of the MPU is improved, the display performance such as the processing speed does not change, and the performance of the MPU cannot be followed. Furthermore, since the processing time is longer as described above,
There is a problem that power consumption increases.

On the other hand, in any of the above methods, ML
In the S drive or the like, since the display mapping is different from that of the PC, the address space in the VRAM and the address space of the RAM are in different mapping states, and the RAM structure is as shown in FIG.
As shown by 0, if the direction of W / R from the MPU is the same as the direction of R reading to the LCD side, memory cell selection efficiency is poor, it takes time, and power consumption increases.

Further, when the built-in RAM driver is configured as an IC chip, the size of the display panel becomes large and the chip becomes longer in the horizontal direction. However, there is a problem that the operation speed becomes slow. Furthermore, the device must be formed to have a high withstand voltage, and the device structure naturally has a long channel length, so that the device is driven at a high voltage and power consumption is increased.
In addition, unlike a simple LOGICIC, peripheral circuits are also incorporated in the IC, so that the latest memory supporting low voltage cannot be incorporated in the IC, and there is a limit to speeding up.

The present invention has been made to solve the above-mentioned technical problems, and has as its object the following:
It is an object of the present invention to provide a display control circuit, an image display device, and an electronic apparatus including the same, which can improve a transfer method of display data and can achieve high operation speed and high access speed with low power consumption.

[0014]

According to a first aspect of the present invention, there is provided a display control circuit for inputting / outputting display data to / from a microprocessor unit and controlling display of the display data on a display unit. A first storage unit from which the display data from the microprocessor unit is read / written; and the display data read from the first storage unit is written, and the written display data is written by the first storage unit. A second storage unit that is read toward the display unit, a drive unit that performs read / write control of the second storage unit and a display drive control of the display data on the display unit, and a command from the microprocessor unit. Read control of the display data from the microprocessor unit side toward the first storage means based on the first And control means for performing write control on display data of the storage means toward the second storage means, wherein the control means makes an access from the microprocessor unit to the first storage means at a predetermined time. A first mode in which the display data is written to the first storage means during a first period required by the first storage means; and a first mode in which the access is not requested at a predetermined time. And a second mode in which the display data is transferred from the first storage means to the second storage means during a second period in which the display data is read. It has a selection means for switching and selecting.

According to the first aspect of the present invention, in the first period, the control means executes all access requests of the microprocessor unit (hereinafter, referred to as MPU) for updating the display unit and the like. For example, all the display data for one frame is stored in the first storage means. Thereafter, by switching the selection means, all display data written in the first storage means is transferred to the driving means in a second period, for example, one frame period after the first period in which the access request is made. be able to. For this reason, there is no need for a conventional adjustment work for switching the switching for each access request.

Further, unlike the conventional case, for example, when the second storage means is a single input / output port, there is no case where access from the MPU conflicts with access from the LCD.

Furthermore, since the waiting time unlike the conventional case is eliminated, the processing speed is greatly improved, and the power consumption can be greatly reduced. At this time, the reading / writing of the first storage means is performed based on the clock of the MPU, and the clock of the display unit is not used for the transfer to the display unit as in the conventional case. Reducing access delay, MP
High speed processing of U can be ensured. Therefore, the MPU can be used even if the operation speed of the MPU changes as the speed of the MPU increases.

Since the first storage means functioning as a so-called frame buffer is formed independently of the drive means, the configuration of the first storage means is, for example, LOGIC I.
It can be formed only with C. For this reason, it is possible to achieve a higher speed than the second storage means. For example, if the first storage means uses an external RAM for addition, the latest high speed,
A low-voltage memory can be used.
With the generation change of the IC, the IC can be used as the first storage means.

According to a second aspect of the present invention, in the display control circuit according to the first aspect, the second mode of the control means is configured to transfer the output from the microprocessor unit to start transfer of the display data. It is started based on a start command.

According to the second aspect of the present invention, the transfer control means is controlled on the basis of the MPU command, whereby the MPU is controlled.
A corresponding display control circuit can be provided, and data update data transfer can be performed regardless of the operation clock of the display unit.

According to a third aspect of the present invention, in the display control circuit according to the second aspect, the control means includes a flag register for receiving the transfer start instruction, and a flag register for receiving the transfer start instruction. A transfer for outputting an address designating signal for designating an address of the first storage means, setting the selection means to the second mode, reading the display data from the first storage means and transferring the data. And control means.

According to the third aspect of the invention, the transfer control means for controlling the transfer of the display data performs an active operation in response to the transfer start command of the MPU, and sets the selection means to the second.
Mode can be switched. By outputting the address designation signal, the address supplied from the MPU to the first storage means is stopped in the first mode, and the address selection can be easily and quickly performed based on the control of the MPU. Can be.

A display control circuit according to a fourth aspect of the present invention is the display control circuit according to the second or third aspect, wherein:
Having a signal generation means for generating a frame start signal to start the display scan to the display unit for each frame,
The second mode is started based on the transfer start command and the frame start signal.

According to the fourth aspect of the invention, the start of the second mode is performed by a transfer start command of the MPU.
In addition to this, by starting the second mode based on the frame start signal, data can be periodically transferred to the second storage means at least in frame units, and delays such as updating can be prevented. I have. Usually, the amount of data transferred along with the update is the amount of data that can be sufficiently transferred within one frame period.
It is preferable to set a frame.

According to a fifth aspect of the present invention, in the display control circuit according to the fourth aspect, the control unit is configured to perform the transfer when the first mode requires n (n is an integer of 1 or more) frame periods. An interrupt signal output means for generating and outputting an interrupt signal for outputting a start command toward the microprocessor unit is provided.

According to the fifth aspect of the present invention, before switching from the first mode to the second mode, the interrupt signal is output to the MPU.
The MPU that has received this sends a transfer start command to the control means. Upon receiving the command, the control means switches the selection means to the second mode.

As described above, the switching from the first mode to the second mode is performed by using the interrupt signal generated by the clock based on the control signal that is periodically oscillated. Even when the means executes the write control of the first storage means, it is possible to forcibly switch to the data transfer. It is not necessary to use a high-frequency oscillating means for data transfer as a reference clock serving as a reference for this interrupt signal, but a low-frequency oscillating means for generating a frame signal or the like is sufficient.

According to a sixth aspect of the present invention, in the display control circuit according to the fifth aspect, the interrupt signal of the interrupt signal output means is output based on the frame start signal. .

According to the sixth aspect of the present invention, by generating the interrupt signal based on the frame start signal, the display data written in the first storage means in each frame unit can be driven at a suitable timing. The data can be transferred to the second storage means built in the.

Thus, after the MPU access ends, 1
By using the frame period and transferring the display data,
Update of the display screen of the display unit can be displayed without delay.

The present invention according to claims 7 and 8 defines an image display device and an electronic apparatus using the display control circuit according to any one of claims 1 to 6.

In particular, since the third storage means and the first storage means are sequentially designated to the addresses on the respective storage means in the MPU, when viewed from the MPU side, , The first storage means can be easily received as an address in the MPU system, the first storage means functioning as a frame buffer can be controlled based on the address specification of the MPU, and the display control can be completely dependent on the MPU. MPU
There is no reduction in the operating speed of.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments in which the present invention is applied to a liquid crystal display device will be specifically described below with reference to the drawings.

Embodiment 1 (Overall Configuration of System) FIG. 1 shows a liquid crystal display device including a liquid crystal display panel and its display control circuit. The liquid crystal display device of the present embodiment is roughly divided into a microcomputer 1 and a display control circuit 2. The display control circuit 2 includes an external R
AM 18 (first storage unit), control unit (module controller) 20, signal line driver 40 and scanning line driver 50 (drive unit), liquid crystal display panel 60 (display unit), power supply circuit 80, and external oscillation circuit 70 Consisting of The driving means and the liquid crystal display panel may be an LCD module.

Each of the drivers 40 and 50 is configured by arranging one or a plurality of dedicated ICs for driving the MLS of the liquid crystal display panel 60, and is built in an electronic device on which the liquid crystal display panel 60 is mounted. It is used by being connected to the microcomputer 1. This microcomputer 1 is also a semiconductor integrated circuit.

In FIG. 1, a microcomputer 1
Is a programmed 8-bit MPU (Microcompute
r Processing Unit) 10, a data bus 10A to which data is transferred, an address bus 10B to which addresses or control signals are transferred, and a system memory 11 which is a working memory of the MPU 10 and stores program instructions.
And a video RAM (VRA) for storing display data in the same address space as the ROM 14 and the system memory 11.
M) 12, an auxiliary storage device 13 for storing data, voice information, and the like. The system memory 11, VRA
The M12, the auxiliary storage device 13, and the ROM 14 may be combined or any of them may be used as the third storage unit.

The liquid crystal display device of FIG. 1 has a data bus 10A and an address bus 1 in addition to the microcomputer.
0B, a liquid crystal display panel 60 whose display is controlled by the control means 20, a liquid crystal display panel 60,
And a plurality of signal electrodes X1 to X of the liquid crystal display panel 60.
n and a signal line driver 40 for supplying display data to the n. Incidentally, peripheral devices such as a communication control device and other display devices can be connected to the data bus 10A as required.

System memory 11 (third storage means)
Is connected to the data bus 10A connecting the MPU 10 and the display control circuit, and stores a program instruction for operating the MPU 10. When updating the entire display screen such as a scroll operation, the MPU 10 performs the address association process at high speed in order to secure the continuity of addresses. At this time, as shown in FIG. 4B, the address in the internal memory space of the MPU 10 has an address corresponding to the system memory 11 specified in the most significant bit, and the RAM 18 and the built-in RAM 100 (described later) in the middle bit. The corresponding address is specified, and the address corresponding to ROM 14 is specified in the least significant bit.

Further, on the liquid crystal display panel 60, for example, an electromagnetic input touch sensor 16 is provided.
Touch detection can be performed via. This touch detection can be performed with high accuracy during a blank period in which no voltage is applied to the liquid crystal.

Each of the drivers 40 and 50 is formed of one or a plurality of XY, for example, two in accordance with the size of the liquid crystal display panel 60, and controls display driving of display data on a display unit. Display data RAM 100 as means
(Frame buffer). Display data R
The AM 100 reads and writes display data corresponding to at least a part of the read display unit based on the frame signal YD and the like.

The display data LDn is sequentially transferred to the signal line driver 40 by the shift clock XSCL.
This display data is once written into the built-in display data RAM 100. Display data for one or a plurality of scanning lines is simultaneously read from the display data RAM 100 to perform a display operation. For this reason, when there is no display change, the built-in RA can be used without newly transferring display data to the signal line driver 40.
The display refresh can be performed by reading the display data from M, and the power consumption is reduced.

Further, a RAM 18 (SRAM) as first storage means is connected outside the control means 20. Note that the RAM 18 has display data RA due to its configuration.
Normal LOG so that the operation speed is faster than M100
IC It is composed of IC. That is, since it is an external RAM, it is possible to mount the latest RAM with low power consumption and high speed.

The RAM 18 writes the display data in the first period (T _{1 in} FIG. 8) in which the access request is made from the MPU 10 in accordance with the command from the MPU 10, and stores at least one of the frame signals YD generated immediately after the first period. It is read during the second period of the frame (T _{2 in} FIG. 8).

When display data from the MPU 10 is stored in the RAM 18, the control means 20 performs addressing to specify an address to the RAM 18 based on an update command (write start command) from the MPU 10.
When display data from the RAM 18 is stored in the display data RAM 100, the control unit 20 performs data transfer to the display data RAM 100 based on a transfer start command from the MPU 10.

As described above, in this embodiment, the read control to the RAM 18 can be performed depending on the operation of the MPU 10. Further, even if the performance of the MPU 10 is increased, for example, the frequency is increased to increase the operation speed, the liquid crystal display panel 60 can be driven regardless of the performance of the MPU 10 by following the performance without limiting the performance.

Here, the display data RA built in each driver is set.
Since M100 is formed with a high withstand voltage, the operation speed is slightly reduced. However, in this example, the external RAM 18 is used, which has a function as a so-called frame buffer, and the display data RAM 100 itself can be used for distributed calculation or the like for MLS driving. And MPU
When the address space on the memory of the RAM 18 is viewed from the side 10, the address space is incorporated in the address space in the MPU, can be completely dependent on the MPU, and the frame buffer looks completely like an SRAM. Therefore, writing and data transfer can be performed without using a driver clock and without conflict between LCD access and MPU access.

In the RAM 18 of this embodiment, as shown in FIG. 7, the order of selecting memory cells for MPU access (in the direction of W / R) and the order of selecting memory cells for accessing LCD (in the direction of read R). Since the directions are different by 90 degrees, it is convenient when the display mapping is changed in the selection in the MLS drive.

In the MLS drive, in the conventional device shown in FIG. 20, the order selected by MPU access (R / W direction) is the same as the order selected by LCD access (read R direction). . Therefore, in the MLS drive, in FIG. 20, the written memory cells A1, A2, A3,... Need to be selected as A1, B1, C1,. Scan A2, A3,... To select A1, and scan B1, B2, B3,... To select B1, and so on. It took a lot of processing time.

On the other hand, in this embodiment, the R / W direction
Since the direction is different from the direction, A1 shown in FIG.
The memory cells written by B1, C1,...
2, A3,... Can be selected efficiently, and the processing speed can be improved and the power consumption can be reduced.

The liquid crystal display panel 60 is, for example, 320 × 2
For example, a switching element and a liquid crystal are connected in series to form a pixel at a pixel position formed by the intersection of 320 signal lines and 240 scanning lines with 40 pixels. The liquid crystal display panel 60 includes a three-terminal switching element such as a TFT or the like in each liquid crystal layer at a pixel position.
An active matrix type in which two-terminal switching elements such as an IM are connected, or a simple matrix type may be used.

The signal line driver 40 supplies data signals to 320 signal lines, and has first and second signal line drive ICs 42 and 44. The first signal line drive IC 42 supplies data signals to the first to 160th signal lines, and the second signal line drive IC 44 supplies data signals to the 161 to 320th signal lines. Note that a maximum of four signal line drives I
C can be cascaded and can drive up to 640 signal lines.

First and second signal line drive ICs 42 and 4
4 have the same configuration. In order to selectively use up to four signal line drive ICs that can be cascaded in the first to fourth stages, two external terminals LR0 and LR1 are provided for each IC, and the combinations of the applied potentials of the external terminals are made different. ing. The first signal line drive IC 42 in the first stage is
R0 = LR1 = L, second signal line drive I of the second stage
C44 is set so that LR0 = L and LR1 = H. Although not shown in FIG. 1, the third-stage signal line drive IC includes:
LR0 = H, LR1 = L, and the fourth-stage signal line drive IC is set to LR0 = LR1 = H.

The scanning line driver (Y driver) 50
It supplies a scanning signal to 40 scanning lines, and has first and second scanning line drive ICs 52 and 54. The first scan line drive IC 52 supplies a scan signal to the 1st to 120th scan lines, and the second scan line drive IC 54 supplies a scan signal to the 121st to 240th scan lines. In FIG. 1, the scanning line driver 50 and the signal line driver 40 are configured by cascading a plurality of ICs each having the same function, but may be configured as one IC. When a plurality of ICs are cascaded to form one driver, the memory capacity of the display data RAM of each IC is the capacity of the display area handled by one IC, and the signal line drive voltage is one IC. Are the driving voltages for the signal lines in the display area in charge. Power is supplied to the signal line driver 40 and the scanning line driver 50 from the power supply circuit 80, and display data LDn is supplied from the control unit 20.

(Explanation of control means) A write to the externally connected RAM 18 and a built-in RAM
The configuration of the control means that can appropriately switch the data transfer to 100 will be described with reference to FIG. FIG. 2 is a block diagram schematically showing the control means.

The control means 20 has a function of controlling the read / write of the RAM 18 based on a command from the MPU 10, and has a vibrator of about 32 kHz to 512 kHz and constantly oscillates a low frequency clock.
, A scan start signal (frame start signal) YD required for the signal line driver 40, a line latch signal (latch pulse) LP for serial / parallel conversion of transfer display data, and a liquid crystal alternating signal FR based on the low frequency clock. A signal generating means 23 for generating a timing control signal such as the above, a high-frequency oscillating means 22 for generating a high-frequency clock synchronized with the low-frequency clock, an interface circuit 26 for transmitting and receiving information between the MPU 10 and the MPU 10, When display data is changed in a corresponding area of the RAM 100 of the signal line driver 40 in the VRAM 12, a flag register 27 in which a transfer instruction flag is set by the MPU 10 and a high-speed clock X
Outputs the SCL to the dedicated bus, sends the flag address signal and the flag reset signal to the flag register 27,
The display data of the rewrite address in the VRAM 12 is transferred to the bus 1
0A, the display data LDn and the shift clock XSCL obtained by converting the read data into the bit number or format of the data bus using the shift clock XSCL to the signal line driver 40 via the data bus. Transfer control unit 24 (transfer control means)
, Selection means 25, and interrupt signal output means 28.

Upon receiving an access request from the MPU 10, the control means 20 sends the access request from the VRAM 12 to the system bus 10.
Via A, display data for an access request, for example, one frame, is sent to the RAM 18.

The signal generating means 23 has a function of generating various control signals YD and the like based on an update command for updating the display data of the display unit from the MPU 10, and within one frame period based on the low frequency clock. N: a frequency divider for generating 240 latch pulses (line latch signals) LP, a row address signal for counting the latch pulses LP and designating the order (row address) of scan electrodes, a frame start signal YD, etc. , And a frame start signal YD and a count value of the vertical counter.
A frame counter 23 for generating a liquid crystal alternating signal FR
Two. Further, the drive output of the corresponding signal line may be fixed to the voltage level Vc from the signal generation unit 23, and a display control signal for controlling the screen in the display off mode may be output. A predetermined voltage is also supplied to the power supply circuit 80, the signal line driver 40, and the scanning line driver 50.

MP input to interface circuit 26
The update command, transfer start command, and the like from U10 are decoded by a command decoder (command decoding circuit), and the contents and necessary control data are sent to the control unit 24.

The control unit 24 (transfer control means) outputs an address designating signal of the RAM 18 based on control data such as an enable signal, sets and controls the selecting means 25 to the first mode, and based on the transfer start command. Then, display data to be written to the RAM 18 is input, and the display data is read from the RAM 18 and transferred.

The selecting means 25 includes: a first mode in which display data is written from the MPU 10 to the RAM 18 during a _first period (T _{1 in} FIG. 8) in accordance with a command from the MPU in response to an access request from the MPU 10; During the second period (T _{2 in} FIG. 8) after the first period, a function of switching and selecting one of the second mode for transferring display data from the RAM 18 to the display data RAM 100 is provided. . Then, the display data is temporarily written according to the access of the MPU 10, and the data transfer is performed using one frame period after the writing.

The flag register 27 permits the reception of a command of the MPU 10 for starting the second mode immediately before the end of the first mode. Further, it outputs an enable signal based on a write start command from the MPU 10.

The interrupt signal output means 28 outputs the R of the display data.
Immediately before the writing to the AM 18 is completed, an interrupt signal that is output from the MPU 10 and that outputs a transfer start command for starting transfer of display data from the RAM 18 to the display data RAM 100 is output to the MPU 10 based on the control signal. I do. The MPU 10 sends a transfer command when receiving the interrupt. Further, at the time of data transfer, the transfer timing can be finely adjusted using a bus holder as appropriate. For this reason, the MPU 10 can issue a display data transfer start command without being particularly aware of the inside and the outside.

In this embodiment, output control means (not shown) may be provided. When the second mode requires an n-frame period, the output control means determines at least before the end of the two-frame period based on the clock timer of the MPU 10
Terminate the data transfer during the frame period
Control is performed so as to output an update instruction from U10. In this way, in the event that any frame is in a data transfer (second mode) state despite an update command, the output control means causes the MPU to issue an update command, and A write operation can be performed.

Next, the operation of the control means 20 will be described with reference to FIGS.

In the control means 20, the low frequency oscillation means 21
And the signal generating means 43 is always operating, but the high-frequency oscillating means 22 operates intermittently during data transfer. The low-frequency oscillating means 21 always outputs a low-frequency clock, and the frequency divider of the signal generating means 23 divides the low-frequency clock by a predetermined dividing ratio to generate a latch pulse LP. Latch pulse L
P occurs N times in one horizontal period, and is about 32 to 80 kHz. Note that the vertical counter 23-1 outputs the latch pulse L
P is counted, and the row address signal and the frame start signal YD are counted.
Is generated, and the frame counter 23-2 counts the frame start signal YD to generate a liquid crystal alternating signal FR and the like.
The clock XSCL is a high frequency clock.
4 is used for reading and transferring display data. MP
U access is 500 ns, which is an access frequency of 2 MHz.

When the MPU 10 entirely changes the display data of the VRAM 12 during the refresh operation, or when the MPU 10 partially changes the gradation data by the frame thinning method,
An update command (write start command) is input from the MPU 10, and the MPU 10 outputs an address signal and display data to the RA via the data bus 10A and the address bus 10B as needed.
Write to M18. At this time, the selection means 25 is set to the first mode. As a result, display data (update data) of the rewrite address in the VRAM 12 is taken in as read data.

[0067] Then, before the end of the period T ₁ of the Setsu換Ru Figure 8 to the second mode from the first mode, the interrupt signal output means 28 based on the signal YD to periodically output the interrupt signal I
R is output to the MPU 10. MPU1 receiving this
0 sends a transfer start command to the control means 20. In response to the transfer start command, the MPU 10 sets a transfer instruction flag at a corresponding address of the flag register 27 via the interface 26. Further, the control unit 24 has an adder and an offset counter, and has a function of transferring an address and data. When a transfer start command is input, the control unit 24 hits this flag to send an address designation signal of the RAM 18 to the RAM 18. It is output to the selection means 25.

Then, the control unit 20 switches the selection means 25 to the second mode, and reads the display data in the RAM 18 by the high-speed clock by the read address designation signal.
The display data LDn is transferred from the RAM 18 to the driver 40 via the control unit 24.

Here, when an address is generated, MPU 1
The address from 0 is not transmitted, and the data from MPU 10 is not written. At this time, the control unit 24 outputs the shift clock XSCL of the signal generation unit 23 with a high-speed clock. Then, the display data LDn is converted into the number of bits or the format of the data bus, and during one frame period (T _{2 in} FIG. 8), the display data LDn is output and transferred to the dedicated bus based on the high-speed clock XSCL, RAM10
Write to 0. Note that the transfer period may be between two frames.

Here, as shown in FIG.
If the access ends before the rise of YD, the process stands by until the next rise. Further, as shown in FIG. 9B, if data transfer exceeds one frame and MPU access occurs, MPU access has priority and data transfer may be cut off.

In addition, in this example, the second mode is switched from the first mode to the second mode.
Can be switched using a periodically oscillated control signal, for example, an interrupt signal IR generated by a clock based on YD. In this case, even if the control means 20 is executing the write control of the RAM 18, it is possible to forcibly switch to the data transfer.

When one frame period is completed, a flag address signal and a flag reset signal may be sent to the flag register 27 to defeat the transfer instruction flag in the flag address. Then, when the next addressing signal is generated, the above operation is repeated by the high-speed clock, and the display data L for N scanning lines in one frame period.
The transfer of Dn is completed. If one line is selected, L
P1 is 1H (one field period). In the case of simultaneous selection of two lines, LP1 and LP2 are 1H, and in the case of three lines, LP1, LP2 and LP3 are 1H. Inside LP1, 360 XSCLs and LP2s are combined with 360 lines.
Generate 40 shots.

During the transfer of the display data LDn for one frame period, the display operation is temporarily stopped.
Stopping the SCL for one frame period does not affect the display. Nochi, the missing one or two frame screen,
16 ms, which cannot be recognized by human eyes, does not affect the display, and the power consumption can be reduced by eliminating useless screens.

As described above, the control means 20 controls the MPU
At the time of access (when the display data of the VRAM 12 is changed), the display data can be always written to the RAM 18. As a result, the MPU 10 can transfer data to a display data memory for multi-line driving such as the RAM 18 and a control circuit, as well as transfer data to a memory and a register managed by itself which is connected to the internal bus. Since the multi-line driving process is also performed in the same manner as the inside of the MPU, a pipeline-like process is realized, consistency in data transfer timing control is good, and no special load is imposed on the MPU 10.

In the control means of this embodiment, M (not shown)
It is preferable to have an input / output buffer that is directly connected to the PU internal data bus and transmits and receives display data, a bus holder that temporarily stores data, and a command decoder that decodes commands.

(Explanation of Signal Line Driver) A plurality of signal line drive ICs 42 and 44 are semiconductor integrated circuits having the same configuration, and are cascaded to each other via a chip enable output CEO and a chip enable input CEI. None of the signal line drive ICs share the system bus directly connected to the MPU 10 and control means 2 via the data bus.
It only leads to zero.

The first and second signal line drive ICs 4
The specific configurations of the devices 2 and 44 will be described with reference to FIG. FIG. 3 shows a configuration common to the signal line drive IC.

The signal line drive IC 42 is composed of a static RAM for storing display data and its peripheral circuits, for example, a display data RAM 100 having a capacity of 160 segments × 240 lines, and a display data RAM.
LCD control circuit 130 controls read / write of display data in units of 1 byte, for example, reads display data of, for example, four lines from display data RAM 100, and enables MLS driving of simultaneous selection of four lines, column address Control circuit 120, row address control circuit 14
0, the I / O buffer 122 and the latch circuit 132, the multi-line decode circuit 134 and the level shifter 135 for detecting the mismatch between the selected voltage pattern and the display data and determining the applied voltage, and selecting the determined voltage. It has a liquid crystal drive circuit 136 as a voltage selector for outputting, and an internal oscillation circuit 150 for forming a required timing signal and the like based on a signal supplied from the control means 20.

D7 to D0 are connected to the bus line 110 in the IC via the input / output circuit 111 as bus connection terminals. Control data and display data input / output via the input / output circuit 111 can be held in a bus holder (not shown) via the bus line 111. The control data is supplied to the LCD control circuit 130.

The LCD control circuit 130 has external terminals LP,
It is connected to YD, / DOFF, FR, XSCL, CA, / CS and M / S, and is connected to the internal oscillation circuit 150.

The LCD control circuit 130 includes a column address control circuit 120, a row address control circuit 140,
Display data RAM 10 by controlling AM I / O buffer
In addition to functioning as write control means for writing to 0, it also functions as read control means for controlling the driving of the latch circuit 132 and the decode circuit 134 to read display data. That is, when writing, every time the XSCL falls, the display data (1 byte) transferred from the control means 20 is sequentially taken into the I / O buffer 122, and
When reading, display data for 4 lines is stored in RAM10
The data is read from O and supplied to the signal lines of the liquid crystal display panel 60 via the liquid crystal drive circuit 136 to supply a data signal for MLS driving. Also, the LCD control circuit 130 determines the operation timing of the applied voltage, determines the self-refresh mode,
The field of the decoding circuit 134 is also controlled.

The I / O buffer 122 collectively latches the display data LDn for one scan line at the falling edge of the latch pulse LP, and writes the display data LDn to the display data RAM 100 with a write time of one shift clock XSCL or more. The latching order may be defined by, for example, an SHL signal.

Each time the write control signal WR or the read control signal RD is applied, the row address control circuit 140
A row address is output according to the arrangement in 00, a selected address is initialized by a scanning start signal YD, and word lines are sequentially selected based on the row address. The selected address is the display data RA after the falling edge of the LP signal.
It is incremented when data writing to M100 is completed.

The latch circuit 132 converts the display data of the row address selected by the row address control circuit 140 into L
The data is read from the display data RAM 100 at the falling edge of the P signal. The decode circuit 134 stores the display data RAM1
It functions as a signal pulse determining circuit for determining the driving voltage information of the corresponding signal line from the set of the display data and the scanning line column pattern from 00, and outputs a driver control signal necessary for performing the MLS driving. The control signal includes the display data and F
R, / DOFF, and field information provided from the LCD control circuit 320. Further, this circuit converts a signal voltage level from a logic system power supply level (V _DD , V _SS ) to a liquid crystal drive system power supply level (V _{0 to} V ₅ ).
The level shifter 135 is a level interface circuit that performs level conversion for converting a signal of a low logical amplitude level from the decode circuit 134 into a signal of a high logical amplitude level.

The liquid crystal driving circuit 136 includes the decoding circuit 13
4, the voltage V2, V1, Vc (for example, 0), -V1,
-V2 is selected and a liquid crystal application voltage is applied to each of the signal lines X1 to Xn. Which one to select is determined by the display data and the FR signal which is a signal for converting the liquid crystal drive into AC.

The drive IC 42 (44)
8 bit MPU1
0 to the display data RAM 100
As in the data transfer in U10, the data is transferred in 8-bit units (units in which the MPU can process data in parallel).
A data transfer line is constructed between the external MPU 10 and the drive IC 42. At the time of data transfer, the transfer timing can be finely adjusted by using a bus holder as appropriate.

LCD control circuit 1 to which necessary information is given
30 controls the I / O buffer 122, the column and row address control circuits 120 and 140, and controls the I / O buffer 12
2 to the display data RAM 100. In this writing, when the number of simultaneously selected scanning lines is h (h is a natural number of 2 or more), m display data including h display data necessary for determining a voltage to be applied to one data line is used. It is preferable to perform the display data in units of bits.

The LCD control circuit 130 fetches 8-bit (1 byte) control data transmitted via the bus line 110 into a register (not shown) according to a data fetch clock, and based on the control data. , Independently read data from the display data RAM 100. In addition, LC
An operation clock of a logic circuit such as a counter in the D control circuit 130 is supplied from the internal oscillation circuit 150.

Display data necessary for MLS driving is selected and read by an output selection circuit (not shown). The display data is temporarily stored in the latch circuit 132 and then sent to the decode circuit 136. The match of the decode circuit 136
The voltage information determined as a result of the discrepancy determination is transmitted to the liquid crystal driving circuit 136, and a voltage is selected and the liquid crystal display panel 6 is selected.
0 is supplied to the signal line. The description of each terminal described above is shown in Table 1 below.

[0090]

[Table 1] In addition, automatic power save is performed for each driver chip.
Means for controlling data input may be provided so that only the enabled chip captures the display data. In this case, L
Even if all the cascaded drivers are put into the standby state by the input of P and the N drivers are cascaded, only one driver can receive the display data at all times, and the power consumption can be reduced.

When the display content is unchanged, the driver 40 stops the data transfer from the control means 20 to the signal line driver 40, automatically detects this, and sets a self-refresh mode for power-down display. Having. From the end of display data input, shift clock X
SCL is held at L and set, and while XSCL is stopped,
No data is written to the RAM 100. At this time, the driver 40
Receives the signals LP, YD, and FR from the control means 20 and periodically reads out display data from the built-in RAM to refresh the display. The display off function can operate even in the self refresh mode. To release the self-refresh mode, the control means 20 controls the shift clock X from the fall of the signal LP at the time of data transfer.
The SCL is input to the signal line driver 40 and executed. In the cascade connection, the self refresh mode of all the drivers 40 is not released unless the number of XSCL clocks corresponding to the cascade connection is input.

(Description of RAM, Display Data RAM and Peripheral Circuits) In this example, the liquid crystal display panel 60 shown in FIG.
The memory address space of the RAM 100 in one signal line drive IC 42 differs from the display address space of 0 pixel as shown in FIG. In the memory address space of FIG. 6B, the number of memory cells in the row direction is 240 (number) ÷ 8.
(Bits) = 320 in the column direction for 30
(Books) × 8 (bits) ÷ 2 (number of ICs) = 1280. Note that in the memory address space of FIG.
The row address is [0, 1... 29]. In this example, since data is read / written in byte units, the number of column addresses is 1280/8 = 160. still,
The column address of the RAM 100 in the first-stage signal line drive IC 44 is [0, 1,... 159], and the column address of the RAM 100 in the second-stage signal line drive IC 44 is [160,. When a maximum of four signal line drive ICs are cascaded, the maximum column address value is [639].

FIG. 6 is a circuit diagram of the RAM 100 and its peripheral circuits, and includes 30 word lines WL1 to WL30.
Then, the memory cells 102 are respectively connected to the bit line pairs BL and / BL of 1280 columns. The 16 bus lines 110 connected to the RAM I / O buffer 122 in FIG.
128 through each column switch 104 shown in FIG.
It is connected to bit line pair BL, / BL in column 0.

The column address control circuit 120 shown in FIG.
It has 160 column address decoders 120A for simultaneously turning on and off the eight column switches 104 connected to one transfer gate 106 in FIG.
Each column address decoder 120A decodes a 10-bit column address from the LCD control circuit 130 and a 2-bit logic of two external terminals LR0 and LR1,
The eight column switches 104 are turned on and off simultaneously. Each column address decoder 120A is common to each signal drive IC as a mask ROM, and has two external terminals LR.
The set potential of 0, LR1 is changed for each signal drive IC. Therefore, the 1st to 160th column addresses can be decoded by the signal line drive IC 42, and the 161st to 320th column addresses can be decoded by the signal line drive IC 44. Then, when L is output from any one of the column decoders, the eight column switches 104 are simultaneously turned on.

The latch circuit 132 in FIG. 3 has a switch 132A turned on / off by the latch signal SELR and its inverted signal / SELR in FIG. 6, and a latch gate circuit 132B for latching the output. Word line WL1
Becomes active, the latch signal SELR becomes active, and the pixel data of the first to fourth lines are simultaneously latched in the display space of FIG. 5A. Similarly, when the latch inversion signal / SELR is active, The pixel data of the fifth to eighth lines are simultaneously latched. By switching the active word line by the row address control circuit 140, data of the memory cells 102 on all word lines are sequentially latched.

The decoder circuit 134 shown in FIG. 3 includes the PR (signal for precharging the decoding circuit) shown in FIG.
The latch output is decoded based on FR (liquid crystal alternating signal) and F1 and F2 (field signals for distinguishing the MLS pattern). The liquid crystal drive circuit 136 in FIG. 3 determines the signal voltage applied to the signal line from the output of the decoder circuit 134 in FIG. 6 and various voltages.

(Regarding the configuration in which the input / output terminal of the input / output circuit 111 has a high impedance) The 160 column address decoders 120A shown in FIG. 6 each output L when reading / writing data from / to the RAM. Each of the output terminals of the column address decoder 120A is provided with one inverter 108.
Sixty are arranged.

In this example, the column address decoder 120
A monitor circuit 200 monitors whether or not data is read from or written to the RAM 100 based on the output of A. The monitor circuit 200 has 160 N-type transistors 202 to each of which the output of the inverter 108 is applied to the base, and one common connection line 204. When L is output from any one of the column address decoders 120A, one N-type transistor 202 is turned on by the output H of one inverter 108, and the potential of the common connection line 204 becomes L.

The monitor circuit 200 includes the N-type transistor 2
One monitor inverter 206 is provided at the last stage of the common connection line 204 to which the signal line 02 is connected. Therefore, when H is obtained as the output of the monitor circuit 200, the execution of data read / write can be monitored by one of the two signal drivers 22 and 24. The monitor circuit 200 includes a precharge circuit 210 that precharges the potential of the common connection line 204 to H. The precharge circuit 210
It has a transfer gate 212 composed of two P-type transistors 214 and 216. Before reading / writing data, the common connection line 204 is precharged by L of the column control signal CALCTL. At this time,
Since the P-type transistor 216 is also turned on, the monitor output becomes L unless any one of the column decoders 122A becomes L, thereby preventing erroneous detection.

The column address control circuit 120 has a column address decode circuit having 160 column decoders 122A shown in FIG. 6 and a column address counter circuit, and the row address control circuit 140 has a row address decode circuit and a row address decode circuit. LC with address counter circuit
It is preferable that the D control circuit 130 includes a clock control unit that controls each of the column and row address counter circuits. In this case, in the column direction, the column address counter circuit automatically increments each time the RAM is accessed,
In the row direction, the row address counter automatically increments each time the RAM is accessed. Thus, data can be written by accessing the specific area of the storage area of the RAM in the column direction. It should be noted that the row address counter circuit is provided with a third register and a fourth register, and the subsequent stage is provided with cascaded third and fourth bit counters and an address end detector for detecting a row address. preferable.

(Write and Read Operations of Internal RAM) In this example, the latch frequency of the latch circuit is 14.4 KHz,
The time between LCD access requests is 69.4 μS. The signal generation means 23 always generates the frame start pulse YD and the latch pulse LP shown in FIG. The frame start pulse YD is generated every frame period (1F), and the latch pulse LP is generated K times in one horizontal period (1H). In one frame period of YD, the display data LDn for one frame is supplied from the control means 20 to the shift clock XS.
The signal is transferred to the signal line driver 40 by CL. When the transfer of the display data by the YD and the XSCL to the signal line driver 40 is completed, the internal oscillation circuit 150 of the signal line driver 40 generates various read control signals RD, write control signals WR, and the like.

In the driver 40, the display data is taken into the I / O buffer 122 by the latch pulse LP or the like and written into the corresponding row address of the display data RAM 100. If there is no update, the read operation is performed without writing. Also, writing to the display data RAM 100 is 1
At the time of the line 640 dots, the I / O buffer 122 performs the I / O buffer operation at the timing of the one shift clock XSCL of about several hundred ns or at the timing of the latch pulse LP.
It may be possible to write the data for one line at a time from the buffer 122 over a sufficient time (several μs). In the latter case,
This is preferable because the writing speed increases as the display capacity increases.

Thereafter, a data read operation is performed from display data RAM 100, and the read data is stored in latch circuit 132 and sent to decode circuit 134.
Then, the 2-bit information of the mismatch number obtained by the mismatch number determination circuit (not shown) by the generation of the latch pulse LP of the even-numbered line is latched by the latch circuit 132, and one of the signal voltages is selected by the liquid crystal drive circuit, and four sets are selected. Is applied to the liquid crystal matrix.

The control of writing and reading is divided into a writing mode and a reading mode for the same row address within one latch pulse period, and after reading of old data, generation of the next latch pulse causes It is better to write data. In particular, in order to avoid a meaningless display mode that occurs during scrolling, reading may be performed after one frame period. However, when the number of simultaneously selected lines is small, the write operation may be performed after reading the same row address within the period of one latch pulse LP without being necessary until one frame period. Alternatively, one or more readings may be performed after the writing, and the writing of the new data may be performed one frame period after the reading of the old data. Also, the display data LDn in the VRAM 12
The writing and reading operations when the display data of all the other scanning lines are changed except the display data WDk of the k-th scanning line are the display data WD of the k-th scanning line.
The transfer of k may not be newly performed, and the old data in the display data RAM 100 may be read as the display data of the k-th scanning line.

It is to be noted that, for example, when the equal division type n, for example, a four-line simultaneous selection drive system is adopted, the display data R
When the number of column addresses of the AM 100 is equal to the number of signal lines of the panel, and the number of row addresses is equal to the number of scanning lines, it is necessary to read display data for four row lines in the RAM 100 within one horizontal scanning period. Therefore, four latch pulses LP may be generated within one horizontal period.
The number of column addresses of the display data RAM 100 is twice the number of signal lines of the display matrix, and the number of row addresses is half the number of scanning lines (the number of blocks).
When M is used, a latch pulse LP generated once within one horizontal period can be used.

In this case, the address stepping speed of the word line of the RAM 100 in response to the input of the latch pulse LP is faster in reading than in writing.
Reference numeral 40 has a write address generation W counter and a read address generation R counter independently of each other. The output is switched by a multiplexer, and the output of the multiplexer is supplied to an address decoder.

Incidentally, the vertical and horizontal configuration of the display data RAM 100 is such that the number of scanning lines to be simultaneously selected and driven is h, the natural number is n, the number of driver outputs per signal line driver (the number of drivable signal lines) is D, When the number of word lines is W,
(H × 2 ⁿ × D) × W is preferable. This is equal to the maximum number of display dots that can be driven by one signal line driver.

[Embodiment 2] Next, an embodiment of an electronic apparatus using the above-described liquid crystal display device will be described with reference to FIGS.
7 will be described.

An electronic apparatus constructed using the above-described liquid crystal display device includes a display information output source 1000, a display information processing circuit 1002, a display driving circuit 1004, a display panel 1006 such as a liquid crystal panel, a clock generation circuit shown in FIG. 10
08 and a power supply circuit 1010. The display information output source 1000 includes a memory such as a ROM or a RAM, a tuning circuit for tuning and outputting a television signal, and the like, and outputs display information such as a video signal based on a clock from a clock generation circuit 1008. I do. The display information processing circuit 1002 processes and outputs display information based on the clock from the clock generation circuit 1008. The display information processing circuit 1002 can include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. The display driving circuit 1004 includes a scanning side driving circuit and a data side driving circuit, and drives the liquid crystal panel 1006 for display. The data drive circuit in the display drive circuit 1004 includes the above-described signal line drive ICs 22 and 24. The power supply circuit 1010 supplies power to each of the above circuits.

As an electronic device having such a configuration, FIG.
Multimedia compatible personal computer (PC) and engineering workstation (EWS) shown in FIG. 13; a pager shown in FIG. 13; Desktop calculator, car navigation device, POS terminal,
An example of the device includes a touch panel.
A personal computer 1200 illustrated in FIG. 12 includes a main body 1204 having a keyboard 1202 and a liquid crystal display screen 1206.

A pager 1300 shown in FIG. 13 includes a liquid crystal display substrate 1304, a light guide 1306 provided with a backlight 1306a, a circuit board 1308, and first and second shield plates 1310, 13 in a metal frame 1302.
12, two elastic conductors 1314 and 1316, and a film carrier tape 1318. Two elastic conductors 1314 and 1316 and film carrier tape 13
Reference numeral 18 denotes a connection between the liquid crystal display substrate 1304 and the circuit board 1308.

Here, the liquid crystal display substrate 1304 has liquid crystal sealed between two transparent substrates 1304a and 1304b, thereby forming at least a dot matrix type liquid crystal display panel. On one transparent substrate, FIG.
Or a display information processing circuit 1002 in addition to the above. Circuits not mounted on the liquid crystal display substrate 1304 are external circuits of the liquid crystal display substrate, and can be mounted on the circuit substrate 1308 in the case of FIG.

FIG. 13 shows a pager, which is a liquid crystal display substrate 130.
Although a circuit board 1308 is required in addition to 4, a liquid crystal display device is used as a component of the electronic device.
When a display driving circuit or the like is mounted on a transparent substrate, the minimum unit of the liquid crystal display device is the liquid crystal display substrate 1304.
Alternatively, a liquid crystal display substrate 1304 fixed to a metal frame 1302 as a housing can be used as a liquid crystal display device which is one component for electronic devices. Further, in the case of a backlight type, a liquid crystal display substrate 1304 and a light guide 1306 provided with a backlight 1306a can be incorporated in a metal frame 1302 to constitute a liquid crystal display device. Instead, a polyimide tape 132 having a metal conductive film formed on one of two transparent substrates 1304a and 1304b constituting a liquid crystal display substrate 1304 shown in FIG.
2 is a TCP (Tape Carrier Packa) mounting an IC chip 1324 such as a signal line drive IC.
ge) 1320, which can also be used as a liquid crystal display device, which is a component for electronic equipment.

In FIG. 15, a microcomputer is built in mobile phone 1400. This mobile phone 1
Reference numeral 400 denotes an input key 1420 and a liquid crystal display device 1600.
have. The electronic device is, for example, a portable electronic device using a battery (including a solar cell). FIG. 16 shows an outline of the overall configuration of a control circuit of a liquid crystal display device built in such an electronic device.

The microcomputer 1720 shown in FIG.
Are a CPU 1610, an oscillation circuit 1620, a frequency dividing circuit 16
30, an input circuit 1640, a timer 1642, a power supply circuit 1650, a ROM 1670, a RAM 1680, an output circuit 1690, a control circuit 1700, an infrared output controller 1710, and the like. Input circuit 1640 and output circuit 169
Reference numeral 0 denotes a communication interface circuit between the input key 1410 and the like. The control circuit 1700 includes the liquid crystal display device 16
This is a circuit for controlling various states to display various states.
The infrared output controller 1710 is a circuit that turns on and off the infrared light emitting diode D1 via the switching transistor Q100.

The above-mentioned liquid crystal display device can also be used for a personal portable information device (Personal Digital Asistance) 2000, which is one of electronic devices as shown in FIG. The information device 2000 includes an IC card 2100, a simultaneous interpretation system 2200, a handwriting screen 2300,
It has a video conference system 2400a, 2400b, a map information system 2500, and a data creation system 2660, and these images are displayed by the liquid crystal display device of the embodiment. Further, the input / output interface unit 260
0, video camera 2610, speaker 262
0, a microphone 2630, an input pen 2640, and an earphone 2650.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, the present invention is not limited to being applied to the driving of the above-described various liquid crystal panels, but is also applicable to electroluminescence, a plasma display device, a liquid crystal application device using a light valve property of liquid crystal, and the like.

[0118] GPS for navigation systems, etc.
The present invention can be applied to an electronic device such as a (global positioning system) which requires a high operation speed of a CPU for voice recognition and the like and requires low power consumption. Furthermore, one drive I
A configuration in which a plurality of display data RAMs are incorporated in C may be used.
In addition, the drive IC may be provided with a plurality of control means one by one. In this case, as shown in FIG. 18, each of the plurality of control means 20-1.
Even if 1... 18-n are provided, as shown in FIG.
The two RAMs 18 'may be shared. Moreover, these R
The AM is not limited to an external device, and may be configured to be built in the system. 18 and 19, n signal line drive ICs (40-1... 40-n), m scan line drive ICs (50-1... 50-m), and display unit 60
Is formed in an n × m matrix.

Further, the drive IC of this example is connected to the MPU 10
When a read-modify-write command is input, inverted data is read from the bit line / BL from the memory cell, and the inverted data is read from the bit line BL.
, A read-modify-write operation may be performed. With this function, the data in the specific area B can be inverted and only the specific area can be inverted and displayed on the liquid crystal panel without performing data processing in the MPU 10.

Further, the LCD control circuit recognizes a display period and a blank period of each field and controls a row address control circuit and a decode circuit, and a field count signal output from the display control unit. A field counter for counting and an inversion control circuit for controlling the inversion of the polarity of driving the liquid crystal may be provided. in this case,
The data indicating the duty ratio and the length of the blank period are
The data is taken into a register in the display control unit in synchronization with the data taking clock. The display control unit, a display OFF signal to the blank period is supplied to the decoding circuit, fixed forced all signal lines to a reference voltage V _C. At this time, the signal line driver
A control signal for forcibly fixing the scanning line driving voltage is input, and all the scanning lines are also fixed at the reference voltage V _C. During the blank period, no voltage is applied to the liquid crystal. At the end of the field period, the field counter counts the number of outputs.
The display control unit may include first detection means for detecting the end of the display period in each field and second detection means for detecting the end of the blank period. Further, the length of the display period or the blank period may be freely increased or decreased by appropriately changing the value of the register or the data set in the register by the MPU 10. Thus, when the threshold value of the liquid crystal changes depending on the ambient temperature, the liquid crystal applied voltage can be changed so as to match the threshold value, and the display contrast can be controlled.

In the control means 20, when the intermittent operation instruction information is directly received from the MPU 10 or the communication with the MPU 10 and the system bus are monitored, and the display data in the VRAM is updated, the intermittent operation start control is performed. A configuration including a not-shown standby circuit (display data update detection circuit) for generating a signal may be adopted. In this case, the standby circuit
A system bus interface circuit, a line flag register in which a transfer instruction flag is set, a comparison circuit that determines match / mismatch between an address of a scanning line in which the transfer instruction flag is set and a row address and generates a match signal, a match signal and a latch It is preferable to include a synchronization adjustment circuit that generates an intermittent operation start control signal from the pulse LP.

Further, when the display data is unchanged, unnecessary oscillation may not be performed. It can contribute to reduction of power consumption. Further, control means for intermittently operating the high-frequency oscillation circuit may be provided so that display data for each scanning line can be transferred to the display data RAM only when display data of the VRAM is changed.

In addition, the present invention is not limited to the equal-dispersion type n-line simultaneous selection driving method, and can be partially applied to the voltage averaging driving method when a plurality of lines are simultaneously selected. Furthermore, RA
M and the built-in RAM have a part or a plurality of screen cells related to the front and rear of the currently driven pixel among the display panel pixels, even if the pixels of the display panel have cells one-to-one. A method of intermittently sending display data from the control means to the driver or a method of using display data compressed for pixels of the display panel may be used.

[0124]

[Brief description of the drawings]

FIG. 1 is a block diagram including a liquid crystal display device to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a control unit shown in FIG.

FIG. 3 is a block diagram showing a configuration of a signal line driver shown in FIG.

FIG. 4A is a schematic explanatory view showing the configuration of a RAM in a driver, and FIG. 4B is a view from the MPU side;
FIG. 2 is a schematic diagram showing addresses in a memory space.

5A is a schematic explanatory diagram showing a display space address of the liquid crystal display panel of FIG. 1, and FIG. 5B shows a pixel address of a RAM in the signal line drive IC shown in FIG. FIG.

FIG. 6 is a circuit diagram showing a display data RAM and its peripheral circuits shown in FIG. 2;

FIG. 7 is a schematic diagram schematically showing a structure of a RAM shown in FIG. 2;

FIG. 8 is a timing chart for explaining the operation of the circuit in FIG. 2;

FIGS. 9A and 9B are timing charts for explaining the operation of the circuit shown in FIG. 2;

FIG. 10 is a timing chart for explaining the operation of the circuit in FIG. 3;

FIG. 11 is a block diagram of an electronic device to which the present invention is applied.

FIG. 12 is an external view of a personal computer to which the present invention is applied.

FIG. 13 is an exploded perspective view of a pager to which the present invention is applied.

FIG. 14 is a schematic explanatory view showing an example of a liquid crystal display device having an external circuit.

FIG. 15 is a perspective view of a mobile phone to which the present invention is applied.

FIG. 16 is a block diagram of a portable information terminal to which the present invention is applied.

FIG. 17 is a perspective view of a portable information terminal to which the present invention is applied.

FIG. 18 is a block diagram showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 19 is a block diagram showing another embodiment of the liquid crystal display device according to the present invention.

FIG. 20 is a schematic explanatory view schematically showing a conventional RAM.

FIGS. 21A and 21B are timing charts showing timing for transferring display data to a conventional RAM built-in driver, and FIG. 21C is a time-division driving of a conventional RAM port; It is a block diagram for explaining the case where it is used in.

[Explanation of symbols]

 Reference Signs List 10 MPU 11 System memory 12 VRAM 13 Auxiliary storage device 14 ROM 18 RAM (first storage means) 20 Control means 21 Low frequency oscillation means 22 High frequency oscillation means 23 Signal generation means 24 Control unit 25 Selection means 27 Flag register 28 Interrupt Means 40, 50 Driving means 60 Display unit 100 Display data RAM (second storage means)

Claims (8)

[Claims] 1. A display control circuit for inputting / outputting display data to / from a microprocessor unit and controlling display of display data on a display unit, wherein the display data from the microprocessor unit side is read / written. A first storage unit, a second storage unit in which the display data read from the first storage unit is written, and the written display data is read toward the display unit; A drive unit for controlling read / write of the storage unit and display drive control of the display data on the display unit; and transmitting the display data from the microprocessor unit side to the first unit based on a command from the microprocessor unit. Read control towards storage means,
And control means for performing write control on the display data of the first storage means toward the second storage means, wherein the control means makes an access from the microprocessor unit to the first storage means. A first mode in which the display data is written to the first storage means in a first period required at a predetermined time, and a first mode in which the access is not requested at a predetermined time, and During a second period in which the display data in the first storage means is read,
A display control circuit, comprising: a selection unit that switches and selects one of a second mode for transferring the display data from the first storage unit to the second storage unit. 2. The control device according to claim 1, wherein the second mode of the control unit is started based on a transfer start command output from the microprocessor unit to start transfer of the display data. Display control circuit. 3. The control unit according to claim 2, wherein the control unit includes: a flag register that receives the transfer start command; and an address that specifies an address of the first storage unit based on the flag register according to the transfer start command. Display control means for outputting a designation signal, setting the selection means to the second mode, reading the display data from the first storage means, and transferring the data. Control circuit. 4. The signal processing device according to claim 2, wherein the control means has a signal generation means for generating a frame start signal for starting display scanning on the display unit for each frame. A display control circuit, wherein a mode is started based on the transfer start command and the frame start signal. 5. The microcontroller according to claim 4, wherein, when the first mode requires n (n is an integer of 1 or more) frame periods, the control unit outputs the interrupt signal for outputting the transfer start command to the microcontroller. A display control circuit comprising interrupt signal output means for generating and outputting to a processor unit. 6. The display control circuit according to claim 5, wherein the interrupt signal of the interrupt signal output means is output based on the frame start signal. 7. A microprocessor unit, the display control circuit according to claim 1, a display unit driven by the display control circuit, a microprocessor unit, and the display control circuit. A third storage unit connected to a data bus connecting between the first and second storage units and storing a program instruction for operating the microprocessor unit; and the first storage unit in the microprocessor unit. And that a common multi-bit address is specified for the third storage means, and that the address of the third storage means is specified by at least one of the most significant bit or the least significant bit of the address. Characteristic image display device. 8. An electronic apparatus comprising the image display device according to claim 7.