JPH10282527A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of parasitic capacitance between a gate line and a picture element electrode by preventing the gate line selecting the picture element electrode from being protruded on the side of the picture element electrode. SOLUTION: The gate line 12 selecting the row of the picture element electrode 11 is formed along the row of the picture element electrode 11. Also, the picture element electrode 11 within the same row is arranged so as to make an edge part 11b where a notched part 11a is not formed adjacent to the gate line 12 performing selection. Then, a gate projecting part 12A projecting along the notched part 11A of the picture element electrode 11 of a next row is formed at the gate line 12. The gate line 12 where a TFT 16 connected to the picture element electrode 11 is formed is constituted so as not to project on the side of the picture element electrode 11. Thus, an area where the parasitic capacity occurs is reduced, so that the occurrence of flicker due to jump-in voltage caused by the occurrence of the parasitic capacitance is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a thin film transistor (hereinafter, referred to as a TFT) as a switching element.

[0002]

2. Description of the Related Art As a liquid crystal display device, there is an active matrix drive system having a thin film transistor for each pixel. As is well known, in this active matrix driven liquid crystal display device, a common electrode (common electrode) is formed on one of a pair of transparent substrates over the entire display area.
A plurality of pixel electrodes are arranged in a matrix on the other transparent substrate (hereinafter, referred to as TFT substrate) side, and liquid crystal is sealed between the two transparent substrates. In this liquid crystal display device, T
Switching is performed by FT. By applying a voltage between the pixel electrode and the common electrode, the optical characteristics of the liquid crystal corresponding to the pixel portion can be controlled to perform display. On the TFT substrate side, XY such that a gate line and a data line cross each other via an insulating film.
They are formed in a matrix. The TFTs are arranged and connected at the intersections of the gate lines and the data lines. FIG. 6 is a main part plan view showing one pixel electrode 3 surrounded by gate lines 1 and 1 and data lines 2 and 2. FIG. In the TFT indicated by 4 in the figure, a semiconductor layer 5 is formed on a gate electrode 1A protruding from the gate line 1 toward the pixel electrode 3, and data is stored in one of a pair of source / drain regions on the semiconductor layer 5. A drain electrode (or source electrode) 2A protruding from the line is connected, and the other end of a source electrode (or drain electrode) 6 whose one end is connected to the pixel electrode 3 is connected to the other of the source / drain regions on the semiconductor layer 5. Connected and configured. The pixel electrode 3 to which the TFT 4 is connected is provided with the TFT
In order to secure the occupied area of No. 4, a rectangular notch is formed.

[0003]

However, in the above-mentioned liquid crystal display device, a parasitic area is formed in a region indicated by oblique lines in FIG. 7, that is, a region where the gate line (including the gate electrode 1A) 1 and the pixel electrode 3 are adjacent to each other. Generate capacity. This parasitic capacitance is proportional to the length of the region where the gate line 1 and the pixel electrode 3 are adjacent to each other. For this reason, if the length of the gate electrode 1A protruding inside the pixel region increases, the length of the region adjacent to the gate side and the pixel electrode 3 increases, and the parasitic capacitance increases accordingly. This parasitic capacitance is equal to gate line 1
Is generated when the voltage of the first signal changes to the off level, and there is a disadvantage that the so-called jump voltage is increased. When the jump voltage increases, flicker occurs in the liquid crystal display device.

[0006] As shown in FIG. 8, an auxiliary capacitance (C
s) In the case of employing a so-called shield Cs structure in which the gap between the data line 2 and the pixel electrode 3 is shielded from light by using the electrode 7, the above-described protrusion of the gate electrode 1A causes the following inconvenience. . That is, since the auxiliary capacitance electrode 7 and the gate line (including the gate electrode 1A) 1 are formed as a result of simultaneous patterning of the same material film, they must be separated by a predetermined distance so as not to short-circuit. As shown in FIG. 8, the area to be light-shielded by the auxiliary capacitance electrode 7 is reduced. In the Cs shield structure, the width of the auxiliary capacitance electrode is set to be equal to or longer than the misalignment even if there is some misalignment with the black mask formed on the other transparent substrate (common substrate) facing the TFT substrate (not shown). This has the advantage that the aperture ratio of the pixel does not change. However, as described above, this advantage cannot be sufficiently exhibited if the area to be light-shielded by the auxiliary capacitance electrode 7 is small. A structure in which the gate electrode 1A is shifted laterally (along the gate line 1) as shown in FIG.
Such a structure has a disadvantage that the aperture ratio of the pixel is reduced.

[0005] The problem to be solved by the present invention lies in what kind of measures should be taken to obtain a liquid crystal display device capable of suppressing the occurrence of parasitic capacitance between a gate line and a pixel electrode. Another problem to be solved by the present invention is to increase the area in which the gap between the data line and the pixel electrode can be shielded by the auxiliary capacitance electrode,
The point is what kind of measures should be taken to obtain a liquid crystal display device in which the aperture ratio changes little due to the misalignment of the black mask.

[0006]

According to the first aspect of the present invention,
A plurality of gate lines and a plurality of data lines are formed so as to intersect with each other with an insulating film interposed therebetween, and pixel electrodes are respectively arranged in regions divided by the gate lines and the data lines. In a liquid crystal display device in which thin film transistors connected to the corresponding pixel electrodes are arranged in the vicinity of intersections with the data lines, a gate line for selecting the pixel electrodes does not protrude toward the pixel electrodes.

According to the first aspect of the present invention, the area of the region where the pixel electrode and the gate line are adjacent to each other is reduced because the gate of the TFT for switching the pixel electrode does not protrude toward the pixel electrode. . Therefore, the parasitic capacitance between the pixel electrode and the gate line is reduced. In addition, the parasitic capacitance between the gate line and the pixel electrode increases the jump voltage generated when the voltage of the gate line changes to the off level. According to the first aspect of the present invention, the parasitic capacitance is reduced. Thus, the increase in the jump voltage can be suppressed, and the occurrence of flicker can be suppressed.

In the invention according to claim 2, the gate line has a gate projecting portion projecting toward a pixel electrode located on the opposite side of the pixel electrode selected by the gate line with the gate line interposed therebetween. It is characterized by:
According to the second aspect of the present invention, the gate of the TFT for switching the pixel electrode protrudes toward the pixel electrode on which the TFT is not switched, that is, toward the pixel electrode in the next column, and the pixel electrode in the next column is switched. And the parasitic capacitance between the gate line and the gate line increases, and the parasitic capacitance causes a variation in the pixel electrode potential accompanying the variation in the gate pulse. However, since the variation in the potential is minute and very short, The adverse effect on the display quality can be ignored. In addition, the parasitic capacitance between the pixel electrode in the adjacent column and the parasitic capacitance has an effect like an auxiliary capacitance, and conversely, there is an advantage that the jump voltage is reduced. Further, since the gate portion protrudes to the pixel electrode side of the adjacent column, there is an advantage that a TFT formation region can be secured.

According to a third aspect of the present invention, there is provided the above-mentioned pixel electrode,
A storage capacitor electrode is formed along the periphery of the adjacent gate line side where the selection of the pixel electrode is not performed and between the pixel electrodes passing through the data line, and overlaps with the pixel electrode via an insulating film. It is characterized by. According to the third aspect of the present invention, since the auxiliary capacitance can be reduced, the area of the auxiliary capacitance electrode for suppressing the auxiliary capacitance that overlaps with the pixel electrode can be reduced, and the aperture ratio can be increased. Since the aperture ratio has a margin as described above, the width of the auxiliary capacitance electrode formed in this region can be secured in a structure in which the region where the data line passes between the pixel electrodes is optically shielded by the auxiliary capacitance electrode. For this reason, even if the misalignment of the black mask occurs, the problem that the aperture ratio changes because the width of the auxiliary capacitance electrode absorbs the misalignment width can be solved.

According to a fourth aspect of the present invention, the pixel electrode includes:
It is characterized by a delta arrangement.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the liquid crystal display device according to the present invention will be described below with reference to the embodiments shown in the drawings. (Embodiment 1) FIGS. 1 to 4 show Embodiment 1 of a liquid crystal display device according to the present invention. Figure 1 shows the TFT of the display device
FIG. 2 is a plan view showing a relationship between a pixel electrode and a gate line, and FIGS. 3 and 4 are views each showing a structure in which an auxiliary capacitance electrode is formed in the present embodiment. It is a partial plan view. First, in the liquid crystal display device of the present embodiment, a plurality of pixel electrodes made of a transparent ITO having a substantially rectangular shape in which one corner portion is formed with a rectangular cutout portion 11A are formed on a TFT substrate (not shown). 11 are arranged in a matrix. In the present embodiment, the notch 11A is located at the upper left in the figure. A gate line 12 for selecting the column of the pixel electrodes 11 is formed along the column of the pixel electrodes 11 (the horizontal direction in the figure). Note that the pixel electrodes 11 in the same row are arranged such that the edge portion 11B where the notch portion 11 is not formed is adjacent to the gate line 12 for making these selections. The gate line 12 has a gate protrusion 12 protruding downward in the drawing along the notch 11A of the pixel electrode 11 in the next column.
A is formed. That is, one gate line 1
2, the number of the gate protrusions 1 is equal to the number of the pixel electrodes 11 in the column.
2A is formed.

Gate protruding portion 1 in gate line 12
A semiconductor layer 13 made of a-Si is pattern-formed on each region where 2A is formed. The data lines 14 are formed between the rows of the pixel electrodes 11 arranged in the row direction orthogonal to the gate lines 12. The number of the data lines 14 is the same as the number of rows of the pixel electrodes 11. Also, each data line 1
4 is formed on one side of each row of the pixel electrodes 11 (for example, on the left side of the row as shown in the present embodiment). Note that an insulating film (not shown) is interposed between the gate line 12 and the data line 14. In the data line 14, a drain electrode 14A is formed so as to protrude so as to be connected to one of the source / drain regions located on the side of the gate protrusion 12A of each of the semiconductor layers 13 arranged in the vicinity. The other source / drain region in the semiconductor layer 13 has a source electrode 15 connected to the pixel electrode 11 to be switched.
Is provided. The gate line 12, the semiconductor layer 13, the source electrode 15 and the drain electrode 14A form T
The FT 16 is configured. Note that other configurations in the present embodiment are the same as those of a well-known liquid crystal display device, and a description thereof will be omitted.

In the liquid crystal display device having the above configuration,
Parasitic capacitance is generated in a region indicated by oblique lines in FIG. 2, that is, in a region around an edge of the pixel electrode 11 and the gate line 12 where the TFT 16 connected to the pixel electrode 11 is formed. In the present embodiment, the pixel electrode 11
The region where the parasitic capacitance is generated can be minimized because the opposing edges of the gate line 12 and the gate line 12 are parallel to each other. That is, in the present embodiment, since the gate line 12 in which the TFT connected to the pixel electrode 11 is formed does not protrude toward the pixel electrode 11, the region where the parasitic capacitance occurs can be reduced. For this reason, in the liquid crystal display device of the present embodiment, it is possible to suppress the occurrence of flicker caused by the jump voltage due to the occurrence of the parasitic capacitance. The TFT 16 for switching the pixel electrode 11
The gate line 12 protrudes toward the pixel electrode 11 where switching is not performed by the TFT 16, that is, toward the pixel electrode 11 in the next column, and the pixel electrode 11 in the next column and the gate line 12 (the gate protrusion 12A). ), And the potential of the pixel electrode may fluctuate due to the fluctuation of the gate pulse due to the parasitic capacitance. However, since the fluctuation of the potential is minute and very short, The adverse effect on the display quality can be ignored. Further, the parasitic capacitance between the pixel electrode 11 in the next column and the pixel electrode 11 can not only neglect the adverse effect, but also has an effect like an auxiliary capacitance. Further, since the gate protrusion 12A protrudes toward the pixel electrode 11 in the next column, a region for forming the TFT 16 can be secured.

FIG. 3 shows the pixel electrode 11 in this embodiment.
Under the storage capacitor electrode 17 via an insulating film (not shown),
An example in which the center of the pixel electrode 11 is formed along the column direction is shown. FIG. 4 shows the storage capacitor electrode 17 in the present embodiment.
A gate line 1 for selecting a column of adjacent pixel electrodes 11
This is an example formed along line 2. In the present embodiment, since the parasitic capacitance of the rod between the gate line 12 and the pixel electrode 11 can be reduced, the auxiliary capacitance for reducing the jump voltage may be small. Therefore, the auxiliary capacitance electrode 17 and the pixel electrode 1
1 can be reduced, and the aperture ratio of the pixel can be increased.

(Embodiment 2) FIG. 5 is a plan view of a main part of a TFT substrate side showing a liquid crystal display device according to Embodiment 2 of the present invention. In the present embodiment, each pixel electrode 11 is set to R,
It has a structure in which the pixels are arranged in a delta arrangement corresponding to one of the G and B colors, and the space between the pixel electrodes 11 in the column is light-shielded by the auxiliary capacitance electrode 17. In the description of the present embodiment, the same portions as those in the above-described first embodiment will be denoted by the same reference numerals. Further, the configuration of the liquid crystal display device of the present embodiment other than the pixel electrodes, the gate lines, the data lines, and the auxiliary capacitance electrodes is the same as that of the conventional liquid crystal display device, and thus the description thereof is omitted.

Also in this embodiment, the gate line 12
Are formed parallel to the column direction. On the side of each gate line 12, the pixel electrodes 11 are arranged along the gate line 12 so as to form a row formed by repeating R, G, and B as one cycle. The columns of the pixel electrodes 11 adjacent to each other are arranged to be displaced in the column direction by substantially half of one cycle. Pixel electrodes 1 arranged in the column direction
Data lines 14 extending in the row direction are formed between the two. The data line 14 extends in the column direction substantially one third of the pixel width on the gate line 12, extends in the row direction between the pixel electrodes 11 belonging to adjacent columns, and then extends again in the pixel width. It is formed in a so-called zigzag shape that repeats a shape extending back in the column direction by about one-third of the dimension. In addition, the gate line 12
The TFT 16 formed on the gate line 12
The gate protruding portion 12A is formed toward the pixel electrode 11 side of the adjacent column, which is not switched by the above. In addition,
In accordance with the protrusion of the gate protrusion 12A, a rectangular cutout 11A is formed substantially at the center of the edge of the pixel electrode 11 in the pixel region that receives the gate protrusion 12A. A semiconductor layer 13 is pattern-formed on each of the gate lines 12 in the region where the gate protrusion 12A is formed. Further, a drain electrode 14A extending from a data line 14 passing therethrough is provided on one of the source / drain regions of the semiconductor layer 13 located on the side of the gate protrusion 12A with a length substantially equal to a half of the pixel width. They are connected alternately in the row direction. The other source / drain region of the semiconductor layer 13 has a TFT
The source electrode 15 connected to the pixel electrode 11 switched at 16 is connected.

In the above-described configuration on the TFT substrate side, the lower portion of the pixel electrode 11 (the TFT substrate) is overlapped with the edge portion of the pixel electrode 11 forming a column along the gate line 12 on the side where the cutout portion 11A is formed. On the (side), an auxiliary capacitance electrode 17 is formed via an insulating film (not shown). In the present embodiment, the auxiliary capacitance electrode 17 is formed of an electrode material having a light shielding property. Further, as shown in FIG. 5, the auxiliary capacitance electrode 17 has a protruding portion 17A that protrudes so as to overlap a region between the pixel electrodes 11 in the same column. The projecting portion 17A also overlaps the edge portions of the pixel electrodes 11 adjacent to each other in the column.

In the present embodiment, the pixel electrode 11
Since the gate line 12 on which the TFT 16 for switching the pixel electrode 11 is formed is formed so that the edges are parallel to each other without protruding from each other, it is necessary to minimize the parasitic capacitance generated in this region. And the occurrence of flicker can be suppressed. With such a structure in which the generation of the parasitic capacitance is suppressed, the auxiliary capacitance electrode 17 and the pixel electrode 1 for suppressing the generation of the parasitic capacitance are formed.
1 can be reduced, and the aperture ratio of the pixel can be increased. For this reason, a sufficient aperture ratio can be ensured even if the width of the protruding portion 17 has a margin for the pattern shift so that the region between the pixel electrodes 11 in the same column is shielded from light by the auxiliary capacitance electrode 17. it can. Further, since the protrusion can absorb the misalignment of the black mask (not shown) formed on the common substrate (not shown) side, there is an advantage that the change in the aperture ratio can be reduced. Note that, also in the present embodiment, the gate line 12 on which the TFT 16 is formed is connected to the pixel electrode 11 on which the TFT 16 does not perform switching.
That is, a parasitic capacitance is projected between the pixel electrode 11 in the next column and the gate line 12 (including the gate protrusion 12A), and the parasitic capacitance is generated between the pixel electrode 11 in the next column and the gate line 12 (including the gate protrusion 12A). It is conceivable that the potential of the pixel electrode fluctuates due to the fluctuation of the pulse, but since the fluctuation of the potential is very small and very short, the adverse effect on the display image quality can be ignored. Further, the parasitic capacitance between the pixel electrode 11 in the next column and the pixel electrode 11 can not only neglect the adverse effect, but also has an effect like an auxiliary capacitance. Further, since the gate protrusion 12A protrudes toward the pixel electrode 11 in the next column, there is an advantage that a region for forming the TFT 16 can be secured.

Although the first and second embodiments have been described above, the present invention is not limited to these, and various changes accompanying the gist of the configuration are possible. For example, in the first and second embodiments, the gate line 12 is formed with the gate protrusion 12A that is not switched by the TFT 16 formed on the gate line 12 and protrudes toward the pixel electrode 11 in the adjacent column. However, when the formation region of the TFT 16 can be secured, the gate protrusion 12A need not be formed. Further, the gate line 12, the data line 14, the semiconductor layer 13, the source
A material such as a drain electrode can be appropriately adopted.
In the first and second embodiments, the TFT 16 has an inverted staggered structure.
Of course, it is also possible to use a TFT having another structure.
In the first and second embodiments, the drain electrode 14A is provided from the data line 14 to the semiconductor layer 13 and the source electrode 15 is provided on the pixel electrode 11 side. However, the characteristics of the TFT 16, the liquid crystal material, and the driving method are different. The source and drain will need to be changed accordingly. Furthermore, in the first embodiment, the data lines 14 are formed, and the auxiliary capacitance electrodes are extended in the regions between the pixel electrodes 11 so that light shielding between the pixel electrodes arranged in the column direction is performed. Of course, it is good.

[0020]

As is apparent from the above description, according to the present invention, a liquid crystal display device in which the occurrence of a parasitic capacitance between a gate line and a pixel electrode is suppressed and the occurrence of flicker and the like is suppressed is realized. can do. Further, since the generation of the parasitic capacitance is suppressed, the overlapping area of the auxiliary capacitance electrode and the pixel electrode can be reduced, and the aperture ratio of the pixel can be increased. Further, according to the present invention, since the aperture ratio is high, the width of the auxiliary capacitance electrode for shielding the gap between the data line and the pixel electrode can be widened, so that the liquid crystal display with small aperture ratio fluctuation due to misalignment of the black mask. This has the effect of realizing the device.

[Brief description of the drawings]

FIG. 1 is a plan view of a TFT substrate side in a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is an explanatory plan view showing a region where a parasitic capacitance occurs in the first embodiment;

FIG. 3 is a plan view showing an example in which an auxiliary capacitance electrode is formed in the first embodiment.

FIG. 4 is a plan view showing an example in which an auxiliary capacitance electrode is formed in the first embodiment.

FIG. 5 is a plan view of a TFT substrate side in a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a plan view of a main part of a conventional liquid crystal display device on a TFT substrate side.

FIG. 7 is an explanatory view of a main part of a conventional liquid crystal display device.

FIG. 8 is a plan view showing an example in which a storage capacitor electrode is formed in a conventional liquid crystal display device.

FIG. 9 is a plan view showing an example in which a storage capacitor electrode is formed in a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Pixel electrode 11A Notch 12 Gate line 16 TFT 17 Auxiliary capacitance electrode

Claims (4)

[Claims] A plurality of gate lines and a plurality of data lines are formed so as to intersect with each other via an insulating film;
A liquid crystal in which a pixel electrode is arranged in a region divided by a gate line and a data line, and a thin film transistor connected to the pixel electrode corresponding to an intersection between the gate line and the data line is arranged. In a display device, a gate line for selecting the pixel electrode does not protrude toward the pixel electrode. 2. The method according to claim 1, wherein the gate line has a gate protrusion protruding toward a pixel electrode located on a side opposite to the pixel electrode selected by the gate line with the gate line interposed therebetween. Item 2. The liquid crystal display device according to item 1. 3. The pixel electrode is formed along a peripheral portion located on the side of an adjacent gate line on which the selection of the pixel electrode is not performed and between pixel electrodes passing through the data line, and The liquid crystal display device according to claim 1, further comprising an auxiliary capacitance electrode overlapping with an insulating film interposed therebetween. 4. The liquid crystal display device according to claim 1, wherein the pixel electrodes form a delta arrangement.