JP2006013524A - Semiconductor device and manufacturing method for it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device of high display quality by assuring a sufficient retention capacitance (Cs) with a high aperture, while the load on a capacitor wiring (pixel write-in current) is distributed in time, so that it is effectively reduced. <P>SOLUTION: A scanning line 102 is formed at a layer different from a gate electrode 106, and a capacitor wiring 107 is so arranged as to be parallel to a signal line 109. Since each pixel is connected to independent capacitor wiring 107 through a dielectrics, fluctuations in the electric potential of capacitor wiring due to write-in current of adjoining pixel is avoided and satisfactory display image is obtained. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a method for manufacturing the semiconductor device. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic apparatus in which such an electro-optical device is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices. In particular, development of thin film transistors as switching elements for liquid crystal display devices is urgently required.

  In a liquid crystal display device, in order to obtain a high-quality image, an active matrix type liquid crystal display device in which pixel electrodes are arranged in a matrix and a TFT is used as a switching element connected to each pixel electrode has attracted attention.

  In this active matrix liquid crystal display device, in order to display a good quality, it is necessary to hold the potential of the video signal in each pixel electrode connected to the TFT until the next writing. Generally, the potential of the video signal is held by providing a holding capacitor (Cs) in the pixel.

  Various proposals have been made for the structure of the storage capacitor (Cs) and its formation method. From the viewpoint of simplicity of the manufacturing process and reliability, an insulating film having the highest quality among the insulating films constituting the pixel is proposed. It is desirable to use the gate insulating film of the TFT as a dielectric of the storage capacitor (Cs). Conventionally, as shown in FIG. 18, a capacitor wiring serving as an upper electrode is provided using the same wiring layer as the scanning line, and an upper electrode (capacitor wiring) / dielectric layer (gate insulating film) / lower electrode (semiconductor film). Thus, the storage capacitor (Cs) is configured.

  In addition, from the viewpoint of display performance, the pixel is required to have a large storage capacity and to have a high aperture ratio. Since each pixel has a high aperture ratio, the light utilization efficiency of the backlight is improved, and the backlight capacity for obtaining a predetermined display luminance can be suppressed. As a result, power saving and downsizing of the display device can be achieved. Further, since each pixel has a large storage capacity, the display data retention characteristic of each pixel is improved, and the display quality is improved.

Such a requirement is a major issue in the advancement of finer display pixel pitches associated with higher definition (increase in the number of pixels) and downsizing of liquid crystal display devices.

In addition, the conventional pixel configuration described above has a problem that it is difficult to achieve both a high aperture ratio and a large storage capacity.

FIG. 18 shows a conventional example in which a conventional pixel configuration is implemented with a pixel size of 19.2 μm square according to the design rules in Table 1.

  A conventional feature is that two wiring lines (scanning line and capacitive wiring line) are arranged in parallel in order to continuously form two scanning lines and two capacitive wiring lines. In FIG. 18, 10 is a semiconductor film, 11 is a scanning line, 12 is a signal line, 13 is an electrode, and 14 is a capacitor wiring. FIG. 18 is a simplified top view of the pixel, and the pixel electrode connected to the electrode 13 and the contact hole reaching the electrode 13 are not shown.

  When such a storage capacitor configuration with an upper electrode (capacitance wiring) / dielectric layer (gate insulating film) / lower electrode (semiconductor film) is adopted, circuit elements (pixel TFT, storage capacitor, contact hole, etc.) required for the circuit configuration of the pixel ) Are all related to the gate insulating film, and these elements constituting the circuit element are arranged almost planarly in each pixel.

For this reason, in order to obtain both a high aperture ratio and a large storage capacity for each pixel within a specified pixel size, it is essential to efficiently lay out circuit elements necessary for the circuit configuration of the pixel. In other words, it is essential to improve the utilization efficiency of the gate insulating film because all circuit elements are related to the gate insulating film.

  From this point of view, FIG. 19 shows the planar layout efficiency in the circuit configuration of the pixel in the example of FIG. In FIG. 19, 21 indicates a single pixel region, 22 indicates a pixel opening region, 23 indicates a storage capacitor region, 24 indicates an A region, and 25 indicates a part of the TFT and a contact region.

In FIG. 19, the area of the pixel opening region 22 is 216.7 μm ² (aperture ratio 58.8%), the area 64.2 μm ² of the storage capacitor region 23, the area of a part of the TFT and the contact region 25 is 42.2 μm ² , The A region 24 has an area of 34.1 μm ² .

The A region 24 is a wiring region that interconnects the regions serving as the gate electrodes of the TFTs, and a separation region of the scanning line and the capacitive wiring resulting from the parallel arrangement of the scanning line and the capacitive wiring. The gate insulating film in the A region is not given its original function, which causes a reduction in layout efficiency.

Further, in the case of the above structure, there is a problem that the requirement for the capacitance wiring resistance becomes severe.

In normal liquid crystal display driving, the potential of the video signal is applied to each of the plurality of pixels connected to each scanning line continuously (in the case of dot sequential driving) or simultaneously (in the case of line sequential driving) in the scanning line direction. Writing is performed.

In this case, in the above pixel configuration, since the capacitor wiring is arranged in parallel to the scanning line, a plurality of pixels connected to each scanning line are connected to the common capacitor wiring. In this case, the counter current corresponding to the pixel writing current flows continuously or simultaneously for a plurality of pixels, and the capacitance wiring resistance needs to be lowered sufficiently in order to avoid deterioration in display quality due to potential fluctuation of the capacitance wiring. There is.

However, increasing the line width in order to reduce the resistance of the capacitor wiring resistance increases the area occupied by the storage capacitor, while impairing the aperture ratio of the pixel.

The present invention provides a solution from the design side to the above-mentioned problem, ensuring a sufficient holding capacity (Cs) while obtaining a high aperture ratio, and at the same time, loading the capacity wiring (pixel writing current) in terms of time. It is intended to provide a liquid crystal display device having high display quality by dispersing and effectively reducing.

The configuration of the invention disclosed in this specification is as follows.
A first wiring on an insulating surface;
A first insulating film on the first wiring;
A semiconductor film on the first insulating film;
A second insulating film on the semiconductor film;
A second wiring on the second insulating film; a gate electrode connected to the first wiring;
A third insulating film on the second wiring and the gate electrode;
A semiconductor device having a third wiring connected to the semiconductor film on the third insulating film.

  In the above structure, the semiconductor film and the second wiring overlap with each other with the second insulating film interposed therebetween.

In each of the above structures, a storage capacitor having the second insulating film as a dielectric is formed in a region where the second wiring and the semiconductor film overlap with each other through the second insulating film. Yes.

  In each of the above structures, an impurity element that imparts a conductivity type (p-type or n-type) to the semiconductor is added to a region of the semiconductor film that overlaps the second wiring through the second insulating film. It is characterized by having.

  In each of the above structures, an electrode that is in contact with the semiconductor film and a pixel electrode that is connected to the electrode are provided over the third insulating film.

  In each of the above-described configurations, the first wiring is arranged in a direction orthogonal to the second wiring.

  In each of the above-described configurations, the first wiring is arranged in a direction orthogonal to the third wiring. That is, in the pixel portion, the second wiring and the third wiring are arranged in a parallel direction (Y direction), and the first wiring is arranged in a direction orthogonal to these wirings (X direction).

  In each of the above structures, the gate electrode is formed in a different layer from the first wiring.

  In each of the above structures, the gate electrode is patterned in an island shape.

  In each of the above configurations, the first wiring is a scanning line. This scanning line overlaps with a part of the semiconductor film through the first insulating film, and serves as a light shielding film that blocks light to the semiconductor film.

  In each of the above configurations, the second wiring is a capacitor wiring.

  In each of the above configurations, the third wiring is a signal line.

  In each of the above configurations, the second insulating film is a gate insulating film.

In each of the above structures, the gate electrode is mainly composed of an element selected from poly-Si, W, WSi _x , Al, Ta, Cr, or Mo doped with an impurity element imparting conductivity type. It is characterized by comprising a film or a laminated film thereof.

In addition, the configuration of other inventions is as follows:
A plurality of signal lines connected to the signal line driving circuit and arranged in parallel with each other at a predetermined interval;
A plurality of scanning lines connected to the scanning line driving circuit and arranged in parallel with each other at a predetermined interval;
A semiconductor device having a capacitor wiring arranged in parallel with the signal line.

  In the above structure, the scan line is orthogonal to the signal line.

  In the above structure, the semiconductor device includes a thin film transistor having a gate electrode connected to a scanning line orthogonal to the signal line, and a pixel electrode connected to the transistor.

  In each of the above structures, the gate electrode is formed in a layer different from the scanning line.

  In each of the above structures, the gate electrode is patterned in an island shape.

The configuration of the invention for realizing the above structure is as follows.
A first step of forming a first wiring on a substrate having an insulating surface;
A second step of forming a first insulating film on the first wiring;
A third step of forming a semiconductor film on the first wiring;
A fourth step of forming a second insulating film on the semiconductor film;
A fifth step of forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;
A sixth step of forming a gate electrode connected to the first wiring through the first contact hole and overlapping a part of the semiconductor film on the second insulating film;
A seventh step of forming a third insulating film on the gate electrode;
An eighth step of selectively etching the second insulating film and the third insulating film to form a second contact hole reaching the semiconductor film;
And a ninth step of forming a third wiring connected to the semiconductor film through the second contact hole on the third insulating film.

  In the above structure, a second wiring that overlaps with a part of the semiconductor film is formed over the second insulating film by the same process as the gate electrode.

  Further, the above structure is characterized in that, after the step of forming the second insulating film on the semiconductor film, there is a step of partially thinning the second insulating film overlapping the second wiring.

In the above structure, the second insulating film is a gate insulating film, the first wiring is a scanning line, the second wiring is a capacitor wiring, and the third wiring is a signal line.

According to the present invention, an area (corresponding to area A in FIG. 19) that has been conventionally used as a wiring area in a scanning line and a scanning line / capacitor wiring separation area can be used as a storage capacitor. The plurality of pixels connected to each have an independent capacitance wiring, so that each pixel is affected by the write current of the adjacent pixel even when signal writing is performed continuously or simultaneously with the adjacent pixel. Furthermore, since the current load is distributed over time in each capacitor wiring, the effective load is reduced and the requirement for the capacitor wiring resistance is eased.

Therefore, according to the liquid crystal display device using the present invention, a liquid crystal display element having both a high aperture ratio and a storage capacitor that holds a sufficient display signal potential in each pixel can be obtained, thereby reducing the size and power consumption of the device. A good display image can be obtained while achieving this.

  Embodiments of the present invention will be described below.

  The present invention is characterized in that a scanning line is formed in a layer different from the gate electrode in order to improve the aperture ratio and increase the storage capacitor. An example of the pixel configuration of the present invention is shown in FIG.

  In FIG. 1, the gate electrode 106 is patterned in an island shape, and is connected to the scanning line 102 through a contact hole 100c formed in an insulating film. The semiconductor film 104 is connected to the signal line 109 through the contact hole 100a. The semiconductor film 104 is connected to the electrode 110 through the contact hole 100b. A region of the semiconductor film in contact with the signal line 109 or the electrode 110 is called a source region or a drain region. In addition, a channel formation region is formed between the source region and the drain region, and the gate electrode 106 exists on the channel formation region through a gate insulating film. For simplification, the source region, the drain region, and the channel formation region are not shown.

  In the present invention, when the scanning line 102 is formed below the gate electrode 106 as shown in FIG. 1, the scanning line 102 is provided below the semiconductor film 104, so that it can function as a light shielding film. . The storage capacitor is formed such that the lower electrode is a semiconductor film, the insulating film covering the semiconductor film is a dielectric, and the upper electrode is a capacitor wiring 107. Note that the storage capacitor may be increased by partially thinning an insulating film covering the semiconductor film.

  In addition, according to this configuration, the TFT of each pixel can have a dual gate structure including a gate electrode via an insulating film above and below the channel formation region, and the first insulating film has an appropriate film thickness. By setting to, the TFT characteristics can be improved while suppressing the parasitic capacitance formed by the scanning lines and other wirings.

  Further, the present invention is characterized in that, unlike the conventional case (capacitive wiring is parallel to the scanning line), the capacitive wiring is arranged in parallel to the signal line. Accordingly, video signals are continuously written to the pixels corresponding to the respective scanning lines from the driving method, but at this time, the corresponding pixels are connected to the holding capacitors formed by the independent capacitance wirings. Variations in the capacitance wiring potential due to the write current of adjacent pixels can be avoided, and a good display image can be obtained.

  Conventionally, each signal line is provided with a sample hold capacitor in order to prevent a decrease in signal line potential (write potential) during each scanning line writing period. However, in the present invention, the capacitor wiring is parallel to the signal line. In addition, since the parasitic capacitance of the signal line is increased and the signal line potential retention characteristics are improved, it is not necessary to provide a sample hold capacitor in the peripheral circuit portion, and the peripheral circuit is smaller than the conventional one. Can be

  Also, for the same reason, the required performance on the capacitance wiring resistance is eased, so the design flexibility of the layout, size, and film thickness of the capacitance wiring increases, and the range of selection of the capacitance wiring material increases, and the design difficulty and Manufacturing difficulty is reduced, leading to higher manufacturing yield.

  The present invention having the above-described configuration will be described in more detail with the following examples.

Hereinafter, an embodiment of the present invention will be described by taking a projection type dot sequential liquid crystal display device as an example.

  An active matrix liquid crystal display device using a TFT as a switching element has a structure in which a substrate (TFT substrate) in which pixel electrodes are arranged in a matrix and a counter substrate on which a counter electrode is formed are arranged to face each other through a liquid crystal layer. It has become. The distance between the two substrates is controlled to a predetermined interval via a spacer or the like, and a liquid crystal layer is sealed by using a sealing material on the outer periphery of the pixel portion.

  FIG. 4 is a cross-sectional structure diagram showing an outline of the liquid crystal display device of this embodiment. In FIG. 4, 101 is a substrate (TFT substrate), 102 is a scanning line, 103 is a first insulating film, 104 is a semiconductor film, 105 is a gate insulating film (second insulating film), 106 is a gate electrode, and 107 is a capacitor wiring. , 108 are third insulating films, 109 and 111 are signal lines or electrodes branched from the signal lines, 110 is connected to the semiconductor film through a contact hole (not shown) formed in the third insulating film, and TFTs and pixels It is an electrode for connecting an electrode.

  Note that in this specification, an “electrode” is a part of “wiring” and refers to a portion where electrical connection with another wiring is made or a portion intersecting with a semiconductor layer. Therefore, for convenience of explanation, “wiring” and “electrode” are used properly, but “wiring” is always included in the term “electrode”.

  In this specification, the TFT is defined as a portion indicated by 101 to 110. Further, in 109 and 110, an electrode branched from the wiring or a wiring may be used.

  Reference numeral 112 denotes a fourth insulating film covering the TFT, 113 denotes a light shielding film for preventing light degradation of the TFT, 114 denotes a fifth insulating film, 115 denotes a pixel electrode connected to the electrode 110 through the contact hole 100d, and 116 denotes a liquid crystal layer. This is an alignment film for aligning 117.

  In FIG. 4, the counter electrode 119 and the alignment film 118 are provided on the counter substrate 120, but a light shielding film and a color filter may be provided as necessary.

  As shown in FIG. 2, the substrate (TFT substrate) 101 includes a pixel portion 201, a scanning line driving circuit 202 and a signal line driving circuit 203 formed around the pixel portion 201.

  The scanning line driving circuit 202 is mainly configured by a shift register that sequentially transfers scanning signals. The signal line driver circuit 203 is mainly composed of a shift register and a sample hold circuit that samples and holds a video signal input based on the shift register output and drives the signal line.

  A plurality of scanning lines (gate wirings) 207 connected to the scanning line driving circuit 202 and arranged in parallel with each other at a predetermined interval and a signal line driving circuit 203 connected to the pixel portion 201 in parallel with each other at a predetermined interval. The plurality of signal lines 208 are arranged so as to intersect with each other, and a TFT (not shown) is disposed at each of the intersecting positions, and a pixel electrode (in each area partitioned by the scanning lines and the signal lines). (Not shown) is arranged. With this configuration, the pixel electrodes are arranged in a matrix. A plurality of capacitor wirings 209 connected to GND (ground) or a fixed potential 206 are provided in parallel with the signal line 208. In FIG. 2, only a few signal lines, scanning lines, and capacitor wirings are shown for simplification.

  Hereinafter, a manufacturing process of the semiconductor device illustrated in FIGS. In addition, FIG.3 and FIG.1 is also used for description.

  First, a quartz substrate or a plastic substrate can be used for the substrate 101 in addition to a glass substrate. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. In order to prevent impurity diffusion from the substrate 101, a base film made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is preferably formed on the surface of the substrate 101 where the TFT is formed.

Next, a conductive film is formed over the substrate, and patterning is performed to form the scanning line 102. As the scanning line 102, a conductive material such as poly-Si or WSi _x (X = 2.0 to 2.8) doped with an impurity element imparting a conductivity type, Al, Ta, W, Cr, or Mo, and Such a stacked structure can be used. In this embodiment, the scanning lines 102 are formed at predetermined intervals by a conductive material having a high light-shielding property having a laminated structure of WSi _x (film thickness: 100 nm) / poly-Si (film thickness: 50 nm).

  Next, a first insulating film 103 having a thickness of about 500 nm is formed so as to cover the scanning line 102. As the first insulating film 103, an insulating film containing silicon formed by a plasma CVD method, a sputtering method, or the like is used. In addition, the first insulating film may be formed of an organic insulating material film, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a laminated film combining these.

  Next, a semiconductor film having a thickness of 25 to 80 nm (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method, and is patterned into a desired shape. In this embodiment, an amorphous silicon film is formed to a thickness of about 50 nm by a plasma CVD method, and after performing a crystallization step by a known method to form a crystalline silicon film (poly-Si), Patterning was performed in an island shape. In this embodiment, a crystalline silicon film (poly-Si) is used, but there is no particular limitation as long as it is a semiconductor film.

Note that in this specification, a “semiconductor film” refers to a single crystal semiconductor film, a crystalline semiconductor film (such as poly-Si), an amorphous semiconductor film (such as a-Si), or a microcrystalline semiconductor film. In addition, a compound semiconductor film such as a silicon germanium film is also included.

  Next, the second insulating film (gate insulating film) 105 is formed using an insulating film containing silicon formed by plasma CVD, sputtering, or the like, or an oxide film formed by thermal oxidation of a semiconductor film (Si film or the like). Form. The second insulating film 105 may have a laminated structure including a plurality of layers such as two layers or three layers as necessary.

  Next, in order to form a TFT that obtains the function of a video signal writing switch using each island-shaped semiconductor film, an impurity element (phosphorus or boron or the like) that selectively imparts n-type or p-type to the semiconductor film is known. Addition is performed using a technique to form a low resistance source region and drain region, and further a low resistance region. This low resistance region is a part of the semiconductor film which has been reduced in resistance by adding an impurity element (typically phosphorus or boron) in the same manner as the drain region. Note that the order of steps in which the impurity element is selectively added is not particularly limited, and may be, for example, before the first insulating film is formed, before the gate electrode is formed, or after the gate electrode is formed. In addition, the LDD region and the offset region may be formed according to the circuit. For simplification, each region is not shown.

  Thus, a channel formation region sandwiched between the source region and the drain region is formed in the semiconductor film 104.

  Next, the first insulating film 103 and the second insulating film 105 are selectively etched to form a first contact hole 100c (shown in FIG. 3B) reaching the scanning line 102.

Next, a conductive film is formed over the second insulating film 105 and patterned to form the gate electrode 106 and the capacitor wiring 107. The gate electrode 106 and the capacitor wiring 107 are conductive such as poly-Si doped with an impurity element imparting a conductivity type, WSi _x (X = 2.0 to 2.8), Al, Ta, W, Cr, and Mo. The film is formed with a film thickness of about 300 nm by the conductive material and its laminated structure. The gate electrode 106 and the capacitor wiring 107 may be formed as a single layer, but may have a stacked structure including a plurality of layers such as two layers or three layers as necessary. At this time, each gate electrode arranged in an island shape is electrically connected to the scanning line 102 through the first contact hole 100 c formed in the first insulating film 103 and the second insulating film 105.

  An island-shaped gate electrode 106 is disposed on the channel formation region of each pixel with the second insulating film 105 interposed therebetween. In addition, a capacitor wiring 107 is disposed on the low resistance region via the second insulating film 105. Note that the storage capacitor may be increased by adding a step of partially thinning a region of the second insulating film 105 overlapping with the capacitor wiring 107. In addition, the capacitor wiring 107 is continuously arranged in the signal line direction for each pixel, and is electrically grounded or connected to a fixed potential outside the pixel portion.

Next, a third insulating film 108 that covers the gate electrode 106 and the capacitor wiring 107 is formed. As the third insulating film 108, an insulating film containing silicon formed by plasma CVD, sputtering, or the like is used. In addition, the third insulating film 108 may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film in which these are combined.

  Next, the second insulating film 105 and the third insulating film 108 are selectively etched to form second contact holes 100a (in FIG. 3A) and 100b (see FIG. 3A) reaching the semiconductor film (source region or drain region). 3 (b)).

Next, a film containing Al, W, Ti, TiN as a main component or a conductive film (thickness: 500 μm) having a laminated structure thereof is formed on the third insulating film 108 and patterned to perform signal line 109. 111, and an island-shaped electrode 110 for connecting to a pixel electrode to be formed later. The signal lines 109 and 111 are connected to the source region or the drain region through the second contact holes 100a and 100b reaching the semiconductor film. Similarly, the island-shaped electrode 110 is connected to the source region or the drain region through the second contact hole 100a reaching the semiconductor film. The signal lines 109 and 111 are arranged in a direction parallel to the capacitor line 107.

  Further, the island-shaped electrode 110 is disposed separately from the signal line 109. However, both the signal line 109 and the island-shaped electrode 110 are not connected to the source region. Similarly, neither the signal line 109 nor the island-shaped electrode 110 is connected to the drain region.

  A top view of the pixel at this stage corresponds to FIG. 1, and a schematic sectional view taken along the dotted line AA ′ in FIG. 1 corresponds to FIG. 3A, along the dotted line BB ′. The cut schematic sectional structure diagram corresponds to FIG.

  Next, a fourth insulating film 112 that covers the signal line 109 and the island-shaped electrode 110 is formed. The fourth insulating film 112 may be formed of an organic insulating material film, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a laminated film combining these.

Next, a light shielding film 113 is formed on the fourth insulating film 112 by patterning a film having high light shielding properties such as Ti, Al, W, Cr, or black resin into a desired shape. The light shielding film 113 is arranged in a mesh shape so as to shield light other than the opening of the pixel.

In this embodiment, the light shielding film 113 is electrically floating, but when a low resistance film is selected as the light shielding film material, the light shielding film can be controlled to an arbitrary potential outside the display portion.

Next, a fifth insulating film 114 is formed over the light shielding film 113. The fifth insulating film 114 may be formed of an organic insulating material film. Note that the surface can be satisfactorily planarized by forming the fifth insulating film 114 of an organic insulating material. In addition, since the organic resin material generally has a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and is not suitable as a protective film, a stacked structure combined with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like may be used.

Next, the fourth insulating film 112 and the fifth insulating film 114 are selectively etched to form a third contact hole 100d that reaches the island-shaped electrode. In FIG. 4, for convenience, the third contact hole 100d is illustrated by a dotted line.

  Next, a transparent conductive film such as ITO is formed and patterned to form the pixel electrode 115. The pixel electrode 115 is connected to the island-shaped electrode 110 through the third contact hole 100d. Each pixel electrode is independently arranged so as to cover the pixel opening.

  An alignment film 116 for aligning the liquid crystal layer 117 is formed on the TFT substrate thus formed, and is bonded to the counter substrate 120 provided with the counter electrode 119 and the alignment film 118 by using a known cell assembling technique, and then the liquid crystal. The material was injected and sealed to complete a liquid crystal cell in which a liquid crystal layer was held between both substrates.

By using the manufacturing process as described above and further arranging the wiring, the semiconductor film, and the like according to the design rules in Table 2, the area of the pixel opening area of 236.9 μm ² (opening ratio of 64.3%) and the storage capacitor area An area of 62.8 μm ² was obtained.

  In this embodiment, it is necessary to newly provide a region for the contact hole 100c for connecting the gate electrode 106 and the scanning line 102 to the pixel region. Further, in this embodiment, since the film that shields the periphery of the channel formation region of the island-like Si film is only the upper light shielding film, it is desirable to have a structure including the upper light shielding film.

Further, according to this configuration, since the scanning line 102 functions as a lower light-shielding film for the channel formation region and its peripheral part, the light incident from the liquid crystal layer 117 is reflected at the lower interface of the TFT substrate, and the channel formation region and its peripheral part It is possible to prevent the occurrence of light leakage of the TFT by being incident on the TFT, and better display quality can be obtained.

  In this embodiment, the structure of the active matrix liquid crystal display device shown in Embodiment 1 will be described with reference to the perspective view of FIG. In addition, the same code | symbol is used for the part corresponding to Example 1. FIG.

In FIG. 5, the active matrix substrate includes a pixel portion, a scanning line driver circuit 802, a signal line driver circuit 803, and other signal processing circuits formed over the substrate 101. A pixel TFT 800 and a storage capacitor 200 are provided in the pixel portion, and a driving circuit provided around the pixel portion is configured based on a CMOS circuit.

Further, the capacitor wiring 107 is provided in a direction parallel to the signal line 109 and functions as an upper electrode of the storage capacitor 200. The capacitor wiring 107 is connected to ground or a fixed potential.

  From the scanning line driver circuit 802 and the signal line driver circuit 803, the scanning line 102 and the signal line 109 extend to the pixel portion and are connected to the pixel TFT 800, respectively. A flexible printed circuit (FPC) 804 is connected to an external input terminal 805 and used to input image signals and the like. The FPC 804 is firmly bonded with a reinforcing resin. Connection wirings 806 and 807 are connected to the respective drive circuits. Further, although not shown in the figure, the counter substrate 808 is provided with a light shielding film and a transparent electrode.

  The pixel matrix circuit formed by implementing the present invention can be used in various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC display). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display units.

  Such electronic devices include video cameras, digital cameras, projectors (rear or front type), head mounted displays (goggles type displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones or e-books) Etc.). Examples of these are shown in FIGS.

  FIG. 6A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display portion 2003, and a keyboard 2004. The present invention can be applied to the display portion 2003.

  FIG. 6B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display portion 2102.

  FIG. 6C illustrates a mobile computer (mobile computer), which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display portion 2205.

  FIG. 6D illustrates a goggle type display which includes a main body 2301, a display portion 2302, and an arm portion 2303. The present invention can be applied to the display portion 2302.

  FIG. 6E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 2401, a display portion 2402, a speaker portion 2403, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 6F illustrates a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, an operation switch 2504, and an image receiving portion (not shown). The present invention can be applied to the display portion 2502.

  FIG. 7A illustrates a front projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to a liquid crystal display device 2808 that constitutes a part of the projection device 2601.

  FIG. 7B shows a rear projector, which includes a main body 2701, a projection device 2702, a mirror 2703, a screen 2704, and the like. The present invention can be applied to a liquid crystal display device 2808 that constitutes a part of the projection device 2702.

  FIG. 7C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 7A and 7B. The projection devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a prism 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. Projection optical system 2810 includes an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

  FIG. 7D shows an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system illustrated in FIG. 7D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. In addition, the electronic apparatus of the present embodiment can be realized by using a configuration including any combination of the first and second embodiments.

  Although Example 1 shows an example of a single gate TFT, this example shows an example using a double gate TFT. However, the basic structure is the same.

  First, a conductive film is formed over the substrate 401 having an insulating surface, and the scanning lines 402 are formed by patterning. (FIG. 8A) This scanning line 402 also functions as a light shielding layer for protecting an active layer formed later from light. Here, a quartz substrate is used as the substrate 401, and a stacked structure of a polysilicon film (film thickness of 50 nm) and a tungsten silicide (W-Si) film (film thickness of 100 nm) is used as the scanning line 402. The polysilicon film protects the contamination from the tungsten silicide to the substrate.

  Next, insulating films 403a and 403b that cover the scanning lines 402 are formed to a thickness of 100 to 1000 nm (typically 300 to 500 nm). Here, a silicon oxide film having a thickness of 100 nm using the CVD method and a silicon oxide film having a thickness of 280 nm using the LPCVD method were stacked.

  Next, an amorphous semiconductor film is formed with a thickness of 10 to 100 nm. Here, an amorphous silicon film (amorphous silicon film) having a thickness of 69 nm is formed by LPCVD. Next, the amorphous semiconductor film was crystallized using the technique described in Japanese Patent Laid-Open No. 8-78329 as a technique for crystallizing the amorphous semiconductor film. The technique described in this publication is to selectively add a metal element that promotes crystallization to an amorphous silicon film and perform a heat treatment to form a crystalline silicon film that spreads from the added region as a starting point. is there. Here, nickel was used as a metal element for promoting crystallization, and after heat treatment for dehydrogenation (450 ° C., 1 hour), heat treatment for crystallization (600 ° C., 12 hours) was performed.

  Next, Ni is gettered from the region used as the active layer of the TFT. A region to be an active layer of the TFT was covered with a mask (silicon oxide film), phosphorus (P) was added to part of the crystalline silicon film, and heat treatment (600 ° C., 12 hours in a nitrogen atmosphere) was performed.

  Next, after removing the mask, patterning is performed to remove unnecessary portions of the crystalline silicon film, so that the semiconductor layer 404 is formed. Note that FIG. 8C2 is a top view of the pixel after the semiconductor layer 404 is formed. In FIG. 8C2, a cross-sectional view taken along dotted line A-A ′ corresponds to FIG.

  Next, in order to form a storage capacitor, a mask 405 is formed, and a part of the semiconductor layer (a region to be a storage capacitor) 406 is doped with phosphorus. (Fig. 9 (A))

  Next, after removing the mask 405 and forming an insulating film covering the semiconductor layer, the insulating film over the region 406 serving as a storage capacitor is formed by forming the mask 407. (Fig. 9 (B))

  Next, the mask 407 is removed, and thermal oxidation is performed to form an insulating film (gate insulating film) 408a. By this thermal oxidation, the final gate insulating film thickness was 80 nm. Note that an insulating film 408b thinner than other regions was formed over the region serving as the storage capacitor. (FIG. 9C1) A top view of the pixel here is shown in FIG. 9C2. In FIG. 9C2, a cross-sectional view taken along dotted line B-B ′ corresponds to FIG. 9C1. In addition, a region indicated by a chain line in FIG. 9 is a portion where a thin insulating film 408b is formed.

Next, a channel doping process for adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the TFT was performed over the entire surface or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, boron was added by an ion doping method in which diborane (B ₂ H ₆ ) was plasma-excited without mass separation. Of course, an ion implantation method that performs mass separation may be used.

  Next, a mask 409 is formed over the insulating film 408a and the insulating films 403a and 403b, and a contact hole reaching the scanning line 402 is formed. (FIG. 10A) Then, after the contact hole is formed, the mask is removed.

  Next, a conductive film is formed and patterned to form the gate electrode 410 and the capacitor wiring 411. Here, a stacked structure of a phosphorus-doped silicon film (thickness 150 nm) and tungsten silicide (thickness 150 nm) was used. Note that the storage capacitor includes a capacitor wiring 411 and a part 406 of the semiconductor layer, with the insulating film 408b as a dielectric.

Next, phosphorus is added at a low concentration in a self-aligning manner using the gate electrode 410 and the capacitor wiring 411 as a mask. (FIG. 10C1) A top view of the pixel here is shown in FIG. 10C2. In FIG. 10C2, a cross-sectional view taken along dotted line CC ′ corresponds to FIG. The concentration of phosphorus in this low concentration region is adjusted so as to be 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ , typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / cm ^3. To do.

Next, a mask 412 is formed, phosphorus is added at a high concentration, and a high concentration impurity region 413 to be a source region or a drain region is formed. (FIG. 11A) The phosphorus concentration in this high concentration impurity region is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²⁰ atoms / cm ³ ). Adjust so that Note that in the semiconductor layer 404, a region overlapping with the gate electrode 410 becomes a channel formation region 414, and a region covered with the mask 412 becomes a low-concentration impurity region 415 and functions as an LDD region. Then, after the impurity element is added, the mask 412 is removed.

  Next, although not shown here, in order to form a p-channel TFT used for a driver circuit formed over the same substrate as the pixel, a region that becomes an n-channel TFT is covered with a mask, and boron is added to form a source region. Alternatively, a drain region is formed.

  Next, after the mask 412 is removed, a passivation film 416 that covers the gate electrode 410 and the capacitor wiring 411 is formed. Here, a silicon oxide film was formed with a thickness of 70 nm. Next, a heat treatment step for activating the n-type or p-type impurity element added to the semiconductor layer at each concentration is performed. Here, heat treatment was performed at 850 ° C. for 30 minutes.

  Next, an interlayer insulating film 417 made of an organic resin material is formed. Here, an acrylic resin film having a thickness of 400 nm was used. Next, after a contact hole reaching the semiconductor layer is formed, an electrode 418 and a source wiring 419 are formed. In this embodiment, the electrode 418 and the source wiring 419 are each a laminated film having a three-layer structure in which a Ti film is formed with a thickness of 100 nm, an aluminum film containing Ti is formed with a thickness of 300 nm, and a Ti film is formed with a thickness of 150 nm. (FIG. 11B1) Note that a cross-sectional view taken along dotted line D-D ′ in FIG. 11B2 corresponds to FIG.

  Next, after performing a hydrogenation process, an interlayer insulating film 420 made of acrylic is formed. (FIG. 12A1) Next, a light-shielding conductive film 100 nm is formed over the interlayer insulating film 420 to form a light-shielding layer 421. Next, an interlayer insulating film 422 is formed. Next, a contact hole reaching the electrode 418 is formed. Next, after forming a 100 nm transparent conductive film (here, indium tin oxide (ITO) film), patterning is performed to form pixel electrodes 423 and 424. In FIG. 12A2, a cross-sectional view taken along dotted line E-E ′ corresponds to FIG.

  Thus, in the pixel portion, a pixel TFT composed of an n-channel TFT is formed while ensuring an area (aperture ratio 76.5%) of a display region (pixel size 26 μm × 26 μm), and a sufficient storage capacitor (51.5 fF) is formed. ) Can be obtained.

  Needless to say, the present embodiment is an example and is not limited to the steps of the present embodiment. For example, as each conductive film, an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), or an alloy in which the elements are combined A film (typically, a Mo—W alloy or a Mo—Ta alloy) can be used. As each insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an organic resin material (polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like) film can be used.

The characteristics of the TFT thus obtained showed good values. FIG. 13 shows the TFT characteristics (VI characteristics). In particular, since the structure of the present invention is a dual gate structure, the S value shows an excellent value of 105.8 (mV / dec). Further, by adopting the structure of the present invention, the threshold value (Vth) indicating the voltage value at the rising point in the VI characteristic graph is 0.946 V when Vd = 0.1 V, and Vd = 5 V. In some cases, it is 0.886 V, and the difference is as very small as 0.06. It can be said that the smaller this difference is, the more the short channel effect is suppressed. Further, the mobility (μ _FE ) is excellent at 220 (cm ² / Vs).

  This embodiment is characterized in that the scanning line 502a is formed in a different layer from the gate electrode and the capacitive electrode 502b is formed in the same layer as the scanning line 502a in order to improve the aperture ratio and increase the storage capacitance. Yes. An example of the pixel configuration of the present invention is shown in FIGS.

  14 is equivalent to FIG. 15A, and the schematic cross-sectional structure cut along the BB ′ dotted line is FIG. 15B. It corresponds to.

  In FIG. 14, the gate electrode 506 is patterned in an island shape and is connected to the scanning line 502a through a contact hole 500c formed in the insulating film. The semiconductor film 504 is connected to the signal line 509 through the contact hole 500a. The semiconductor film 504 is connected to the electrode 510 through the contact hole 500b. A region of the semiconductor film in contact with the signal line 509 or the electrode 510 is called a source region or a drain region. In addition, a channel formation region is formed between the source region and the drain region, and a gate electrode 506 exists over the channel formation region with a gate insulating film interposed therebetween. For simplification, the source region, the drain region, and the channel formation region are not shown.

  In this embodiment, when the scan line 502a is formed below the gate electrode 506 as shown in FIG. 14, the scan line 502a is provided below the semiconductor film 504, so that it can function as a light shielding film. is there. In addition, the storage capacitor is formed such that the lower electrode is a semiconductor film, the insulating film covering the semiconductor film is a dielectric, and the upper electrode is a capacitor wiring 507. Note that the storage capacitor may be increased by partially thinning an insulating film covering the semiconductor film.

  Furthermore, as shown in FIG. 15, the storage capacitor of this embodiment can also form a storage capacitor using the insulating film 503 as a dielectric for the capacitor electrode 502b connected to the capacitor wiring 507. Therefore, the storage capacitor can be efficiently secured, and the contrast of the liquid crystal display device using this pixel structure is improved.

  In addition, according to the configuration of this embodiment, the TFT of each pixel can have a dual gate structure in which a gate electrode is provided above and below the channel formation region via an insulating film, and the first insulating film is appropriately formed. By setting the film thickness to be small, the TFT characteristics can be improved while suppressing parasitic capacitance formed by the scanning lines and other wirings.

  The manufacturing method of the pixel structure shown in this embodiment is almost the same as that of Embodiment 1 or Embodiment 4, and the description thereof is omitted here.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 4.

  In this embodiment, when the pixel size is reduced, the aperture ratio is improved and the storage capacitor is increased. This embodiment is characterized in that a storage capacitor is formed by a light shielding film and a pixel electrode.

  FIG. 16 is a cross-sectional structure diagram showing an outline of the liquid crystal display device of the present embodiment. In FIG. 16, 601 is a substrate (TFT substrate), 602 is a scanning line, 603 is a first insulating film, 604 is a semiconductor film, 605 is a gate insulating film (second insulating film), 606b is a gate electrode, and 606c is a gate wiring. 606a is a capacitor wiring, 607 is a third insulating film, 608 is connected to the semiconductor film 604 through a contact hole formed in the third insulating film, and is an electrode for connecting the TFT and the pixel electrode 612.

  Reference numeral 609 denotes a fourth insulating film covering the TFT, 610 a light-shielding film for preventing light degradation of the TFT, 611 a fifth insulating film, 612 a pixel electrode connected to the electrode 608 through a contact hole, and 613 a liquid crystal layer 614. Is an alignment film for orienting.

  In FIG. 16, the counter electrode 616 and the alignment film 615 are provided on the counter substrate 617, but a light shielding film and a color filter may be provided as necessary.

  As shown in FIG. 16, in the storage capacitor of this example, the insulating film 605 is a dielectric, the first storage capacitor formed by the capacitor wiring 606a and the semiconductor film 604, and the insulating film 611 is a dielectric. A second storage capacitor formed by the light shielding film 610 and the pixel electrode 612 is configured. Note that as the insulating film 611, an organic resin film may be used, or an inorganic insulating film such as a silicon oxynitride film or a silicon oxide film may be used, and the thickness may be appropriately designed by a practitioner.

  For example, even when the pixel size is 14 μm × 14 μm, the cross-sectional structure shown in FIG. 16 is used, and a sufficient storage capacity (about 100 fF) is ensured by designing the top view as shown in FIG. And an aperture ratio of 48.7%.

  17A is a top view when the electrode 608 is formed, and FIG. 17B is a top view when the light shielding film 610 and the pixel electrode 612 are further formed. The same code | symbol was used for the location corresponding to 16. FIG.

  Note that this embodiment can be freely combined with any one of Embodiments 1 to 5.

The figure which shows a pixel top view. The figure which shows the circuit diagram of a TFT substrate. The figure which shows a cross-section figure. FIG. 3 is a cross-sectional structure diagram of an active matrix liquid crystal display device. The figure which shows the external appearance of AM-LCD. FIG. 14 illustrates an example of an electronic device. FIG. 14 illustrates an example of an electronic device. 10A and 10B are a manufacturing process cross-sectional view and a top view of a pixel portion. 10A and 10B are a manufacturing process cross-sectional view and a top view of a pixel portion. 10A and 10B are a manufacturing process cross-sectional view and a top view of a pixel portion. 10A and 10B are a manufacturing process cross-sectional view and a top view of a pixel portion. 10A and 10B are a manufacturing process cross-sectional view and a top view of a pixel portion. The figure which shows TFT characteristics. The figure which shows a pixel top view. The figure which shows a cross-section figure. The figure which shows a cross-section figure. The figure which shows a pixel top view. FIG. The figure which shows the conventional pixel opening area | region.

Claims (26)

A first wiring on an insulating surface;
A first insulating film on the first wiring;
A semiconductor film on the first insulating film;
A second insulating film on the semiconductor film;
A second wiring on the second insulating film; a gate electrode connected to the first wiring;
A third insulating film on the second wiring and the gate electrode;
A semiconductor device comprising: a third wiring connected to the semiconductor film on the third insulating film.   2. The semiconductor device according to claim 1, wherein the semiconductor film and the second wiring overlap with each other with the second insulating film interposed therebetween. 3. The storage capacitor according to claim 1, wherein a storage capacitor having the second insulating film as a dielectric is formed in a region where the second wiring and the semiconductor film overlap with each other through the second insulating film. A featured semiconductor device.   4. The semiconductor device according to claim 1, wherein an impurity element imparting a conductivity type is added to a region of the semiconductor film that overlaps with the second wiring with the second insulating film interposed therebetween. A semiconductor device.   5. The semiconductor device according to claim 1, further comprising: an electrode in contact with the semiconductor film; and a pixel electrode connected to the electrode over the third insulating film.   6. The semiconductor device according to claim 1, wherein the first wiring is disposed in a direction orthogonal to the second wiring.   7. The semiconductor device according to claim 1, wherein the first wiring is disposed in a direction orthogonal to the third wiring.   8. The semiconductor device according to claim 1, wherein the gate electrode is formed in a different layer from the first wiring.   9. The semiconductor device according to claim 1, wherein the gate electrode is patterned in an island shape.   10. The semiconductor device according to claim 1, wherein the first wiring is a scanning line.   The semiconductor device according to claim 1, wherein the second wiring is a capacitor wiring.   12. The semiconductor device according to claim 1, wherein the third wiring is a signal line.   13. The semiconductor device according to claim 1, wherein the second insulating film is a gate insulating film. 14. The element according to claim 1, wherein the gate electrode is made of an element selected from poly-Si, W, WSi _x , Al, Ta, Cr, or Mo doped with an impurity element imparting a conductivity type. A semiconductor device comprising a film as a main component or a laminated film thereof. A plurality of signal lines connected to the signal line driving circuit and arranged in parallel with each other at a predetermined interval;
A plurality of scanning lines connected to the scanning line driving circuit and arranged in parallel with each other at a predetermined interval;
A semiconductor device having a capacitor wiring arranged in parallel with the signal line.   16. The semiconductor device according to claim 15, wherein the scanning line is orthogonal to the signal line.   17. The semiconductor device according to claim 16, further comprising: a thin film transistor having a gate electrode connected to a scanning line orthogonal to the signal line; and a pixel electrode connected to the transistor.   18. The semiconductor device according to claim 15, wherein the gate electrode is formed in a different layer from the scanning line.   19. The semiconductor device according to claim 15, wherein the gate electrode is patterned in an island shape. A first step of forming a first wiring on a substrate having an insulating surface;
A second step of forming a first insulating film on the first wiring;
A third step of forming a semiconductor film on the first wiring;
A fourth step of forming a second insulating film on the semiconductor film;
A fifth step of forming a first contact hole reaching the first wiring by selectively etching the first insulating film and the second insulating film;
A sixth step of forming a gate electrode connected to the first wiring through the first contact hole and overlapping a part of the semiconductor film on the second insulating film;
A seventh step of forming a third insulating film on the gate electrode;
An eighth step of selectively etching the second insulating film and the third insulating film to form a second contact hole reaching the semiconductor film;
And a ninth step of forming a third wiring connected to the semiconductor film through the second contact hole on the third insulating film.   21. The method for manufacturing a semiconductor device according to claim 20, wherein a second wiring which overlaps with part of the semiconductor film is formed over the second insulating film in the same step as the gate electrode.   22. The method according to claim 20, further comprising a step of partially thinning the second insulating film overlapping the second wiring after the step of forming the second insulating film on the semiconductor film. A method for manufacturing a semiconductor device. 23. The method for manufacturing a semiconductor device according to claim 20, wherein the second insulating film is a gate insulating film.   24. The method for manufacturing a semiconductor device according to claim 20, wherein the first wiring is a scanning line.   25. The method for manufacturing a semiconductor device according to claim 20, wherein the second wiring is a capacitor wiring.   26. The method for manufacturing a semiconductor device according to claim 20, wherein the third wiring is a signal line.

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