JPH10276362A - Digital signal processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the distribution of system clock without mixing any noise into signals to be exchanged between units and increasing power consumption by generating a clock having the highest frequency dividing ratio among clocks required for respective units, distributing this clock as a reference clock to the respective units and doubling its frequency at the respective units. SOLUTION: A reference clock R at the same frequency as a low frequency clock T among system clocks S and T or the like required for plural units (such as CCD unit 2, Video unit 3 and CPU unit 4) is generated by a clock generating circuit 5 and distributed to the respective units. At the CCD unit 2 and Video unit 3 requiring the system clock, the system clock is respectively generated by doubling the frequency of reference clock R through a frequency double circuit 6 and these units are operated by this clock. Besides, the CPU unit 4 requiring the clock T is operated by using the reference clock R as the clock T.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing system, and more particularly to a system clock distribution used in a television camera system.

[0002]

2. Description of the Related Art Conventionally, digital signal processing, N
In a TSC (National Television System Committee) television camera device, for example, in the case of a system using a 400,000 pixel CCD (Charge Coupled Device), the frequency of a system clock S for driving the CCD and operating various circuits is as follows. , 14.318 MHz. In this case, as shown in FIG. 2, the clock generation circuit 5 of the signal generation unit (SG unit) 1 generates 14.318 MHz as the system clock S, and
Unit 2, Video unit 3, CPU unit 4
Distributed to Here, the distributed system clock S
, The CCD unit 2 and the Video unit 3 use the system clock S as it is and are driven by this clock. Further, C operating on the divided clock T of the distributed system clock S
The PU unit 4 divides the frequency of the system clock S by the frequency dividing circuit 7 and is driven by the divided frequency clock T.

As described above, the highest frequency among the clocks required for driving and operating each unit is distributed to each unit as a system clock S, and each unit divides the system clock S as necessary. Then, each unit is driven and operated by an optimum clock. In recent years, HDTV (High Definit
In the case of a system that drives and operates a 2 million pixel CCD, a system clock S is 74.25 MHz.
, And it is expected that the system clock S will become faster in the future.

[0004]

In the above apparatus,
When an HDTV television camera apparatus is to be realized, if the system clock S is set to 74.25 MHz and distributed to each unit, noise caused by the system clock S jumps into a video signal or the like transmitted between the units, CMOS (Compleme) for system clock S
ntary Metal Oxide Semiconductor) or TTL (Transi
There is a problem that transmission at the stor-transistor logic level becomes difficult, or a problem that power consumption increases because all units operate with the system clock S. The present invention solves these problems and provides a system clock S
When distributing to each unit, there is no increase in power consumption and noise mixing in signals transmitted between units.
It is intended to realize a system capable of distributing a system clock.

[0005]

According to the present invention, in order to achieve the above object, in a system constituted by a plurality of units including a digital signal processing unit, the most frequency-divided clock among the clocks required by each unit is used. Means for generating a clock having a large ratio and distributing the generated clock as a reference clock to the respective units; and means for reproducing the clock having a frequency required by the unit by multiplying the reference clock by the predetermined unit. And the reference clock having a low frequency is distributed to each unit. As a result, the frequency of the reference clock distributed to each unit can be reduced, and it is possible to reduce noise contamination and power consumption in signals transmitted between the units.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, the configuration and operation of clock distribution between main units when applied to an HDTV television camera apparatus will be described below with reference to FIG. Since the configuration and operation of the television camera device are well known, the description of the configuration and operation of parts not directly related to the present invention will be omitted.
Reference numeral 1 denotes a signal generation unit (SG unit) for generating a reference clock and a synchronization signal used in the device; 2, a CCD unit for converting a captured image into an electric signal; 3, various kinds of video signals converted by the CCD unit 2. A signal processing unit (Video unit) for performing signal processing, 4 is an SG unit, a CPU unit for controlling the CCD unit 2 and the Video unit 3, and 5 is a clock for generating a reference clock R used in the device and distributing it to each unit. A generating circuit 6 is a frequency-multiplying circuit that generates a system clock S required by the CCD unit 2 and the video unit 3 from the reference clock R, and T is a clock T for operating the CPU unit 4.

In the SG unit 1, the CCD unit 2,
System clock S required by Video unit 3
(Clock frequency: 74.25 MHz) and the clock T required by the CPU unit 4 (clock frequency: 18.5)
625 MHz = 74.25 MHz / 4), the clock generation circuit 5 generates a reference clock R having the same frequency as the low frequency clock T. Then, the generated reference clock R (clock frequency: 18.5625 MHz) is distributed to each unit. Here, the CCD unit 2 and the Video unit 3, which require the system clock S (clock frequency: 74.25 MHz), multiply the reference clock R (clock frequency: 18.5625 MHz) four times by the frequency multiplier 6, and System clock S (clock frequency: 7
4.25 MHz) and operates with this clock. Further, the CPU unit 4 requiring the clock T
Operate using the distributed reference clock R as the clock T.

As described above, the clock having the highest frequency division ratio among the clocks required by each unit is distributed to each unit as the reference clock R of the device, and each unit needs the reference clock R. , The reference clock R distributed to each unit
, The clock frequency becomes lower, so that noise mixing and power consumption in signals transmitted between the units can be reduced. In this embodiment, the camera system that drives and operates a 2 million pixel CCD in the HDTV system has been described. However, the present invention is not limited to this, and the NTSC system and the EDTVII that drive a high pixel CCD are not limited thereto.
The present invention can be similarly applied to a system having a higher definition than the HDTV system expected in the future, and can also be applied to a system which operates by distributing a clock other than a camera system.

[0009]

According to the present invention, the clock frequency of the reference clock distributed to each unit constituting various systems is reduced, and the frequency of the distributed reference clock is doubled as necessary in each unit. In addition, since a clock required by each unit is obtained, it is possible to reduce noise contamination and power consumption in a signal transmitted between the units.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is a block diagram showing a conventional configuration.

[Explanation of symbols]

1: SG unit, 2: CCD unit, 3: Video
o unit, 4: CPU unit, 5: clock generation circuit, 6: frequency doubler, R: reference clock, S: system clock, T: CPU clock.

Claims (2)

[Claims] In a system constituted by a plurality of units including a digital signal processing unit, a clock having the largest frequency division ratio among clocks required by each unit is generated, and this is used as a reference clock. Means for distributing to the unit, and means for reproducing the clock of a frequency required by the unit by multiplying the reference clock by the predetermined unit,
A digital signal processing system, wherein the reference clock having a low frequency is distributed. 2. A digital signal processing system according to claim 1, wherein said digital signal processing system is a digital signal processing television camera system.